Intel® Xeon Phi™ Processor Datasheet - Volume 2 - Registers December 2016 Reference Number: 335265-001US IntelLegal Lines and Disclaimerstechnologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. 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All Rights Reserved. 2 Intel® Xeon Phi™ Processor Datasheet - Volume 2 December 2016 Contents 1 Registers Overview and Configuration Processor..................................................... 19 1.1 Platform Configuration Structure ......................................................................... 19 1.1.1 Processor IIO Devices (CPUBUSNO (0))..................................................... 19 1.1.2 Processor Uncore Devices (CPUBUSNO (1) & CPUBUSNO (2))....................... 20 1.2 Configuration Registers Rules.............................................................................. 22 1.2.1 CSR Access ........................................................................................... 22 1.2.2 Memory-Mapped I/O Registers ................................................................. 26 1.3 Terminology ..................................................................................................... 26 1.4 Register Terminology ......................................................................................... 28 1.5 Notational Conventions ...................................................................................... 30 2On Package IO (OPIO) Registers ............................................................................. 31 2.1 Bus: 2, Devices: 23, Function: 4 (CFG) ................................................................ 31 2.1.1 VID_2_23_4_CFG................................................................................... 31 2.1.2 DID_2_23_4_CFG .................................................................................. 32 2.1.3 PCICMD_2_23_4_CFG............................................................................. 32 2.1.4 PCISTS_2_23_4_CFG.............................................................................. 33 2.1.5 RID_2_23_4_CFG................................................................................... 33 2.1.6 CCR_2_23_4_CFG .................................................................................. 34 2.1.7 CLSR_2_23_4_CFG ................................................................................ 34 2.1.8 PLAT_2_23_4_CFG ................................................................................. 34 2.1.9 HDR_2_23_4_CFG.................................................................................. 34 2.1.10 BIST_2_23_4_CFG ................................................................................. 35 2.1.11 CAPPTR_2_23_4_CFG ............................................................................. 35 2.1.12 INTL_2_23_4_CFG ................................................................................. 35 2.1.13 INTPIN_2_23_4_CFG .............................................................................. 35 2.1.14 MINGNT_2_23_4_CFG ............................................................................ 35 2.1.15 MAXLAT_2_23_4_CFG............................................................................. 36 2.2 Bus: 2, Device: 24, Function: 4 (CFG).................................................................. 36 2.2.1 VID_2_24_4_CFG................................................................................... 36 2.2.2 DID_2_24_4_CFG .................................................................................. 37 2.2.3 PCICMD_2_24_4_CFG............................................................................. 37 2.2.4 PCISTS_2_24_4_CFG.............................................................................. 37 2.2.5 RID_2_24_4_CFG................................................................................... 38 2.2.6 CCR_2_24_4_CFG .................................................................................. 38 2.2.7 CLSR_2_24_4_CFG ................................................................................ 38 2.2.8 PLAT_2_24_4_CFG ................................................................................. 39 2.2.9 HDR_2_24_4_CFG.................................................................................. 39 2.2.10 BIST_2_24_4_CFG ................................................................................. 39 2.2.11 CAPPTR_2_24_4_CFG ............................................................................. 39 2.2.12 INTL_2_24_4_CFG ................................................................................. 39 2.2.13 INTPIN_2_24_4_CFG .............................................................................. 39 2.2.14 MINGNT_2_24_4_CFG ............................................................................ 40 3 Memory Controller (MC) Registers........................................................................... 41 3.1 Bus: 2, Device: 10, Function: 0 (CFG).................................................................. 43 3.1.1 MAXLAT_2_10_0_CFG............................................................................. 43 3.1.2 PXPCAP_KDMI ....................................................................................... 43 3.1.3 PXPENHCAP_KDMI.................................................................................. 44 3.1.4 scrb0_cfg .............................................................................................. 44 3.1.5 scrb1_cfg .............................................................................................. 45 3.1.6 scrb2_cfg .............................................................................................. 45 3.1.7 scrb3_cfg .............................................................................................. 45 Intel® Xeon Phi™ Processor 3 Datasheet - Volume 2, December 2016 3.1.8 scrb4_cfg ..............................................................................................45 3.1.9 scrb5_cfg ..............................................................................................45 3.1.10 scrb6_cfg ..............................................................................................46 3.1.11 scrb7_cfg ..............................................................................................46 3.2 Bus: 2, Device: 10, Function: 1 (CFG) ..................................................................46 3.2.1 VID_2_10_1_CFG ...................................................................................47 3.2.2 DID_2_10_1_CFG...................................................................................47 3.2.3 PCICMD_2_10_1_CFG .............................................................................47 3.2.4 PCISTS_2_10_1_CFG ..............................................................................48 3.2.5 RID_2_10_1_CFG ...................................................................................49 3.2.6 CCR_2_10_1_CFG ..................................................................................49 3.2.7 CLSR_2_10_1_CFG .................................................................................49 3.2.8 PLAT_2_10_1_CFG .................................................................................49 3.2.9 HDR_2_10_1_CFG ..................................................................................49 3.2.10 BIST_2_10_1_CFG..................................................................................50 3.2.11 SVID_MCXKDRWDBU_CFG.......................................................................50 3.2.12 CAPPTR_2_10_1_CFG .............................................................................50 3.2.13 INTL_2_10_1_CFG..................................................................................50 3.2.14 INTPIN_2_10_1_CFG ..............................................................................50 3.2.15 MINGNT_2_10_1_CFG.............................................................................51