Accelerating Innovation Through Education

Accelerating Innovation In the Era of Exponentials

Dr. Chi-Foon Chan President and co-Chief Executive Officer, Synopsys, Inc.

August 27, 2013

Technology

The Future Ahead

~8,195 Employees

~4,431 Masters/ PhD Degrees Verification IP Implementation

~31% R&D/Revenue

~5,129 R&D Engineers Manufacturing ~1,100 Application Consultants

~1,889 Issued Patents Advanced Technology Leadership

Delivers Benefits at Every Node © Synopsys 2013 ASQED© Synopsys 2013 3 What Happens in 204 Million Emails Sent

>2 Million Search Queries

6 Million Facebook Views

1.3 Million Video Views And the Future Growth is Exponential Today, the number of the global networked devices = population By 2017, the number of devices the global as high as connected to IP networks will be 3x population © Synopsys 2013 ASQED© Synopsys 2013 4 Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2013 and Intel SmartTech Blog Moore’s Law Continues…

Transistor Count Trends 1.0E+12

256Gb MLC/128Gb SLC  DRAM 128Gb MLC/64Gb SLC 1.0E+11 NAND Flash (SLC) 64Gb

NAND Flash (MLC) 16Gb 8Gb 1.0E+10  Intel PC MPU 4Gb "Poulson"  4Gb 2Gb Intel Server MPU "Tukwila" "Broadwell" 1Gb Itanium 2 "Ivy Bridge" 1.0E+9 "Gulftown" Core i7 "Bloomfield" 256Mb Itanium 2 Core 2 Duo 64Mb 1.0E+8 Pentium 4 "Prescott" Itanium Pentium 4 16Mb Pentium III 1.0E+7 4Mb Pentium II Pentium Pro Pentium 1.0E+6 1Mb 80486 256Kb 80386 64Kb Transistors per Die Transistors 1.0E+5 80286 16Kb 4Kb 8086 1.0E+4 1Kb 8085 8080 8008 4004 1.0E+3

1.0E+2 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 04 06 08 10 12 14F 16F Year Source: Intel, SIA, IC Insights 2012 © Synopsys 2013 ASQED 5 Designs Are Larger and Faster

60,000 800 MHz

700 50,000

600

40,000 500

30,000 400

300 20,000 Clock Frequency Clock

Gate Count, K Count, Gates Gate 200

10,000 100

0 0 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 Expon. (Gate Count, K Gates) Expon. (Clock Frequency, MHz)

Source: Synopsys Global User Survey, 2002-2012 © Synopsys 2013 ASQED 6 Power Is a Growing Problem

1000 Leakage Power

800 Dynamic Power

2 600 W/cm 400

200

0 90nm 65nm 40nm 28nm 20nm

Source: IBS © Synopsys 2013 ASQED 7 Functional Verification Costs Are Exploding

$6.0B Engineering Effort

IT Infrastructure for Verification $5.0B

$4.0B

$3.0B

$2.0B

$1.0B

$0.0B 2011 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 Source: VCS User Companies, Synopsys © Synopsys 2013 ASQED 8 Chip Development Costs Are Increasing

$300 Chip Design $250 Software Dev. +116% $200

$150

+82% ($M) Cost $100 +96%

$50 +44% +75% +62% +54% $0 65nm (90M) 45/40nm (130M) 28nm (180M) 22/20nm (240M) 16/14nm (310M)

Feature Dimension (Transistor Count)

Source: IBS, December 2012 © Synopsys 2013 ASQED 9 Advanced Designs at Every Node

1st to tapeout at 1st to tapeout at 1st to tapeout at 1st to tapeout at 22/20nm 500 65nm 45/40nm 32/28nm

450

400

350

300

250

200

150

100

0 Q3'03 Q4'03 Q1'04 Q2'04 Q3'04 Q4'04 Q1'05 Q2'05 Q3'05 Q4'05 Q1'06 Q2'06 Q3'06 Q4'06 Q1'07 Q2'07 Q3'07 Q4'07 Q1'08 Q2'08 Q3'08 Q4'08 Q1'09 Q2'09 Q3'09 Q4'09 Q1'10 Q2'10 Q3'10 Q4'10 Q1'11 Q2'11 Q3'11 Q4'11 Q1'12 Q2'12 Q3'12 Q4'12 Q1'13 Q2'13

90nm Advanced Tapeout Counts 65nm 45/40nm 32/28nm 22/20nm 16/14nm © Synopsys 2013 10nm ASQED 10 08 09 10 11 12 Companies Working Hard to Differentiate

Recession

Recovery

Uncertainty

© Synopsys 2013 ASQED© Synopsys 2013 11 Semi Snapshot as of 7/23/2013 Source: IC Insights Report, August 02, 2013. © Synopsys 2013 ASQED 12 Source: IC Insights Report, August 02, 2013. © Synopsys 2013 ASQED 13 Buys

Buys

Forces Driving Buys - Wireless Consolidation Buys

Buys Semiconductor • Critical Mass Buys MODEM

Shaping Buys

• Differentiation the Buys Industry • Collaboration Buys Buys

Buys Accelerating Buys Buys

Innovation Buys

TechnologyTechnology

The Future Ahead

Traditional Flow

Software Development

Software Stack Product Support & Maintenance Synopsys Hardware Integration Development & Test Virtual Effort Development Prototype Time to Market Time in Market

With Virtual Prototyping Higher Prototype Productivity A simulation model for the targeted hardware Software Earlier Higher Integration TTM Quality & Test

Development Effort Development Hardware Product Support & Maintenance

Time to Market Time in Market

Graphics Application Processors Application Application Graphic RAM RAM ROM Processor CPU CPU Core(s) LVDS, Etc

Specialty I/O Specialty I/O

Flash Flash Storage RAM RAM RAM RAM Interface Memory I/Fs

On-Chip Bus DDR DDR memory

On-Chip Bus Interface & Others RAM RAM RAM RAM Memories & Logic Libraries Basic Peripherals (UARTs/Timers) Headset Jack Analog Interfaces Audio Microphone Interface / Video Audio Codecs I/F Data Video Codecs Converters Deeply Analog embedded USB PCIe SATA HDMI MIPI processors * Small boxes are standard cell library elements. © Synopsys 2013 ASQED 18 3rd Party IP Usage Will Continue Increasing Design to Double Through 2017

Complexity 2017 2012

Consumer

Escalating Design Costs Wireless Communication

Data Processing Shorter Time Window for New Product Overall 3rd party Automotive design IP use Launch in 2012

Industrial

Overall 3rd party design IP use Strong Growth Wired Communication in 2017 in 3rd Party 0% 15% 30% 45% 60% 75% 90% IP Usage Percentage of 3rd Party IP Block

Source: Gartner, Semi IP Market, March 2013

2002 2005 2009 2011 2012 “Correlation” “Look-Ahead” “In-Design” “Exploration” “Co-Design”

Synthesis Synthesis Synthesis Synthesis Synthesis

Design Planning Place & Place & Place & Place & Signoff Signoff Signoff Signoff Signoff Custom Place & Route Route Route Route Route

DRC / LVS DRC / LVS DRC / LVS DRC / LVS DRC / LVS

FinFET Double Patterning (DPT)

• Density / • Power Integration • Performance • Performance • Power

Power Area

3D-IC Delivering • Density / Integration More Performance • Power Performance with Less Power • Performance in a Smaller Area

Process Develop. Characterization Design Implementation IP

TCAD Circuit Simulation Custom Design Implementation

>= DPT spacing

C 1

V0 C2

C 3

Trench M0 Contact

Fin C4 Gate Fin Sourc Drain e

C5 Substrate

3D Lithography Extraction Physical Verification Signoff

Multi-Voltage Power Gating DVFS, AVFS SoC Design (Shutdown) Advanced multi-voltage Requires techniques

Advanced Well Biasing Clock Gating Low-VDD Mainstream Standby intent-driven

EN FF techniques LT Low Power CLK ICG

Techniques Gate-Level Opt. Architect. Opt. Multi--Threshold

THTH Synthesis-based c LowLow VV 16 bit 64 bit d optimization Ripple 90 366 CLA 100 405 THTH Leakage Current techniques Leakage Current Nominal V Carry Skip 108 437

THTH a High V c Carry Select 161 711

b DelayDelay Carry Save 218 1323

d Basic

Heavy Setup and Debug Activity Heavy Regression Activity Issue is Engr. Resource and Time Issue is Compute Cost and Time

2 3 1 Verification Debug Faster Reuse Automation Simulation

Project Time Bugs Found Compute Cycles

Technology Must Address • Performance • Digital • Capacity • Low-Power • Accuracy • AMS • Productivity • HW/SW • Standards

Collaboration 1. Industry The Era of Electronics 2. University 3. Government Technology

The Future Ahead

June 2, 2012 Economist.com

California becomes latest state to OK driverless cars September 25, 2012

Sources: USA TODAY, California becomes latest state to OK driverless cars, September 25, 2012. The Economist, Look, no hands, September 1, 2012. © Synopsys 2013 ASQED 29 The New Green Hub Shifting Gears to Sustainable Development

Source: Ecofriend.com – Urban Reforestation: Sky-bridges & green connectors to give a new skyline to Kuala Lumpur © Synopsys 2013 ASQED 30 Purpose + Plan + Our Part How will we impact the future and accelerate innovation?

Economy Technology

Environmental

Legal, Ethical

Responsibility