Informatyka 1, Studia Niestacjonarne I Stopnia Dr Inż

Total Page:16

File Type:pdf, Size:1020Kb

Informatyka 1, Studia Niestacjonarne I Stopnia Dr Inż Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 2/59 Plan wykładu nr 5 Informatyka 1 Język C § pętla for, operatory ++ i – Klasyfikacja systemów komputerowych (Flynna) Architektura von Neumanna i architektura harwardzka Politechnika Białostocka --WydziałWydział Elektryczny Budowa komputera § jednostka centralna Elektrotechnika, semestr II, studia niestacjonarne I stopnia § płyta główna Rok akademicki 2018/2019 § procesor (mikroarchitektury) Wykład nr 5 (05.04.2019) dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 3/59 Rok akademicki 2018/2019, Wykład nr 5 4/59 Język C --sumasuma kolejnych 10 liczb: 1+2+…+10 Język C --sumasuma kolejnych 100 liczb: 1+2+…+100 Suma wynosi: 55 Suma wynosi: 5050 #include <stdio.h> #include <stdio.h> int main(void ) int main(void ) { { int suma; int suma=0, i; suma = 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10; for (i=1; i<=100; i=i+1) suma = suma + i; printf("Suma wynosi: %d\n" ,suma); printf("Suma wynosi: %d\n" ,suma); return 0; } return 0; } Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 5/59 Rok akademicki 2018/2019, Wykład nr 5 6/59 Język C --pętlapętla for Język C --pętlapętla for Najczęściej stosowana postać pętli for for (wyr1; wyr2; wyr3) wyr1 instrukcja int i; for (i = 0; i < 10; i = i + 1) NIE wyr 2 ≠ 0 instrukcja wyr1 , wyr2 , wyr3 - dowolne wyrażenia w języku C TAK Instrukcja zostanie wykonana 10 razy Instrukcja: instrukcja (dla i = 0, 1, 2, … 9 ) § prosta - jedna instrukcja Funkcje pełnione przez wyrażenia zakończona średnikiem wyr3 § złożona - jedna lub kilka instrukcji objętych nawiasami klamrowymi for (inicjalizacja ;test ;aktualizacja ) instrukcja Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 7/59 Rok akademicki 2018/2019, Wykład nr 5 8/59 Język C --pętlapętla for (wyświetlenie tekstu) Język C --pętlapętla for (suma liczb: 1 + 2 + … + N) Programowanie nie jest trudne Suma 1234 liczb to 761995 #include <stdio.h> #include <stdio.h> Programowanie nie jest trudne Programowanie nie jest trudne #define N 1234 int main(void ) Programowanie nie jest trudne { Programowanie nie jest trudne int main(void ) int i; { int i, suma=0; for (i=0; i<5; i=i+1) printf("Programowanie nie jest trudne\n"); for (i=1; i<=N; i++) suma = suma + i; return 0; } printf( "Suma %d liczb to %d\n" , N, suma); return 0; } Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 9/59 Rok akademicki 2018/2019, Wykład nr 5 10/59 Język C --pętlapętla for (przykłady) Język C --pętlapętla for (przykłady) for (i=0; i<10; i++) 0 1 2 3 4 5 6 7 8 9 for (i=1; i<10; i=i+2) 1 3 5 7 9 printf( "%d ",i); printf( "%d ",i); for (i=0; i<10; i++) 1 2 3 4 5 6 7 8 9 10 for (i=10; i>0; i--) 10 9 8 7 6 5 4 3 2 1 printf( "%d ",i+1); printf( "%d ",i); for (i=1; i<=10; i++) 1 2 3 4 5 6 7 8 9 10 for (i=-9; i<=9; i=i+3) -9 -6 -3 0 3 6 9 printf( "%d ",i); printf( "%d ",i); Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 11/59 Rok akademicki 2018/2019, Wykład nr 5 12/59 Język C --pętlapętla for (break, continuecontinue)) Język C --pętlapętla for (najczęstsze błędy) W pętli for można stosować instrukcje skoku: break i continue Postawienie średnika na końcu pętli for int i; int i; 10 for (i=0; i<10; i++); for (i=1; i<10; i++) § continue przerywa bieżącą printf("%d ",i); { if (i%2==0) iterację i przechodzi do obliczania wyr3 continue ; Przecinki zamiast średników pomiędzy wyrażeniami if (i%7==0) break ; int i; printf("%d\n" ,i); § break przerywa for (i=0, i<10, i++) } wykonywanie pętli printf("%d ",i); Błąd kompilacji! 1 3 5 error C2143: syntax error : missing ';' before ')' Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 13/59 Rok akademicki 2018/2019, Wykład nr 5 14/59 Język C --pętlapętla for (najczęstsze błędy) Język C --pętlapętla nieskończona Błędny warunek - brak wykonania instrukcji for (wyr1; wyr2; wyr3) instrukcja int i; for (i=0; i>10; i++) printf("%d ",i); Wszystkie wyrażenia ( wyr1 , wyr2 , wyr3 ) w pętli for są opcjonalne Błędny warunek - pętla nieskończona for ( ; ; ) instrukcja - pętla nieskończona int i; 1 2 3 4 5 6 7 8 9 ... for (i=1; i>0; i++) W przypadku braku wyr2 przyjmuje się, że jest ono prawdziwe printf("%d ",i); Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 15/59 Rok akademicki 2018/2019, Wykład nr 5 16/59 Język C --zagnieżdżaniezagnieżdżanie pętli for Język C --operatoroperator inkrementacji (++) Jako instrukcja w pętli for może występować kolejna pętla for Jednoargumentowy operator ++ zwiększa wartość zmiennej o 1 (nie wolno stosować go do wyrażeń) int i, j; Operator ++ może występować jako przedrostek lub przyrostek for (i=1; i<=3; i++) // p ętla zewn ętrzna for (j=1; j<=2; j++) // p ętla wewn ętrzna printf ("i: %d j: % d\n",i,j ); Zapis Nazwa Znaczenie wartość zmiennej jest modyfikowana ++x preinkrementacji przed jej użyciem i: 1 j: 1 wartość zmiennej jest modyfikowana i: 1 j: 2 x++ postinkrementacji i: 2 j: 1 po użyciu jej poprzedniej wartości i: 2 j: 2 i: 3 j: 1 i: 3 j: 2 Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 17/59 Rok akademicki 2018/2019, Wykład nr 5 18/59 Język C --operatoroperator inkrementacji (++) Język C --operatoroperator inkrementacji (++) Przykład Miejsce umieszczenia operatora ++ nie ma znaczenia w przypadku instrukcji typu: int x = 1, y; int x = 1, y; y = 2 * ++x; y = 2 * x++; x++; równoważne x = x + 1; ++x; Kolejność operacji Nie należy stosować operatora ++ do zmiennych pojawiających się ++ x x = 2 2 * x 2 * 1 w wyrażeniu więcej niż jeden raz 2 * ++x 2 * 2 y = 2 * x y = 2 y = 2 * ++x y = 4 x++ x = 2 x = x++; x = ++x; Wartości zmiennych Zgodnie ze standardem języka C wynik powyższych instrukcji x = 2 y = 4 x = 2 y = 2 jest niezdefiniowany Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 19/59 Rok akademicki 2018/2019, Wykład nr 5 20/59 Język C --operatoroperator dekrementacji ((----)) Język C --priorytetpriorytet operatorów ++ i ---- Jednoargumentowy operator -- zmniejsza wartość zmiennej o 1 Priorytet Operator / opis (nie wolno stosować go do wyrażeń) 1 ++ -- (przyrostki) () [] . -> Operator -- może występować jako przedrostek lub przyrostek ++ -- (przedrostki) sizeof (typ) 2 + - ! ~ * & (jednoargumentowe) Zapis Nazwa Znaczenie 3 * / % wartość zmiennej jest modyfikowana --x predekrementacji 4 + - (dwuargumentowe) przed jej użyciem 5 << >> wartość zmiennej jest modyfikowana x-- postdekrementacji 6 < > <= >= po użyciu jej poprzedniej wartości 7 == != 8 & (bitowy) 9 ^ Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 21/59 Rok akademicki 2018/2019, Wykład nr 5 22/59 Klasyfikacja systemów komputerowych Taksonomia Flynna Taksonomia Flynna - pierwsza, najbardziej ogólna klasyfikacja architektur komputerowych (1972): § Flynn M.J.: „Some Computer Organizations and Their Effectiveness”, IEEE Transactions on Computers, Vol. C-21, No 9, 1972. SI - Single instruction Opiera się na liczbie przetwarzanych strumieni rozkazów i strumieni danych: MI - Multiple Instruction SD - Single Data § strumień rozkazów (Instruction Stream) - odpowiednik licznika rozkazów; system złożony z n procesorów posiada n liczników MD - Multiple Data rozkazów, a więc n strumieni rozkazów § strumień danych (Data Stream) - zbiór operandów, np. system SM - Shared Memory rejestrujący temperaturę mierzoną przez n czujników posiada n DM - Distributed Memory strumieni danych Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 23/59 Rok akademicki 2018/2019, Wykład nr 5 24/59 SISD (Single InstructionInstruction,, Single Data) SISD (Single InstructionInstruction,, Single Data) Jeden wykonywany program Komputer Komputer przetwarza jeden strumień danych IBM PC/AT PCPC Klasyczne komputery zbudowane według architektury von Neumanna SISD Zawierają: § jeden procesor § jeden blok pamięci operacyjnej - instrukcje zawierający wykonywany program. - dane Laptop - wyniki Komputer PCPC Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Informatyka 1, studia niestacjonarne I stopnia dr inż. Jarosław Forenc Rok akademicki 2018/2019, Wykład nr 5 25/59 Rok akademicki 2018/2019, Wykład nr 5 26/59 SIMD (Single InstructionInstruction,, Multiple Data) -SIMD SM-SIMD --KomputerySMKomputery wektorowe Jeden wykonywany program CDC CDC 1 -1-yarC yarC przetwarza wiele strumieni Cyber 205 (1976) danych (1981) Te same operacje wykonywane są na różnych danych SIMD Podział: § SM-SIMD (Shared Memory SIMD): - instrukcje 2 -2-yarC yarC - komputery wektorowe - dane (1985) Hitachi - rozszerzenia strumieniowe procesorów - wyniki 36S00 36S00 (MMX, 3DNow!, SSE, SSE2, SSE3, AVX, …) (1994) § DM-SIMD (Distributed Memory SIMD): - tablice procesorów - procesory kart graficznych (GPGPU ) Informatyka 1, studia niestacjonarne I stopnia dr inż.
Recommended publications
  • Microcode Revision Guidance August 31, 2019 MCU Recommendations
    microcode revision guidance August 31, 2019 MCU Recommendations Section 1 – Planned microcode updates • Provides details on Intel microcode updates currently planned or available and corresponding to Intel-SA-00233 published June 18, 2019. • Changes from prior revision(s) will be highlighted in yellow. Section 2 – No planned microcode updates • Products for which Intel does not plan to release microcode updates. This includes products previously identified as such. LEGEND: Production Status: • Planned – Intel is planning on releasing a MCU at a future date. • Beta – Intel has released this production signed MCU under NDA for all customers to validate. • Production – Intel has completed all validation and is authorizing customers to use this MCU in a production environment.
    [Show full text]
  • Class-Action Lawsuit
    Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys.
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • The Intel X86 Microarchitectures Map Version 2.0
    The Intel x86 Microarchitectures Map Version 2.0 P6 (1995, 0.50 to 0.35 μm) 8086 (1978, 3 µm) 80386 (1985, 1.5 to 1 µm) P5 (1993, 0.80 to 0.35 μm) NetBurst (2000 , 180 to 130 nm) Skylake (2015, 14 nm) Alternative Names: i686 Series: Alternative Names: iAPX 386, 386, i386 Alternative Names: Pentium, 80586, 586, i586 Alternative Names: Pentium 4, Pentium IV, P4 Alternative Names: SKL (Desktop and Mobile), SKX (Server) Series: Pentium Pro (used in desktops and servers) • 16-bit data bus: 8086 (iAPX Series: Series: Series: Series: • Variant: Klamath (1997, 0.35 μm) 86) • Desktop/Server: i386DX Desktop/Server: P5, P54C • Desktop: Willamette (180 nm) • Desktop: Desktop 6th Generation Core i5 (Skylake-S and Skylake-H) • Alternative Names: Pentium II, PII • 8-bit data bus: 8088 (iAPX • Desktop lower-performance: i386SX Desktop/Server higher-performance: P54CQS, P54CS • Desktop higher-performance: Northwood Pentium 4 (130 nm), Northwood B Pentium 4 HT (130 nm), • Desktop higher-performance: Desktop 6th Generation Core i7 (Skylake-S and Skylake-H), Desktop 7th Generation Core i7 X (Skylake-X), • Series: Klamath (used in desktops) 88) • Mobile: i386SL, 80376, i386EX, Mobile: P54C, P54LM Northwood C Pentium 4 HT (130 nm), Gallatin (Pentium 4 Extreme Edition 130 nm) Desktop 7th Generation Core i9 X (Skylake-X), Desktop 9th Generation Core i7 X (Skylake-X), Desktop 9th Generation Core i9 X (Skylake-X) • Variant: Deschutes (1998, 0.25 to 0.18 μm) i386CXSA, i386SXSA, i386CXSB Compatibility: Pentium OverDrive • Desktop lower-performance: Willamette-128
    [Show full text]
  • The Intel X86 Microarchitectures Map Version 2.2
    The Intel x86 Microarchitectures Map Version 2.2 P6 (1995, 0.50 to 0.35 μm) 8086 (1978, 3 µm) 80386 (1985, 1.5 to 1 µm) P5 (1993, 0.80 to 0.35 μm) NetBurst (2000 , 180 to 130 nm) Skylake (2015, 14 nm) Alternative Names: i686 Series: Alternative Names: iAPX 386, 386, i386 Alternative Names: Pentium, 80586, 586, i586 Alternative Names: Pentium 4, Pentium IV, P4 Alternative Names: SKL (Desktop and Mobile), SKX (Server) Series: Pentium Pro (used in desktops and servers) • 16-bit data bus: 8086 (iAPX Series: Series: Series: Series: • Variant: Klamath (1997, 0.35 μm) 86) • Desktop/Server: i386DX Desktop/Server: P5, P54C • Desktop: Willamette (180 nm) • Desktop: Desktop 6th Generation Core i5 (Skylake-S and Skylake-H) • Alternative Names: Pentium II, PII • 8-bit data bus: 8088 (iAPX • Desktop lower-performance: i386SX Desktop/Server higher-performance: P54CQS, P54CS • Desktop higher-performance: Northwood Pentium 4 (130 nm), Northwood B Pentium 4 HT (130 nm), • Desktop higher-performance: Desktop 6th Generation Core i7 (Skylake-S and Skylake-H), Desktop 7th Generation Core i7 X (Skylake-X), • Series: Klamath (used in desktops) 88) • Mobile: i386SL, 80376, i386EX, Mobile: P54C, P54LM Northwood C Pentium 4 HT (130 nm), Gallatin (Pentium 4 Extreme Edition 130 nm) Desktop 7th Generation Core i9 X (Skylake-X), Desktop 9th Generation Core i7 X (Skylake-X), Desktop 9th Generation Core i9 X (Skylake-X) • New instructions: Deschutes (1998, 0.25 to 0.18 μm) i386CXSA, i386SXSA, i386CXSB Compatibility: Pentium OverDrive • Desktop lower-performance: Willamette-128
    [Show full text]
  • 2 Basic Compiler Optimizations.Pdf
    What’s New for Intel compilers 19.1? Advance Support for Intel® Architecture – Use Intel compiler to generate optimized code for Intel Atom® processor through Intel® Xeon® Scalable processor and Intel® Xeon Phi™ processor families Achieve Superior Parallel Performance – Vectorize & thread your code (using OpenMP*) to take full advantage of the latest SIMD-enabled hardware, including Intel® Advanced Vector Extensions 512 (Intel® AVX-512) What’s New in C++ What’s New in Fortran Initial C++20, and full C++ 17 enabled Substantial Fortran 2018 support ▪ Enjoy advanced lambda and constant expression support ▪ Enjoy enhanced C-interoperability features for effective mixed language ▪ Standards-driven parallelization for C++ developers development Initial OpenMP* 5.0, and full OpenMP* 4.5 ▪ Use advanced coarray features to parallelize your modern Fortran code support Initial OpenMP* 5.0, and substantial OpenMP* 4.5 ▪ Modernize your code by using the latest parallelization support specifications ▪ Customize your reduction operations by user-defined reductions 2 Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Common optimization options Linux* Disable optimization -O0 Optimize for speed (no code size increase) -O1 Optimize for speed (default) -O2 High-level loop optimization -O3 Create symbols for debugging -g Multi-file inter-procedural optimization -ipo Profile guided optimization (multi-step build) -prof-gen -prof-use Optimize for speed across the entire program (“prototype switch”) -fast same as: fast options definitions changes over time! -ipo –O3 -no-prec-div –static –fp-model fast=2 -xHost) OpenMP support -qopenmp Automatic parallelization -parallel Optimization Notice Copyright © 2020, Intel Corporation.
    [Show full text]
  • Microcode Revision Guidance April2 2018 MCU Recommendations the Following Table Provides Details of Availability for Microcode Updates Currently Planned by Intel
    microcode revision guidance april2 2018 MCU Recommendations The following table provides details of availability for microcode updates currently planned by Intel. Changes since the previous version are highlighted in yellow. LEGEND: Production Status: • Planning – Intel has not yet determined a schedule for this MCU. • Pre-beta – Intel is performing early validation for this MCU. • Beta – Intel has released this production signed MCU under NDA for all customers to validate. • Production – Intel has completed all validation and is authorizing customers to use this MCU in a production environment. • Stopped – After a comprehensive investigation of the microarchitectures and microcode capabilities for these products, Intel has determined to not release microcode updates for these products for one or more reasons including, but not limited to the following: • Micro-architectural characteristics that preclude a practical implementation of features mitigating Variant 2 (CVE-2017-5715) • Limited Commercially Available System Software support • Based on customer inputs, most of these products are implemented as “closed systems” and therefore are expected to have a lower likelihood of exposure to these vulnerabilities. Pre-Mitigation Production MCU: • For products that do not have a Production MCU with mitigations for Variant 2 (Spectre), Intel recommends using this version of MCU. This does not impact mitigations for Variant 1 (Spectre) and Variant 3 (Meltdown). STOP deploying these MCU revs: • Intel recommends to discontinue using these select versions of MCU that were previously released with mitigations for Variant 2 (Spectre) due to system stability issues. • Lines with “***” were previously recommended to discontinue use. Subsequent testing by Intel has determined that these were unaffected by the stability issues and have been re-released without modification.
    [Show full text]
  • Intel: Manufacturing, Chip Design Expertise Driving Innovation and Integration, Historic Change to Computers
    Intel: Manufacturing, Chip design Expertise Driving Innovation and Integration, Historic Change to Computers SAN FRANCISCO, Sep 22, 2009 (BUSINESS WIRE) -- Intel Corporation executives today said Moore's Law, driven by Intel's advances in 32 and 22 nanometer (nm)-manufacturing technologies, is leading to a broader and faster pace of "innovation and integration." Future Intel(R) Atom(TM), Core(R) and Xeon(R) processors and System on Chip (SoC) products will make computers smaller, smarter, more capable and easier to use. For example, among a number of other innovations on tap, Intel will integrate graphics into some of its future chip products for the first time ever. "Over the past 40 years, the opportunities enabled by Moore's Law have gone beyond just impressive performance increases," said Sean Maloney, executive vice president and general manager of the Intel Architecture Group. "The rapidly increasing number of transistors and processor instructions we add have made possible the integration of more and more capabilities and features within our processors. This has driven an incredible amount of innovation throughout the industry, with the real winners being the consumers, gamers and businesses which buy these Intel-based computers." Next Generation Processors - Westmere and Sandy Bridge In his Intel Developer Forum keynote, Maloney demonstrated a Westmere-based PC that showed a marked increase in responsiveness on simple, everyday tasks such as Web-surfing with multiple windows open. Moreover, Westmere is Intel's first 32nm processor, and historic in that it is the first-ever Intel processor to integrate graphics die right into the processor's package.
    [Show full text]
  • Intel I7 Core Processor – a New Order Processor Level
    © 2014 IJIRT | Volume 1 Issue 6 | ISSN : 2349-6002 Intel i7 core processor – A new order processor level Arpit Yadav ; Anurag Parmar; Abhishek Sharma Electronics and Communication Engineering ABSTRACT: The paper bestowed up here may be a higher and economical compactibility , advanced complete exposure to the exactly used technologies in response towards the users demand. Now, the Intel i7 core processor.Intel i7 processor may be a fresh question arise why solely Intel core? .. Intel on the market and latest core processor gift within the Penrynmicroarchitecture includes Core a pair of market. It uses all the new technologies gift with within family of the processors that was the primary thought the corporative world. it's redesigned by a high repetitive quality of software package technocrats so it's . Intel microarchitecture isbased on the 45nm subtle style of all of the core processors gift.Intel Core i7 fabrication method. this enables Intel to create the sometimes applies to any or all families of desktop and next performance vary of processorsthat apace portable computer 64-bit x86-64processors that uses the consumes similar or less power than the antecedently Westmere , Nehalaem , Ivy , Sandy Bridge and also the generation processors. Intel Core primarily may be a Haswell microarchitectures. The Core i7 complete brand that Intel uses for the assorted vary of middle principally targets all the business and high-end to high-end customers and business based mostly shopper markets for each desktop and portable microprocessors. Generally, processors computer computers, and is distinguished from the oversubscribed within the name of Core square (entry-level consumer)Core i3, (mainstream consumer) Core i5, and (server and workstation) Xeon brands.
    [Show full text]
  • Why Should Intel Channel Partners Transition to Sandy Bridge?
    Legal Notices and Important Information Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to: http://www.intel.com/products/processor_number Performance results are based on certain tests measured on specific computer systems. Any difference in system hardware, software or configuration will affect actual performance. Configurations: see Appendix A. For more information go to http://www.intel.com/performance Intel® Hyper-Threading Technology requires an Intel® HT Technology enabled system, check with your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel® Core™ i5-750. For more information including details on which processors support HT Technology, visit http://www.intel.com/info/hyperthreading Intel® Turbo Boost Technology requires a system with Intel® Turbo Boost Technology capability. Consult your PC manufacturer. Performance varies depending on hardware, software and system configuration. For more information, visit http://www.intel.com/technology/turboboost This document contains information on products in the design phase of development. For more information on Intel® Advanced Vector Extensions see http://software.intel.com/sites/avx/ Intel, the Intel logo, Intel Core, Core, Core Inside, are trademarks of Intel Corporation in the U.S. and other countries. All products, computer systems, dates, and figures specified are preliminary based on current
    [Show full text]
  • Camp Marketing Consultancy
    Camp Marketing Consultancy Power Dimensions of Economic Freedom. Law Int l Express Int l Express e e Understanding artificial acceleration - systematic concentration – targeted financial misappropriation iCore 9 Gulftown Desktop & Xeon Westmere EP 5600 Series 2 way Economic assessment calculated on Intel through press signal that is RICO Collusion by Model “Science is basically concerned with investigating how and why things are as they are. Science, in fact, is organized knowledge about the world, not organized knowledge about itself”. Stafford Beer, University of Manchester; Decision & Control, 1966 Mike Bruzzone, Camp Marketing Consultancy, [email protected], 415/250-4652 FTC Submission 7/23/2012 Camp Marketing Consultancy “The latest wave of new competition laws is taking place in countries where the domestic economy has some similarities to the United States when Competition law was first enacted. Many of these countries, like the United States of the 1890’s, have economies that are dominated by large firms. In the transitional economies, the giant firms tend to be leftovers from colonial governments, state enterprise formed by socialist governments, or government favoritism based on Crony capitalism. Regardless of the reasons for the dominance of these oversized firms they will not survive if they are disciplined by competitive market forces. As a result some of these firms are likely to fail when faced by market competition and competition laws, others will have to change dramatically in order to survive. The question of what institutions are necessary to create a market economy has provoked a great deal of discussion that is reflected in academic and popular literature.
    [Show full text]
  • Making the Most of Intel® Transactional Synchronisation Extensions
    Making the Most of Intel® Transactional Synchronisation Extensions 10 May 2016 Dr. Roman Dementiev Software and Services Group, Intel Legal Disclaimer and Optimization Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. All products, platforms, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance.
    [Show full text]