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(12) Patent Application Publication (10) Pub. No.: US 2011/0231717 A1 HUR Et Al

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(12) Patent Application Publication (10) Pub. No.: US 2011/0231717 A1 HUR Et Al US 20110231717A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2011/0231717 A1 HUR et al. (43) Pub. Date: Sep. 22, 2011 (54) SEMICONDUCTOR MEMORY DEVICE Publication Classification (76) Inventors: Hwang HUR, Kyoungki-do (KR): ( 51) Int. Cl. Chang-Ho Do, Kyoungki-do (KR): C. % CR Jae-Bum Ko, Kyoungki-do (KR); ( .01) Jin-Il Chung, Kyoungki-do (KR) (21) Appl. N 13A149,683 (52) U.S. Cl. ................................. 714/718; 714/E11.145 ppl. No.: 9 (22)22) FileFiled: Mavay 31,51, 2011 (57) ABSTRACT Related U.S. Application Data Semiconductor memory device includes a cell array includ (62) Division of application No. 12/154,870, filed on May ing a plurality of unit cells; and a test circuit configured to 28, 2008, now Pat. No. 7,979,758. perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a (30) Foreign Application Priority Data write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a Feb. 29, 2008 (KR) ............................. 2008-OO18761 wafer-level. O 2 FAD MoDE PE, FRS PWD PADX8 GENERATOR EAELER PEC 3. PD) PWDC CRECKCCES CKCKB RASCASECSCE SISTE CLOCKBUFFER CEE e EST CLK BSI RASCASECSCKE WREFB ESTE s ACTF 32 P 8:W 4. 38t.A 3. se. A(2) FIRST REFRESH AKE13A2) REFIREFA CONTROR ROWANC RSBSAApp.12BS ARS BA255612.ESE E L - ww.i. 33 EE 3. PE PWDA RAE7(3) ECS issi: OLREFB SECOND LAK:2) BSDT DATABUFFERG08 EABLER REFIREFA SECON REFRESH BSE Y ADDRC CONTROLLER BST YEADDK)) PWS Testaposs WKB811-12 BAADDICBAAD BSYBRST (88.11:12) "Of BST CLK 380 3. ESCE WAK8,9,1,2) TWB BISKCNAC BSRAS BWB2 E. S. BSCS TWBIS, YS S. ECODERIES HERE TESTGENERATOR PATTER ISOADDRESS - TWB7TWE8 GENERATOR BSF BS EN ROWANC BSI CIYMC Y ADDRE BSAAEK12) ESA (2. EAONC EIS YAOE) ESEA). Patent Application Publication US 2011/0231717 A1 e ISHI HH00030 Patent Application Publication Sep. 22, 2011 Sheet 2 of 18 US 2011/0231717 A1 FIG. 2A CLOCK CLOCK TRANSFER INVERSION UNIT CLOCKPULSE GENERATION CCKB RSTOCPUP pulse) UNIT FIG. 2B PWDD -1 154 156 158 CMD/ADD COMMAND PAD TRANSFER UNIT DELAY UNIT LATCH UNIT DCMD/ADD CCKB Patent Application Publication Sep. 22, 2011 Sheet 3 of 18 US 2011/0231717 A1 FIG. 2C -10 RAO3KO:13) 124 REFA D RAKO:12) ADDRESS TPTXREF D COUNTING UNIT PTXREF Patent Application Publication Sep. 22, 2011 Sheet 4 of 18 US 2011/0231717 A1 FIG. 2D -14 RAKO-6,1213) curs 1240 RNIRST REFADD-Tp BS,2. TPTXREF - PTXREF " RCNT 5 RCNT RAKA) X r R C N T R : K i . RAK1. 12411 RCNT RAK9) A. 1241 RCNT RAK8) RCNT RAIy RA 12414 RCNT RAK6) Patent Application Publication Sep. 22, 2011 Sheet 5 of 18 US 2011/0231717 A1 [69 []; 300|| Patent Application Publication Sep. 22, 2011 Sheet 6 of 18 US 2011/0231717 A1 Wij'0|| NETIS|8 Patent Application Publication Sep. 22, 2011 Sheet 7 of 18 US 2011/0231717 A1 VREFBI BIST EN D Patent Application Publication Sep. 22, 2011 Sheet 8 of 18 US 2011/0231717 A1 Patent Application Publication Sep. 22, 2011 Sheet 9 of 18 US 2011/0231717 A1 FIG.6A CLK KC D CKB D OB CKB CLK RST FIG.6B WDD RST C-Do CKKC Do CKB MUXOBD Patent Application Publication Sep. 22, 2011 Sheet 10 of 18 US 2011/0231717 A1 FIG. 6C Patent Application Publication Sep. 22, 2011 Sheet 11 of 18 US 2011/0231717 A1 Patent Application Publication Sep. 22, 2011 Sheet 12 of 18 US 2011/0231717 A1 FIG. 8A x -ox ---X sax xx xx x- axx xx xx x x X x &x xxxx xx wox xx xxx xxx xxx x-: X x& x x X x x Xx: x xxx & xxx xxx x--- BSLEN BIST CKEB ROWADDEN ROWADD END BAADDINC CASADDEN D. Do Do UsCasADED Autu BSLAADD. " Do-Do-DBISTDT ACTEN WTEN PREEN BKCMD ACTEN )--Do-Do-Do-DCM - - - - CMD CMD ADD AFREKO1) D BIST ADDKO1) ROWADDEND XA EN CASADDEND YAEN ADDMUX 392 BSTXAADD(O1) XA KO:1) VSS YA PUPBY CMD CMD ADD AFRE(2:12) D BIST ADDK2:12) ROWADDEND XAEN CASADDEND YAEN ADDMUX 394 BISTXAADDK2.12) XA (2:12) BISTYBADDKO7)YSSYSSYSS YA PUPBY PUPBY BK CMD CMD ADD BAFRECO2) D BIST BAKO2) WDD XAEN YAEN ADDMUX 396 BST YBADDK10:12) XA (O2) VSS YA PUPBY Patent Application Publication Sep. 22, 2011 Sheet 13 of 18 US 2011/0231717 A1 FIG. 8B -a CMDD XADDEN D-I DO O< XA D al D D-D-Do-DAD YADDEN D DO YAD in Patent Application Publication Sep. 22, 2011 Sheet 14 of 18 US 2011/0231717 A1 FIG. 9A PWOD CMD/ADDPAD DCMDIADO BIST EN FIG. 9B BUF OUT D-D . D OUT BIST CMDIADD Patent Application Publication Sep. 22, 2011 Sheet 15 of 18 US 2011/0231717 A1 FIG. 10A -so RAO3KO:13) 324 ROWAD. E O ). Xo-Do-REFAD RAKO:12(2) WSS O- Do-> FIRST ADDRESS PTXREF Do-D COUNTING UNIT BIST XRED BISTRST BISTXA RSTn TPTXREF D BISTEN D XACNTEN WSS YBCNT EN Do-Do 2-AND RAK60,127) (O:12) BISTXAADD(0:12) Patent Application Publication Sep. 22, 2011 Sheet 16 of 18 US 2011/0231717 A1 - Y - SSts." w a aw as a kca ty Ys or goes or cy t }}}}}{ld OG( | ISHINO |M ISHINO ISHINJT?TIS|8 Patent Application Publication Sep. 22, 2011 Sheet 17 of 18 US 2011/0231717 A1 FIG 11 / 330 332 RA47KO 13) ROW ADDRESS DECODING UNIT 334 Y|ADDI, E REFAD RAKO:12) BAADO.NC D SECONDADDRESS PTXREF TPTXR COUNTING UNIT BST YRED EF C BISTRST BISTYRST WSS XA CNT EN BST EN D YBCNT EN 3261 Do-Do 2-AND RAK5,0,127) (O:7) BISTYBADDKO:7) 3262 Do-Do 2-AND RAK11:10) KO:2) 3263 Do-Do 2-AND RAK97) KO2) BST YBADDKO:12) Patent Application Publication Sep. 22, 2011 Sheet 18 of 18 US 2011/0231717 A1 SOTIS|8 JMTIS|8 JNFINITIM US 2011/0231717 A1 Sep. 22, 2011 SEMCONDUCTOR MEMORY DEVICE equipment including a probe card, leading to an increase in test cost. Accordingly, a typical semiconductor memory CROSS-REFERENCE TO RELATED device should be operated within a range so as to consume the APPLICATIONS amount of current not exceeding a predetermined amount. 0006. In this way, to prevent the package from being dam 0001. The present invention claims priority of Korean aged due to overcurrent during TDBI process, semiconductor patent application number 10-2008-0018761 filed on Feb. 29, memory devices to be simultaneously tested should be lim 2008, which is incorporated by reference in its entirety. ited in number, and word lines to be simultaneously enabled in each semiconductor memory device through one-time BACKGROUND OF THE INVENTION active command is also limited in number. Resultingly, most 0002 The present invention relates to a semiconductor of time to be taken for a Subsequent process is used in the memory device, and more particularly, to a semiconductor TDBI process, and thus it is possible to disperse various tests memory device that reduces a test time for operation of the for a semiconductor memory device. However, the TDBI semiconductor memory device with high capacity, and a test process is not effective to reduce a test time notably. ing method of the semiconductor memory device. 0007 To test a semiconductor memory device more effec 0003. In a system with a variety of semiconductor devices, tively before packaging, a testing method has been proposed a semiconductor memory device serves as a data storage. The where a built-in self-test (BIST) circuit is built in the semi semiconductor memory device outputs data according to conductor memory device. In addition, to increase yield of a addresses received from a data processor, e.g., a central pro semiconductor memory device, another testing method has cessing unit (CPU), or stores data received from the data been introduced where a built-in self-repair (BISR) is built in processor into memory cells selected by addresses. the semiconductor memory device so as to repair defects 0004 As the operating speed of the system increases and detected through a wafer level burn-in (WBI) test, and this semiconductor integrated circuit technologies are advanced, method is increasingly applied to various fields. Herein, The semiconductor memory devices are required to input and BISR of the semiconductor memory device is accompanied output data at higher speed. In order for faster and stable with a variety of mechanisms such as built-in self-diagnostics operation of semiconductor memory devices, a variety of (BISD), built-in redundancy analysis (BIRA) as well as BIST. circuits inside the semiconductor memory devices must be 0008. This BIST suggested an alternative to solve prob able to operate at a high speed and transfer signals or data lems, e.g., limitation in channel, in the case of a testing between the circuits at a high speed. This causes a design and process using a conventional ATE. Since a test control circuit, fabrication of a semiconductor memory device to be complex, which is capable of realizing a memory test algorithm, is built and also causes a testing process of the fabricated semicon in the BIST circuit, a great number of ports for a channel to be ductor memory device to be complex and difficult. More connected to an external test equipment are not required, and specifically, the number of operations to be tested increases, operation of the semiconductor memory device can be tested and a testing procedure for each operation is also compli at a high speed.
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