Dsp56156 Overview

Freescale Semiconductor, Inc... MOTOROLA 1 - DSP56156 OVERVIEW Freescale Semiconductor,Inc. F o r M o r G e o I SECTION 1 n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc. SECTION CONTENTS 1.1 INTRODUCTION . 1-3 1.2 DSP56100 CORE BLOCK DIAGRAM DESCRIPTION . 1-5 1.3 MEMORY ORGANIZATION. 1-12 1.4 EXTERNAL BUS, I/O, AND ON-CHIP PERIPHERALS. 1-12 1.5 OnCE . 1-18 1.6 PROGRAMMING MODEL . 1-18 1.7 INSTRUCTION SET SUMMARY . 1-26 . c n I , r o t c u d n o c i m e S e l a c s e e r F 1 - 2 DSP56156 OVERVIEW MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. INTRODUCTION 1.1 INTRODUCTION This manual is intended to be used with the DSP56100 Family Manual (see Figure 1-1). The DSP56100 Family Manual provides a description of the components of the DSP56100 CORE56100 CORE processor (see Figure 1-2) which is common to all DSP56100 family processors (except for the DSP56116) and includes a detailed description of the basic DSP56100 CORE instruction set. The DSP56156 User’s Manual and DSP56166 User’s Manual (see Figure 1-1) provide a brief overview of the core processor and detailed descriptions of the memory and peripherals that are chip specific. A DSP561xx User’s Manual and a DSP561xx Technical Data Sheet will be available for any . future DSP56100 family member. Electrical specifications and timings for the DSP56156 . c can be found in the DSP56156 Technical Data Sheet. n I , r 16-bit 16-bit 16-bit Products o t DSP56156 DSP56166 DSP561xx c u d n o DSP56100 Family Manuals c • architecture i Family Manual • instructions m e S e l DSP56156 DSP56166 DSP561xx Device Manuals a User’s Manual User’s Manual User’s Manual • peripherals • memories c # DSP56156UM/AD # DSP56166UM/AD # DSP561xxUM/AD s e e r F DSP56156 DSP56166 DSP561xx Specifications Technical Data Technical Data Technical Data • electrical # DSP56156/D # DSP56166/D # DSP561xx/D • mechanical Figure 1-1 DSP56100 Family Product Literature MOTOROLA DSP56156 OVERVIEW 1 - 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... 1 -4 DSP56156OVERVIEW Freescale Semiconductor,Inc. F Table 1-1DSP56156FeatureList o r M o r G e o I n t INTRODUCTION f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , MOTOROLA Freescale Semiconductor, Inc. INTRODUCTION DSP56100 Family Features • Up to 30 Million Instructions per Second (MIPS) at • Three 16-bit internal data and three 16-bit internal 60 MHz.– 33.3 ns Instruction cycle address buses • Single-cycle 16 x 16-bit parallel Multiply- • Individual programmable wait states on the Accumulate external bus for program, and data • 2 x 40-bit accumulators with extension byte • On-chip memory-mapped peripheral registers • Fractional and integer arithmetic with support for • Low Power Wait and Stop modes multiprecision arithmetic • On-Chip Emulation (OnCE) for unobtrusive, • Highly parallel instruction set with unique DSP processor speed independent debugging addressing modes • Operating frequency down to DC • Nested hardware DO loops including infinite loops • 5V single power supply and DO zero loop • Low power (HCMOS) . • Two instruction LMS adaptive filter loop . • Fast auto-return interrupts c • Two external interrupt request pins n I , r o DSP56156 On-chip Resources — RAM Version t • 2K x 16 on-chip data RAM • 27 general purpose I/O pins c • 2K x 16 on-chip program RAM • On-chip, programmable, frequency synthesizer u • One bootstrap ROM (PLL) d • Bootstrap loading from external byte wide PROM, • Byte-wide Host Interface with DMA support n Host Interface, or Synchronous Serial Interface 0 • Two independent synchronous serial interfaces o (SSI0) – built in µ-law and A-law compression/expansion c i • One external 16-bit address bus – up to 32 software selectable time slots in • One external 16-bit data bus network mode m • On-chip peripheral registers memory mapped in • One 16-bit timer e data memory space • 112 pin quad flat pack packaging S Σ∆ • On-chip voice band codec (A/D-D/A) e – Internal voltage reference l – No off-chip components required a c s DSP56156ROM On-chip Resources e • 2K x 16 on-chip data RAM – Internal voltage reference (2/5 of positive power supply) e • 8K x 16 on-chip program ROM r • One external 16-bit address bus • 27 general purpose I/O pins F • One external 16-bit data bus • On-chip, programmable PLL • On-chip peripheral registers memory mapped in • Byte-wide Host Interface with DMA support data memory space • Two independent synchronous serial interfaces • On-chip Σ∆ voice band codec (A/D-D/A) • One 16-bit timer – No off-chip components required • 112 pin quad flat pack packaging Operational Differences of the ROM Based Part from the RAM Based Part • PROM area P:$2F00 — P:$2FFF is reserved and should not be programmed or accessed by the user MOTOROLA DSP56156 OVERVIEW 1 - 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56100 CORE BLOCK DIAGRAM DESCRIPTION XAB1 ADDRESS XAB2 EXTERNAL ADDRESS ADDRESS PAB BUS PORT B GENERATION SWITCH 16 UNIT OR HOST PORT A PORT 15 ON-CHIP PERIPHERALS BOOTSTRAP PROGRAM DATA HOST, SSI0, ROM RAM RAM BUS 8 7+12 SSI1, TIMER 64x16 2Kx16 2Kx16 CONTROL GPI/O, CODEC CODEC, PORT C XDB 16 INTERNAL DATA DATA . AND/OR BUS SWITCH EXTERNAL . PDB SSI0, SSI1, AND BIT DATA BUS . TIMER MANIPULATION SWITCH GDB c UNIT n I , EXTAL PROGRAM CONTROL UNIT CLOCK r SXFC AND PLL PROGRAM PROGRAM PROGRAM DATA ALU o CLKO ADDRESS DECODE INTERRUPT 16x16+40 - 40-BIT MAC t GENERATOR CONTROLLER CONTROLLER TWO 40-BIT ACCUMULATORS OnCE c u 4 MODA/IRQA d MODC MODB/IRQB n RESET 16 BITS o c i m Figure 1-2 Detailed RAM Based Part Block Diagram e S A general block diagram of the DSP56156 is shown in Figure 1-2 (see Section 3.2 for in- e formation on the ROM based part). The DSP56156 is optimized for applications such as l a medium to low bit rate speech encoding but can also be used in many other types of ap- c plications. s e Table 1-1 is a list of the DSP56156 primary features. The core features are common to e r any product using the DSP56100 CORE processor. F 1.2 DSP56100 CORE BLOCK DIAGRAM DESCRIPTION The heart of the DSP56156 architecture is a 16-bit multiple-bus core processor called the DSP56100 CORE and designed specifically for real-time digital signal processing (DSP). The overall architecture is presented here and can be seen in Figure 1-5. For a detailed description of the core processor, see the DSP56100 Family Manual. 1 - 6 DSP56156 OVERVIEW MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56100 CORE BLOCK DIAGRAM DESCRIPTION XAB1 ADDRESS XAB2 EXTERNAL ADDRESS ADDRESS PAB BUS PORT B GENERATION SWITCH 16 UNIT OR HOST PROGRAM DATA MEMORY A PORT 15 ON-CHIP PERIPHERALS MEMORY HOST, RSSI0, PROM DATA RAM BUS 10 7+10 RSSI1, TIMER 12K x 16 2Kx16 CONTROL GPI/O, CODEC CODEC, . PORT C XDB 16 . AND/OR INTERNAL DATA DATA BUS SWITCH PDB EXTERNAL c RSSI0, AND BIT DATA BUS RSSI1, MANIPULATION SWITCH n UNIT GDB I TIMER , r o EXTAL PROGRAM CONTROL UNIT CLOCK t SXFC AND PLL PROGRAM PROGRAM PROGRAM DATA ALU CLKO ADDRESS DECODE INTERRUPT c 16x16+40 - 40-BIT MAC GENERATOR CONTROLLER CONTROLLER TWO 40-BIT ACCUMULATORS u OnCE d n 4 MODA/IRQA o MODB/IRQB c 16 BITS RESET MODC/IRQC i m e Figure 1-3 Detailed ROM Based Part Block Diagram S e l DSP56156 RAM Based Part DSP56156 ROM Based Part a c 64x16 s PROM e 2Kx16 12Kx16 2Kx16 e 2Kx16 XRAM r PROM XRAM PRAM F PLL PLL MOTOROLA SSI0 MOTOROLA SSI0 16-bit DSP 16-bit DSP SIGMA Core SSI1 SIGMA Core SSI1 DELTA DELTA CODEC HOST CODEC HOST TIMER TIMER OnCE OnCE Ext. Ext. BUS BUS Figure 1-4 DSP56156 RAM and ROM Based Functional Block Diagram MOTOROLA DSP56156 OVERVIEW 1 - 7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56100 CORE BLOCK DIAGRAM DESCRIPTION OMR SR INSTR DECODER and M0 N0 R0 LA LC INTERRUPT UNIT M1 N1 MOD. R1 ALU M2 N2 ALU R2 SP PC M3 N3 R3 SSH SSL PROGRAM CONTROLLER ADR ALU CLOCK Clock & Control GEN. XAB1 . XAB2 c PAB n PDB I GDB , XDB r o t LIMITER SHIFTER/LIMITER c u DATA ALU d n IBS and o BITFIELD UNIT Y1 Y0 X1 X0 A2 A1 A0 B2 B1 B0 c i MAC and OnCE m ALU e S e Figure 1-5 DSP56100 CORE Block Diagram l a 1.2.1 Data Buses c s Data movement on the chip occurs over three bidirectional 16-bit buses: the X Data Bus e (XDB), the Program Data Bus (PDB), and the Global Data Bus (GDB). Data transfer be- e r tween the Data ALU and the X Data Memory occurs over the XDB when one memory ac- F cess is performed, over the XDB and the GDB when two simultaneous memory reads are performed.

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