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Tms320c55x V3.X DSP Mnemonic Instruction Set C55x v3.x CPU Mnemonic Instruction Set Reference Guide Literature Number: SWPU067E June 2009 Preface Read This First About This Manual The C55x™ CPU is a fixed-point digital signal processor (DSP) in the TMS320™ family, and it can use either of two forms of the instruction set: a mnemonic form or an algebraic form. This book is a reference for the mnemonic form of the instruction set. It contains information about the instructions used for all types of operations. For information on the algebraic instruction set, see C55x v3.1 CPU Algebraic Instruction Set Reference Guide, SWPU068. Notational Conventions This book uses the following conventions. - In syntax descriptions, the instruction is in a bold typeface. Portions of a syntax in bold must be entered as shown. Here is an example of an instruction syntax: LMS Xmem, Ymem, ACx, ACy LMS is the instruction, and it has four operands: Xmem, Ymem, ACx, and ACy. When you use LMS, the operands should be actual dual data- memory operand values and accumulator values. A comma and a space (optional) must separate the four values. - Square brackets, [ and ], identify an optional parameter. If you use an optional parameter, specify the information within the brackets; do not type the brackets themselves. iii Related Documentation From Texas Instruments / Trademarks Related Documentation From Texas Instruments The following books describe the C55x™ devices and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477-8924. When ordering, please identify the book by its title and literature number. TMS320C55x Technical Overview (SPRU393). This overview is an introduction to the TMS320C55x™ digital signal processor (DSP). The TMS320C55x is the latest generation of fixed-point DSPs in the TMS320C5000™ DSP platform. Like the previous generations, this processor is optimized for high performance and low-power operation. This book describes the CPU architecture, low-power enhancements, and embedded emulation features of the TMS320C55x. C55x v3.x CPU Reference Guide (literature number SWPU073) describes the architecture, registers, and operation of the v 3.x CPU for the C55x™ . C55x v3.x CPU Algebraic Instruction Set Reference Guide (literature num- ber SWPU068) describes the algebraic instructions individually. It also includes a summary of the instruction set, a list of the instruction opcodes, and a cross-reference to the mnemonic instruction set. TMS320C55x Programmer’s Guide (literature number SPRU376) describes ways to optimize C and assembly code for the TMS320C55x™ DSPs and explains how to write code that uses special features and instructions of the DSP. TMS320C55x Optimizing C Compiler User’s Guide (literature number SPRU281) describes the TMS320C55x™ C Compiler. This C compiler accepts ANSI standard C source code and produces assembly language source code for TMS320C55x devices. TMS320C55x Assembly Language Tools User’s Guide (literature number SPRU280) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for TMS320C55x™ devices. Trademarks TMS320, TMS320C54x, TMS320C55x, C54x, and C55x are trademarks of Texas Instruments. iv Contents Contents 1 Terms, Symbols, and Abbreviations. 1-1 Lists and defines the terms, symbols, and abbreviations used in the TMS320C55x DSP mnemonic instruction set summary and in the individual instruction descriptions. 1.1 Instruction Set Terms, Symbols, and Abbreviations. 1-2 1.2 Instruction Set Conditional (cond) Fields. 1-7 1.3 Affect of Status Bits. 1-9 1.3.1 Accumulator Overflow Status Bit (ACOVx). 1-9 1.3.2 C54CM Status Bit. 1-9 1.3.3 CARRY Status Bit. 1-9 1.3.4 FRCT Status Bit. 1-9 1.3.5 INTM Status Bit. 1-9 1.3.6 M40 Status Bit. 1-10 1.3.7 RDM Status Bit. 1-12 1.3.8 SATA Status Bit. 1-12 1.3.9 SATD Status Bit. 1-13 1.3.10 SMUL Status Bit. 1-13 1.3.11 SXMD Status Bit. 1-13 1.3.12 Test Control Status Bit (TCx). 1-13 1.4 Instruction Set Notes and Rules. 1-14 1.4.1 Notes. 1-14 1.4.2 Rules. 1-14 1.5 Nonrepeatable Instructions. 1-21 2 Parallelism Features and Rules. 2-1 Describes the parallelism features and rules of the TMS320C55x DSP mnemonic instruction set. 2.1 Parallelism Features. 2-2 2.2 Parallelism Basics. 2-3 2.3 Resource Conflicts. 2-4 2.3.1 Operators. 2-4 2.3.2 Address Generation Units. 2-4 2.3.3 Buses. 2-5 2.4 Soft-Dual Parallelism. 2-5 2.4.1 Soft-Dual Parallelism of MAR Instructions. 2-6 2.5 Execute Conditionally Instructions. 2-6 v Contents 2.6 Other Exceptions. 2-7 3 Introduction to Addressing Modes. 3-1 Provides an introduction to the addressing modes of the TMS320C55x DSP. 3.1 Introduction to the Addressing Modes. 3-2 3.2 Absolute Addressing Modes. 3-3 3.2.1 k16 Absolute Addressing Mode. 3-3 3.2.2 k23 Absolute Addressing Mode. 3-3 3.2.3 I/O Absolute Addressing Mode. 3-3 3.3 Direct Addressing Modes. 3-4 3.3.1 DP Direct Addressing Mode. 3-4 3.3.2 SP Direct Addressing Mode. 3-5 3.3.3 Register-Bit Direct Addressing Mode. 3-5 3.3.4 PDP Direct Addressing Mode. 3-5 3.4 Indirect Addressing Modes. 3-6 3.4.1 AR Indirect Addressing Mode. 3-6 3.4.2 Dual AR Indirect Addressing Mode. 3-14 3.4.3 CDP Indirect Addressing Mode. 3-16 3.4.4 Coefficient Indirect Addressing Mode. 3-19 3.5 Circular Addressing. 3-21 4 Instruction Set Summary. 4-1 Summary of the TMS320C55x mnemonic instruction set. 5 Instruction Set Descriptions. 5-1 Detailed information on the TMS320C55x DSP mnemonic instruction set. AADD (Modify Auxiliary or Temporary Register Content by Addition). 5-2 AADD (Modify Data Stack Pointer). 5-6 AADD (Modify Extended Auxiliary Register Content by Addition). 5-7 ABDST (Absolute Distance). 5-9 ABS (Absolute Value). 5-11 ADD (Addition) . 5-14 ADD (Dual 16-Bit Additions). 5-35 ADD::MOV (Addition with Parallel Store Accumulator Content to Memory). 5-40 ADDSUB (Dual 16-Bit Addition and Subtraction). ..
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