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DSP56300 Family Manual

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DSP56300 Family Manual DSP56300 Family Manual 24-Bit Digital Signal Processor DSP56300FM/AD Revision 2.0, August 1999 OnCE and Mfax are trademarks of Motorola, Inc. Intel“ is a registered trademark of the Intel Corporation. All other trademarks are those of their respective owners. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative Action Employer. How to reach us: USA/Europe/Locations Not Listed: Asia/Pacific: Japan: Motorola Literature Distribution Motorola Semiconductors H.K. Ltd. Nippon Motorola Ltd P.O. Box 5405 8B Tai Ping Industrial Park SPD, Strategic Planning Office141 Denver, Colorado 80217 51 Ting Kok Road 4-32-1, Nishi-Gotanda 1 (800) 441-2447 Tai Po, N.T., Hong Kong Shinagawa-ku, Japan 1 (303) 675-2140 852-26629298 81-3-5487-8488 Motorola Fax Back System (Mfax™): Technical Resource Center: Internet: TOUCHTONE (602) 244-6609 1 (800) 521-6274 http://www.motorola-dsp.com/ 1 (800) 774-1848 [email protected] DSP Helpline [email protected] MOTOROLA INC., 1999 Contents Chapter 1 Introduction 1.1 Core Overview. 1-2 1.1.1 Data Arithmetic Logic Unit (Data ALU) . 1-2 1.1.2 Address Generation Unit (AGU) . 1-3 1.2 Program Control Unit (PCU). 1-4 1.3 On-chip Instruction Cache Controller . 1-5 1.4 Port A External Memory Interface . 1-6 1.5 Phase Lock Loop (PLL) and Clock Generator . 1-6 1.6 Hardware Debugging Support . 1-7 1.7 Direct Memory Access (DMA) . 1-7 1.8 Introduction to Digital Signal Processing . 1-8 1.9 Summary of Features. 1-11 1.10 Manual Organization . 1-12 Chapter 2 Core Architecture Overview 2.1 Core Buses . 2-2 2.2 Core Processing . 2-3 2.3 Processing States . 2-5 2.3.1 Normal Processing State. 2-5 2.3.2 Exception Processing State (Interrupt Processing). 2-6 2.3.2.1 Hardware Interrupt Source. 2-8 2.3.2.2 Software Interrupt Sources. 2-9 2.3.2.3 Interrupt Priority Structure. 2-9 2.3.2.4 Instructions Preceding the Interrupt Instruction Fetch. 2-12 2.3.2.5 Interrupt Types . 2-13 2.3.2.6 Interrupt Arbitration . 2-13 2.3.2.7 Interrupt Instruction Fetch . 2-14 2.3.2.8 Interrupt Instruction Execution . 2-14 2.3.3 Reset Processing State . 2-16 2.3.4 Wait Processing State . 2-17 2.3.5 Stop Processing State . 2-18 2.3.6 Debug State. 2-18 Motorola Contents iii Chapter 3 Data Arithmetic Logic Unit 3.1 Introduction . 3-1 3.2 Data ALU Architecture . 3-1 3.2.1 Data ALU Input Registers (X1, X0, Y1, Y0) . 3-3 3.2.2 Multiplier-Accumulator (MAC) Unit . 3-3 3.2.3 Data ALU Accumulator Registers (A2, A1, A0, B2, B1, B0) . 3-4 3.2.4 Accumulator Shifter. 3-5 3.2.5 Bit Field Unit (BFU) . 3-5 3.2.6 Data Shifter/Limiter. 3-5 3.2.6.1 Scaling . 3-6 3.2.6.2 Limiting . 3-6 3.3 Data ALU Arithmetic and Rounding. 3-7 3.3.1 Data Representation . 3-7 3.3.2 Rounding Modes. 3-8 3.3.2.1 Convergent Rounding . 3-8 3.3.2.2 Twos-Complement Rounding . 3-10 3.3.3 Arithmetic Saturation Mode . 3-11 3.3.4 Multiprecision Arithmetic Support. 3-12 3.3.4.1 Double-Precision Multiply Mode . 3-13 3.3.5 Block Floating-Point FFT Support . 3-14 3.4 Data ALU Programming Model . 3-15 3.5 Sixteen-Bit Arithmetic Mode . 3-15 3.5.1 Moves in Sixteen-Bit Arithmetic Mode . 3-16 3.5.1.1 Moves into Registers or Accumulators . 3-16 3.5.1.2 Moves from Registers or Accumulators . 3-17 3.5.1.3 Short Immediate moves . 3-19 3.5.1.4 Scaling and Limiting . 3-19 3.5.2 Sixteen-bit Arithmetic. 3-19 3.6 Pipeline Conflicts. 3-20 3.6.1 Arithmetic Stall. 3-21 3.6.2 Status Stall . 3-21 3.6.2.1 Transfer Stall. 3-22 Chapter 4 Address Generation Unit 4.1 AGU Architecture . 4-1 4.2 Sixteen-bit Compatibility Mode . 4-3 4.3 Programming Model . 4-4 Motorola DSP56300 Family Manual iv 4.3.1 Address Register Files . 4-4 4.3.2 Stack Extension Pointer . 4-5 4.3.3 Offset Register Files . 4-5 4.3.4 Modifier Register Files . 4-6 4.4 Addressing Modes . 4-6 4.4.1 Register Direct Modes . 4-7 4.4.2 Address Register Indirect Modes . 4-7 4.4.3 PC-relative Modes . 4-9 4.4.4 Special Address Modes. 4-9 4.5 Address Modifier Types . 4-10 4.5.1 Linear Modifier (Mn = $XXFFFF). 4-11 4.5.2 Reverse-Carry Modifier (Mn = $000000) . ..
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