Tms320c55x V3.X DSP Algebraic Instruction Set

Total Page:16

File Type:pdf, Size:1020Kb

Tms320c55x V3.X DSP Algebraic Instruction Set C55x v3.x CPU Algebraic Instruction Set Reference Guide Literature Number: SWPU068E June 2009 Preface Read This First About This Manual The C55x™ is a fixed-point digital signal processor (DSP) in the TMS320™ DSP family, and it can use either of two forms of the instruction set: a mnemonic form or an algebraic form. This book is a reference for the algebraic form of the instruction set. It contains information about the instructions used for all types of operations. For information on the mnemonic instruction set, see C55x v3.x CPU Mnemonic Instruction Set Reference Guide, SWPU067. This release is updated with the 3.0 Revision of the TMS320C55x DSP. Infor- mation not affected by the revision remains identical to the previous manual. The main new features of this revision are: - Relaxed parallelism restrictions: Total size of both instructions may be up to 8 bytes. Constant buses (KAB and KDB) are no longer a source of conflict. - New instructions: lsmf 36 dual mac instructions with double coefficient features MPY, MAC, and MAS instructions with unsigned coefficients lock iii Notational Conventions Notational Conventions This book uses the following conventions. - In syntax descriptions, the instruction is in a bold typeface. Portions of a syntax in bold must be entered as shown. Here is an example of an instruction syntax: lms(Xmem, Ymem, ACx, ACy) lms is the instruction, and it has four operands: Xmem, Ymem, ACx, and ACy. When you use lms, the operands should be actual dual data- memory operand values and accumulator values. A comma and a space (optional) must separate the four values. - Square brackets, [ and ], identify an optional parameter. If you use an optional parameter, specify the information within the brackets; do not type the brackets themselves. iv Related DocumentationRelated Documentation From Texas Instruments From Texas / TrademarksInstruments Related Documentation From Texas Instruments The following books describe the C55x™ devices and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477-8924. When ordering, please identify the book by its title and literature number. TMS320C55x Technical Overview (SPRU393). This overview is an introduction to the TMS320C55x™ digital signal processor (DSP). The TMS320C55x is the latest generation of fixed-point DSPs in the TMS320C5000™ DSP platform. Like the previous generations, this processor is optimized for high performance and low-power operation. This book describes the CPU architecture, low-power enhancements, and embedded emulation features of the TMS320C55x. C55x CPU Reference Guide (literature number SWPU073) describes the architecture, registers, and operation of the CPU for the TMS320C55x™ digital signal processors (DSPs). C55x CPU Mnemonic Instruction Set Reference Guide (literature number SWPU067) describes the mnemonic instructions individually. It also includes a summary of the instruction set, a list of the instruction opcodes, and a cross-reference to the algebraic instruction set. TMS320C55x Programmer’s Guide (literature number SPRU376) describes ways to optimize C and assembly code for the TMS320C55x™ DSPs and explains how to write code that uses special features and instructions of the DSP. TMS320C55x Optimizing C Compiler User’s Guide (literature number SPRU281) describes the TMS320C55x™ C Compiler. This C compiler accepts ANSI standard C source code and produces assembly language source code for TMS320C55x devices. TMS320C55x Assembly Language Tools User’s Guide (literature number SPRU280) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for TMS320C55x™ devices. Trademarks TMS320, TMS320C54x, TMS320C55x, C54x, and C55x are trademarks of Texas Instruments. v vi Contents Contents 1 Terms, Symbols, and Abbreviations. 1-1 Lists and defines the terms, symbols, and abbreviations used in the TMS320C55x DSP algebraic instruction set summary and in the individual instruction descriptions. 1.1 Instruction Set Terms, Symbols, and Abbreviations. 1-2 1.2 Instruction Set Conditional (cond) Fields. 1-7 1.3 Affect of Status Bits. 1-9 1.3.1 Accumulator Overflow Status Bit (ACOVx). 1-9 1.3.2 C54CM Status Bit. 1-9 1.3.3 CARRY Status Bit. 1-9 1.3.4 FRCT Status Bit. 1-9 1.3.5 INTM Status Bit. 1-9 1.3.6 M40 Status Bit. 1-10 1.3.7 RDM Status Bit. 1-12 1.3.8 SATA Status Bit. 1-12 1.3.9 SATD Status Bit. 1-13 1.3.10 SMUL Status Bit. 1-13 1.3.11 SXMD Status Bit. 1-13 1.3.12 Test Control Status Bit (TCx). 1-13 1.4 Instruction Set Notes and Rules. 1-14 1.4.1 Notes. 1-14 1.4.2 Rules. 1-14 1.5 Nonrepeatable Instructions. 1-20 2 Parallelism Features and Rules. 2-1 Describes the parallelism features and rules of the TMS320C55x DSP algebraic instruction set. 2.1 Parallelism Features. 2-2 2.2 Parallelism Basics. 2-3 2.3 Resource Conflicts. 2-4 2.3.1 Operators. 2-4 2.3.2 Address Generation Units. 2-4 2.3.3 Buses. 2-5 2.4 Soft-Dual Parallelism. 2-5 2.4.1 Soft-Dual Parallelism of MAR Instructions. 2-6 2.5 Execute Conditionally Instructions. 2-6 2.6 Other Exceptions. 2-7 vii Contents 3 Introduction to Addressing Modes. 3-1 Provides an introduction to the addressing modes of the TMS320C55x DSP. 3.1 Introduction to the Addressing Modes. 3-2 3.2 Absolute Addressing Modes. 3-3 3.2.1 k16 Absolute Addressing Mode. 3-3 3.2.2 k23 Absolute Addressing Mode. 3-3 3.2.3 I/O Absolute Addressing Mode. 3-3 3.3 Direct Addressing Modes. 3-4 3.3.1 DP Direct Addressing Mode. 3-4 3.3.2 SP Direct Addressing Mode. 3-5 3.3.3 Register-Bit Direct Addressing Mode. 3-5 3.3.4 PDP Direct Addressing Mode. 3-5 3.4 Indirect Addressing Modes. 3-6 3.4.1 AR Indirect Addressing Mode. 3-6 3.4.2 Dual AR Indirect Addressing Mode. 3-14 3.4.3 CDP Indirect Addressing Mode. 3-16 3.4.4 Coefficient Indirect Addressing Mode. 3-19 3.5 Circular Addressing. 3-21 4 Instruction Set Summary. 4-1 Provides a summary of the TMS320C55x DSP algebraic instruction set. 5 Instruction Set Descriptions. 5-1 Detailed information on the TMS320C55x DSP algebraic instruction set. Absolute Distance (abdst). 5-2 Absolute Value . 5-4 Addition . 5-7 Addition with Absolute Value. 5-27 Addition with Parallel Store Accumulator Content to Memory. 5-29 Addition or Subtraction Conditionally (adsc). ..
Recommended publications
  • AMD Athlon™ Processor X86 Code Optimization Guide
    AMD AthlonTM Processor x86 Code Optimization Guide © 2000 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of AMD’s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, AMD Athlon, K6, 3DNow!, and combinations thereof, AMD-751, K86, and Super7 are trademarks, and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
    [Show full text]
  • Benchmark Evaluations of Modern Multi Processor Vlsi Ds Pm Ps
    1220 Session 1220 Benchmark Evaluations of Modern Multi-Processor VLSI DSPµPs Aaron L. Robinson and Fred O. Simons, Jr. High-Performance Computing and Simulation (HCS) Research Laboratory Electrical Engineering Department Florida A&M University and Florida State University Tallahassee, FL 32316-2175 Abstract - The authors continue their tradition of presenting technical reviews and performance comparisons of the newest multi-processor VLSI DSPµPs with the intention of providing concise focused analyses designed to help established or aspiring DSP analysts evaluate the applicability of new DSP technology to their specific applications. As in the past, the Analog Devices SHARCTM and Texas Instruments TMS320C80 families of DSPµPs will be the focus of our presentation because these manufacturers continue to push the envelop of new DSPµPs (Digital Signal Processing microProcessors) development. However, in addition to the standard performance analyses and benchmark evaluations, the authors will present a new image-processing bench marking technique designed specifically for evaluating new DSPµP image processing capabilities. 1. Introduction The combination of constantly evolving DSP algorithm development and continually advancing DSPuP hardware have formed the basis for an exponential growth in DSP applications. The increased market demand for these applications and their required hardware has resulted in the production of DSPuPs with very powerful components capable of performing a wide range of complicated operations. Due to the complicated architectures of these new processors, it would be time consuming for even the experienced DSP analysts to review and evaluate these new DSPuPs. Furthermore, the inexperienced DSP analysts would find it even more time consuming, and possibly very difficult to appreciate the significance and opportunities for these new components.
    [Show full text]
  • (12) Patent Application Publication (10) Pub. No.: US 2011/0231717 A1 HUR Et Al
    US 20110231717A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2011/0231717 A1 HUR et al. (43) Pub. Date: Sep. 22, 2011 (54) SEMICONDUCTOR MEMORY DEVICE Publication Classification (76) Inventors: Hwang HUR, Kyoungki-do (KR): ( 51) Int. Cl. Chang-Ho Do, Kyoungki-do (KR): C. % CR Jae-Bum Ko, Kyoungki-do (KR); ( .01) Jin-Il Chung, Kyoungki-do (KR) (21) Appl. N 13A149,683 (52) U.S. Cl. ................................. 714/718; 714/E11.145 ppl. No.: 9 (22)22) FileFiled: Mavay 31,51, 2011 (57) ABSTRACT Related U.S. Application Data Semiconductor memory device includes a cell array includ (62) Division of application No. 12/154,870, filed on May ing a plurality of unit cells; and a test circuit configured to 28, 2008, now Pat. No. 7,979,758. perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a (30) Foreign Application Priority Data write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a Feb. 29, 2008 (KR) ............................. 2008-OO18761 wafer-level. O 2 FAD MoDE PE, FRS PWD PADX8 GENERATOR EAELER PEC 3. PD) PWDC CRECKCCES CKCKB RASCASECSCE SISTE CLOCKBUFFER CEE e EST CLK BSI RASCASECSCKE WREFB ESTE s ACTF 32 P 8:W 4. 38t.A 3. se. A(2) FIRST REFRESH AKE13A2) REFIREFA CONTROR ROWANC RSBSAApp.12BS ARS BA255612.ESE E L - ww.i. 33 EE 3. PE PWDA RAE7(3) ECS issi: OLREFB SECOND LAK:2) BSDT DATABUFFERG08 EABLER REFIREFA SECON REFRESH BSE Y ADDRC CONTROLLER BST YEADDK)) PWS Testaposs WKB811-12 BAADDICBAAD BSYBRST (88.11:12) "Of BST CLK 380 3.
    [Show full text]
  • Computer Architecture Out-Of-Order Execution
    Computer Architecture Out-of-order Execution By Yoav Etsion With acknowledgement to Dan Tsafrir, Avi Mendelson, Lihu Rappoport, and Adi Yoaz 1 Computer Architecture 2013– Out-of-Order Execution The need for speed: Superscalar • Remember our goal: minimize CPU Time CPU Time = duration of clock cycle × CPI × IC • So far we have learned that in order to Minimize clock cycle ⇒ add more pipe stages Minimize CPI ⇒ utilize pipeline Minimize IC ⇒ change/improve the architecture • Why not make the pipeline deeper and deeper? Beyond some point, adding more pipe stages doesn’t help, because Control/data hazards increase, and become costlier • (Recall that in a pipelined CPU, CPI=1 only w/o hazards) • So what can we do next? Reduce the CPI by utilizing ILP (instruction level parallelism) We will need to duplicate HW for this purpose… 2 Computer Architecture 2013– Out-of-Order Execution A simple superscalar CPU • Duplicates the pipeline to accommodate ILP (IPC > 1) ILP=instruction-level parallelism • Note that duplicating HW in just one pipe stage doesn’t help e.g., when having 2 ALUs, the bottleneck moves to other stages IF ID EXE MEM WB • Conclusion: Getting IPC > 1 requires to fetch/decode/exe/retire >1 instruction per clock: IF ID EXE MEM WB 3 Computer Architecture 2013– Out-of-Order Execution Example: Pentium Processor • Pentium fetches & decodes 2 instructions per cycle • Before register file read, decide on pairing Can the two instructions be executed in parallel? (yes/no) u-pipe IF ID v-pipe • Pairing decision is based… On data
    [Show full text]
  • Thread Scheduling in Multi-Core Operating Systems Redha Gouicem
    Thread Scheduling in Multi-core Operating Systems Redha Gouicem To cite this version: Redha Gouicem. Thread Scheduling in Multi-core Operating Systems. Computer Science [cs]. Sor- bonne Université, 2020. English. tel-02977242 HAL Id: tel-02977242 https://hal.archives-ouvertes.fr/tel-02977242 Submitted on 24 Oct 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Ph.D thesis in Computer Science Thread Scheduling in Multi-core Operating Systems How to Understand, Improve and Fix your Scheduler Redha GOUICEM Sorbonne Université Laboratoire d’Informatique de Paris 6 Inria Whisper Team PH.D.DEFENSE: 23 October 2020, Paris, France JURYMEMBERS: Mr. Pascal Felber, Full Professor, Université de Neuchâtel Reviewer Mr. Vivien Quéma, Full Professor, Grenoble INP (ENSIMAG) Reviewer Mr. Rachid Guerraoui, Full Professor, École Polytechnique Fédérale de Lausanne Examiner Ms. Karine Heydemann, Associate Professor, Sorbonne Université Examiner Mr. Etienne Rivière, Full Professor, University of Louvain Examiner Mr. Gilles Muller, Senior Research Scientist, Inria Advisor Mr. Julien Sopena, Associate Professor, Sorbonne Université Advisor ABSTRACT In this thesis, we address the problem of schedulers for multi-core architectures from several perspectives: design (simplicity and correct- ness), performance improvement and the development of application- specific schedulers.
    [Show full text]
  • Reconfigurable Accelerators in the World of General-Purpose Computing
    Reconfigurable Accelerators in the World of General-Purpose Computing Dissertation A thesis submitted to the Faculty of Electrical Engineering, Computer Science and Mathematics of Paderborn University in partial fulfillment of the requirements for the degree of Dr. rer. nat. by Tobias Kenter Paderborn, Germany August 26, 2016 Acknowledgments First and foremost, I would like to thank Prof. Dr. Christian Plessl for the advice and support during my research. As particularly helpful, I perceived his ability to communicate suggestions depending on the situation, either through open questions that give room to explore and learn, or through concrete recommendations that help to achieve results more directly. Special thanks go also to Prof. Dr. Marco Platzner for his advice and support. I profited especially from his experience and ability to systematically identify the essence of challenges and solutions. Furthermore, I would like to thank: • Prof. Dr. João M. P. Cardoso, for serving as external reviewer for my dissertation. • Prof. Dr. Friedhelm Meyer auf der Heide and Dr. Matthias Fischer for serving on my oral examination committee. • All colleagues with whom I had the pleasure to work at the PC2 and the Computer Engineering Group, researchers, technical and administrative staff. In a variation to one of our coffee kitchen puns, I’d like to state that research without colleagues is possible, but pointless. However, I’m not sure about the first part. • My long-time office mates Lars Schäfers and Alexander Boschmann for particularly extensive discussions on our research and far beyond. • Gavin Vaz, Heinrich Riebler and Achim Lösch for intensive and productive collabo- ration on joint research interests.
    [Show full text]
  • Dsp56156 Overview
    Freescale Semiconductor, Inc... MOTOROLA 1 - DSP56156 OVERVIEW Freescale Semiconductor,Inc. F o r M o r G e o I SECTION 1 n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc. SECTION CONTENTS 1.1 INTRODUCTION . 1-3 1.2 DSP56100 CORE BLOCK DIAGRAM DESCRIPTION . 1-5 1.3 MEMORY ORGANIZATION. 1-12 1.4 EXTERNAL BUS, I/O, AND ON-CHIP PERIPHERALS. 1-12 1.5 OnCE . 1-18 1.6 PROGRAMMING MODEL . 1-18 1.7 INSTRUCTION SET SUMMARY . 1-26 . c n I , r o t c u d n o c i m e S e l a c s e e r F 1 - 2 DSP56156 OVERVIEW MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. INTRODUCTION 1.1 INTRODUCTION This manual is intended to be used with the DSP56100 Family Manual (see Figure 1-1). The DSP56100 Family Manual provides a description of the components of the DSP56100 CORE56100 CORE processor (see Figure 1-2) which is common to all DSP56100 family processors (except for the DSP56116) and includes a detailed descrip- tion of the basic DSP56100 CORE instruction set. The DSP56156 User’s Manual and DSP56166 User’s Manual (see Figure 1-1) provide a brief overview of the core processor and detailed descriptions of the memory and peripherals that are chip specific.
    [Show full text]
  • Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task
    Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task Master thesis in Electronics Systems at Linköping Institute of Technology by VIVEK PACKIARAJ LiTH-ISY-EX--09/4089--SE Linköping 2008 Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task Master thesis in Electronics Systems at Linköping Institute of Technology by VIVEK PACKIARAJ LiTH-ISY-EX--09/4089--SE Linköping 2008 Supervisor: Kent Palmkvist ISY, Linköping Universitet. Examinator: Kent Palmkvist ISY, Linköping Universitet. Linköping, 4th November, 2008 Presentation Date Department and Division 04 – November - 2008 Department of Electrical Engineering Publishing Date (Electronic version) Electronics Systems Language Type of Publication ISBN (Licentiate thesis) X English Licentiate thesis ISRN LiTH-ISY-EX—09/4089—SE Other (specify below) Degree thesis Thesis C-level X Thesis D-level Title of series (Licentiate thesis) Report Number of Pages Other (specify below) 78 Series number/ISSN (Licentiate thesis) URL, Electronic Version http://www.ep.liu.se Publication Title Study, Design and Implementation of an Application Specific Instruction Set processor for Specific DSP Task Author Vivek Packiaraj Abstract There is a lot of literature already available describing well-structured approach for embedded design and implementation of Application Specific Integrated Processor (ASIP) micro processor core. This concept features hardware structured approach for implementation of processor core from minimal instruction set, encoding standards, hardware mapping, and micro architecture design, coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIP processor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR.
    [Show full text]
  • Characterizing X86 Processors for Industry-Standard Servers: AMD Opteron and Intel Xeon Technology Brief
    Characterizing x86 processors for industry-standard servers: AMD Opteron and Intel Xeon Technology brief Abstract.............................................................................................................................................. 3 Acronyms in text.................................................................................................................................. 3 Introduction......................................................................................................................................... 4 Micro-architectural similarities ............................................................................................................... 5 32-bit operations.............................................................................................................................. 5 64-bit operations.............................................................................................................................. 6 Instruction set and registers............................................................................................................ 6 Operating modes ......................................................................................................................... 7 Memory addressability.................................................................................................................. 8 Micro-architectural differences............................................................................................................... 8
    [Show full text]
  • DSP56300 Family Manual
    DSP56300 Family Manual 24-Bit Digital Signal Processor DSP56300FM/AD Revision 2.0, August 1999 OnCE and Mfax are trademarks of Motorola, Inc. Intel“ is a registered trademark of the Intel Corporation. All other trademarks are those of their respective owners. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative Action Employer. How to reach us: USA/Europe/Locations Not Listed: Asia/Pacific: Japan: Motorola Literature Distribution Motorola Semiconductors H.K. Ltd. Nippon Motorola Ltd P.O. Box 5405 8B Tai Ping Industrial Park SPD, Strategic Planning Office141 Denver, Colorado 80217 51 Ting Kok Road 4-32-1, Nishi-Gotanda 1 (800) 441-2447 Tai Po, N.T., Hong Kong Shinagawa-ku, Japan 1 (303) 675-2140 852-26629298 81-3-5487-8488 Motorola Fax Back System (Mfax™): Technical Resource Center: Internet: TOUCHTONE (602) 244-6609 1 (800) 521-6274 http://www.motorola-dsp.com/ 1 (800) 774-1848 [email protected] DSP Helpline [email protected] MOTOROLA INC., 1999 Contents Chapter 1 Introduction 1.1 Core Overview.
    [Show full text]
  • Exploring Early and Late Alus for Single-Issue In-Order Pipelines
    Exploring Early and Late ALUs for Single-Issue In-Order Pipelines Alen Bardizbanyan and Per Larsson-Edefors Chalmers University of Technology, Gothenburg, Sweden [email protected], [email protected] Abstract—In-order processors are key components in energy- end of data memory access stage. This way all dependencies efficient embedded systems. One important design aspect of in- between load operations and ALU operations are eliminated. order pipelines is the sequence of pipeline stages: First, the But since ALU operations happen late, stall cycles will be position of the execute stage, in which arithmetic logic unit (ALU) operations and branch prediction are handled, impacts the num- caused if the address generation unit (AG) needs the result of ber of stall cycles that are caused by data dependencies between the ALU immediately. In addition, branch resolution is delayed data memory instructions and their consuming instructions and which increases the misprediction latency. by address generation instructions that depend on an ALU result. Designing a CPU pipeline is a complex process that in- Second, the position of the ALU inside the pipeline impacts the volves many different tradeoffs, from cycle performance at branch penalty. This paper considers the question on how to best make use of ALU resources inside a single-issue in-order pipeline. the architectural level to timing performance at the circuit We begin by analyzing which is the most efficient way of placing level. With the ultimate goal to improve performance and a single ALU in an in-order pipeline. We then go on to evaluate energy metrics, this work is concerned with design tradeoffs what is the most efficient way to make use of two ALUs, one for the ALU resources in a single-issue in-order pipeline.
    [Show full text]
  • Tms320c55x V3.X DSP Mnemonic Instruction Set
    C55x v3.x CPU Mnemonic Instruction Set Reference Guide Literature Number: SWPU067E June 2009 Preface Read This First About This Manual The C55x™ CPU is a fixed-point digital signal processor (DSP) in the TMS320™ family, and it can use either of two forms of the instruction set: a mnemonic form or an algebraic form. This book is a reference for the mnemonic form of the instruction set. It contains information about the instructions used for all types of operations. For information on the algebraic instruction set, see C55x v3.1 CPU Algebraic Instruction Set Reference Guide, SWPU068. Notational Conventions This book uses the following conventions. - In syntax descriptions, the instruction is in a bold typeface. Portions of a syntax in bold must be entered as shown. Here is an example of an instruction syntax: LMS Xmem, Ymem, ACx, ACy LMS is the instruction, and it has four operands: Xmem, Ymem, ACx, and ACy. When you use LMS, the operands should be actual dual data- memory operand values and accumulator values. A comma and a space (optional) must separate the four values. - Square brackets, [ and ], identify an optional parameter. If you use an optional parameter, specify the information within the brackets; do not type the brackets themselves. iii Related Documentation From Texas Instruments / Trademarks Related Documentation From Texas Instruments The following books describe the C55x™ devices and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477-8924. When ordering, please identify the book by its title and literature number.
    [Show full text]