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INE: Revision

INTRODUCTION TO NANOELECTRONICS Week-3, Lecture-1

Sneh Saurabh 14th January, 2019

Introduction to Nanoelectronics: S. Saurabh Overview 2

Nanoelectronics: Overview Nanoelectronics: Overview

Electronics to Nanoelectronics

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Electronics to Nanoelectronics: CMOS Electronics to Nanoelectronics: Moore’s Law (1)

. Complementary MOS (CMOS) Circuit Configuration was invented in 1963 . C. T. Sah and Frank Wanlass of the Fairchild R&D Laboratory showed that logic circuits combining p-channel and n-channel MOS in a complementary symmetry circuit configuration drew close to zero power in standby mode . Number of components in an IC realized at the minimum cost doubles every year (original)

. Number of transistors on integrated circuits double every two years (revised in 1975) Frank Wanlass's patent drawing Source: http://www.computerhistory.org . Continuing unabated since last five decades!

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Electronics to Nanoelectronics: Moore’s Law (2) Electronics to Nanoelectronics: Moore’s Law (3)

. Exponential increase in the count in integrated circuits CMOS Scaling:

. Continued shrinking of transistor size . Scaling theory proposed by Dennard et al. in 1974

. CMOS Scaling: Reducing the dimensions of the . Proposed that the basic operating characteristics of a MOSFET can be well-preserved if the and the wires connecting them in an IC parameters of the device are scaled in accordance with a given criterion such that the functionality of the IC remains unchanged . Scaling down of dimensions of transistors are done such that the geometric ratios that are important for the functioning of the IC remain unchanged

Increase in number of transistors for Intel’s microprocessor

Source: S.Saurabh and M. J. Kumar, Fundamentals of Tunnel Field Effect Transistors, CRC Press (Taylor & Francis), ISBN 9781498767132

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Electronics to Nanoelectronics: Moore’s Law (4) Electronics to Nanoelectronics: Moore’s Law (5)

3 Motivation for scaling Supply-voltage scaling 2.5 . The scaling of transistors as per Dennard’s rule and Moore’s law results in: 2  100% increase in transistor density . Supply voltage has remained constant 1.5 from 65 nm onward 1  40% increase in the clock-frequency 0.5

 30% reduction in the power delay product (a measure of energy dissipated per switching (V) Voltage Supply 0 operation), Power Challenge 25018013090 65 45 32 22 16 14 10  No change in the area and the power dissipation of the circuit. Technology Node (nm) . Controlling power dissipation is the  Cost of fabrication remained fairly constant with scaling (depends primarily on the area of biggest constraint for increasing the circuit) ⇒ cost of fabrication per transistor decreases with scaling frequency

. Fundamental thermal limits reached

. practically impossible to keep on concurrently increasing both the frequency of operation and the number of transistors

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Electronics to Nanoelectronics: Multicore Electronics to Nanoelectronics: Evolution

. Historically, prevalent technologies were replaced by . Frequency was selected as sacrificial their successors when their energy consumption victim became unaffordable: . Architecture of the microprocessors has . Vacuum Tubes  BJT  NMOS  CMOS changed from single core to multi-core

. More cores, parallel execution: throughput . Increasing power density, heat dissipation and increase energy overheads of the currently employed CMOS technology pose a serious challenge to the continued scaling of transistors Side-effect

. Dark Silicon: Many transistors need to be switched off (not used simultaneously) Source: https://www.sstc.co.jp/en/biz.html

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Electronics to Nanoelectronics: ITRS (1) Electronics to Nanoelectronics: Optimized Devices

. International Technology Roadmap for . Strained silicon (ITRS) . High-κ/ . Roadmaps are prepared by ITRS outlining technology progression in terms of technology “nodes.“ . FinFET

. materials (e.g., Germanium) Functions: http://www.itrs2.net/  Anticipated the evolution of the semiconductor market and helps in the planning of technological needs of IC production  Identified critical challenges in moving to future technology “nodes" and provides its assessment of emerging technologies and solutions https://irds.ieee.org/

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Electronics to Nanoelectronics: IRDS Electronics to Nanoelectronics: Going 3D

. International Roadmap for Devices and . Scaling limit will be reached in 2D by Systems (IDRS) 2020

. Only option left is exploit 3rd dimension

. Structure of integrated circuits needs to . Change in business model evolve from 2D to 3D structures https://irds.ieee.org/ . System requirements are set at the beginning of any new product design cycle . Transistor design needed to be aimed at  step by step corresponding device reduced power consumption as requirements percolated down through opposed to be optimized for maximum the design/development/manufacturing operating frequency production chain to the semiconductor manufactures . Now we are in for “3D Power Scaling” https://irds.ieee.org/

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New Era of Computing Electronics to Nanoelectronics: ITRS (2)

. Newer applications such as big data, IoT, artificial intelligence, . Multiple new and exciting devices autonomous systems, exascale that, after 10 years of research, computing etc. have already become or are soon becoming key players in the . Increasingly difficult to be fulfilled by next decade the saturating More Moore technologies . We will study many of these emerging charge-based devices . Beyond-CMOS technologies are being explored at the devices, processes, and architecture levels for the new era of computing. https://irds.ieee.org/

https://irds.ieee.org/

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