Journal of Xi'an University of Architecture & Technology Issn No : 1006-7930

OPERAND DECOMPOSITION TECHNIQUE BASED LOGARITHMIC MULTIPLIERS FOR BOTH BINARY AND TERNARY LOGIC

R. V. Shalini1 & Dr. P. Sampath2

1Assistant Professor, Departmentof Biomedical Engineering, Sri Shakthi Instituteof Engineering and Technology, Coimbatore, Tamil Nadu, INDIA. 2Professor, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode, Tamil Nadu, INDIA.

ABSTRACT Multipliers have its ineluctable role in many Digital Signal Processing applications such as correlation, convolution, filtering, and frequency analysis and in cryptography. In all these practical applications, Residue Number System (RNS) based multipliers form a reliable alternative technique. Simplified multiplication operation becomes possible with the involvement of logarithmic property as it reduces multiplication to mere . Hence the design that incorporates the features of LNS into RNS is taken, that combines the significant features of both the number systems forming Residue Logarithmic Number System (RLNS). The accuracy of the output values is improved by incorporating Operand Decomposition (OD) procedure into the multiplication process for the circuits designed using both binary logic and ternary logic. The comparison of the simulation results gives the significant features of the multiplication proposed with OD technique. The proposed method is compared with the existing technique of multiplier design for RNS based system that utilizes Radix 8 booth encoding concept (binary logic).

KEYWORDS: Binary logic, Ternary logic, Residue Logarithmic Number System (RLNS), Operand Decomposition (OD) technique.

1. INTRODUCTION The pertinent features of RNS have come out as an effectual solution in implementing several DSP applications. RNS involves in reducing the longer length input operands to shorter length modulo values, thus providing high processing speed for the system where it is involved. Several research works are found in literature implementing RNS for FIR, IIR filters, and Digital Image Processing applications [1-7]. Another significant application of RNS is in cryptography, providing highly secured transmission of data [8-11]. DSP applications generally deal with repeated multiplication and addition operations, therefore implementation of these designs with reduced computational complexity is more essential. To fulfill the above-mentioned criterion, the method of including logarithmic number system into RNS is analyzed to obtain a resource efficient multiplication structure. The combination of these unusual number systems is initially proposed by Arnold [12].

2. LITERATURE SURVEY The Operand Decomposition (OD) technique reduces the switching activity of the input operands during calculation and reduces the dynamic power dissipation of the multiplication with increase in delay and area values [13]. In this method the decomposition of input operands is followed by multiplication on the split operands and finding the sum of multiplied results.Combining OD technique in logarithmic multipliers along with error correction techniques provide results with reduced error value compared with error correction methods used without OD [14,15]. The existing works of logarithmic antilogarithmic

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conversion circuits with error correction procedures include Mitchell’s approximation procedure [16], linear approximation or Divided Approximation (DA) technique [17-23]. Different correction procedures give different percentage of error values for logarithmic and antilogarithmic conversion process. OD technique is applied in the multiplier design for RLNS based system with binary and ternary logic [24, 25]. The main objective of using OD technique is to reduce the Error Percentage (EP) value of multiplication result. This is achieved by combining the error correction methods proposed for binary and ternary logic based RLNS designs [24, 25] with OD technique. The Average Error Percentage (AEP)value and simulation parameters like area occupied, delay and TPD obtained for the proposed Binary and Ternary logic based RLNS multipliers with OD method is compared with results of existing work [24, 25].Simulation of the circuits are made using Cadence tool, Virtuoso 6.1.5 with 45nm TSMC CMOS technology. In this research work linear approximation procedure is followed to reduce the error value of binary logic based multiplier design [24]. And for ternary logic based design error correction circuitsproposed on trial and error method [25] is utilized.Reduction in error value of the multiplication results obtained with the method of OD methodis proposed and the percentage of reduction in EP values is studied in this paper.

3. PROPOSED DESIGN OF B-RLNS AND T-RLNS TECHNIQUES WITH OPERAND DECOMPOSITION METHOD OD is applied in the proposed multiplier designs for RLNS based system (B- RLNS and T-RLNS). The process of finding the split operands for OD process is modified when it is applied for ternary logic based RLNS design. This modification is required to get correct values of split operands whose sum gives the value of final multiplication result. 3.1 Binary Logic based Multiplication Process for RLNS based System (B-RLNS) using OD Methodology The operation of the OD procedure is explained below. Let the two input operands Ab, Bb be decomposed into Cb, Db, Eb, Fb. The suffix ‘b’ denotes binary logic based design. The bitwise operation done with the input operands Ab and Bb to get the split operands are given below,

cabibibib (1)

dabibibib (2)

eabibibib (3)

fabibibib (4)

where ‘i’ ranges from 0 to Nb-1. The values aib and bib denote the inverted of aib and bib respectively by NOT gate. The bitwise operations,  and  in the equations (1) – (4) denotes OR and AND functions respectively. The multiplication process done by the split operands is explained by the equation given below, Ab×Bb = (Cb×Db) + (Eb×Fb) (5) The B-RLNS based multiplication process using OD technique is shown in Figure 1. The output values of 2Nb bit length from two B-RLNS blocks are added by ripple carry addition operation to get the final multiplication result (‘Zb’). The Average Error Percentage (AEP) of the multiplication with OD technique, obtained for each Nb category are compared with the results of AEP calculated with existing work [24]. The disadvantage in this method is increase in the area occupied, TPD and delay when compared with the proposed design of not using OD technique. The B-RLNS based multiplier design block shown in Figure 1, represents the multiplier design explained in [24]. The two 2Nb bit results obtained represents the

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multiplication results of spilt operands and the values are added giving the final required multiplication result (Zb), as shown in Figure 1. a (OR) b a ' (AND) b aib (AND) bib ' i b ib ai b(AND) bi b ib ib

C D E F N bit N bit Nb bit Nb bit b b

B-RLNS based B-RLNS based multiplier design multiplier design

2Nb bit 2Nb bit

Addition block

(2Nb ) bit

Final multiplication result ( Zb ) Figure 1 B-RLNS based multiplication process using OD technique

3.2 Ternary Logic based Multiplication Process for RLNS based System (T-RLNS) using OD Methodology The proposed T-RLNS based multiplier design with T-LEC and T-ALEC circuits proposed are combined with OD method and the AEP value is calculated for the multiplication results obtained. The steps followed in ternary logic based OD method are given as follows. Let At and Bt be the input ternary operands, then the split operands Ct, Dt, Et and Ft are given by the expression as follows,

cit= abitit (5)

dit= abitit (6)

eit= abitit (7)

fit= abitit (8) where ‘i’ ranges from 0 to Nt-1. The trit wise operation  and  in the equations (5) – (8) denotes the Simple Ternary-OR (ST-OR) and Simple Ternary-AND (ST-AND) functions

respectively. The values ait and bit denote the inversion operation done on the input trits of the operands using ST-INV. The multiplication result is given by the equation, At×Bt = (CtDt) + (EtFt) (9) The modification in the OD technique in dealing with ternary values is done in finding the operands Et and Ft. In the process of finding Et and Ft, if the trit values given as

input for the ST-AND ( abit it and abit it ) as given in equation (7), (8) are both‘1’, then the resulting trit value is considered to be ‘0’ instead of ‘1’, where ‘1’ is the actual output value of ST-AND process.

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a (ST-OR) b a ' (ST-AND) b ait (ST-AND) bit' it it ait (ST- AND) bit it it

C D E F

Nt trit Nt trit Nt trit Nt trit

T-RLNS based T-RLNS based multiplier design multiplier design

(2Nt -1) trit (2Nt -1) trit

Addition block

(2Nt -1) trit

Final multiplication result ( Zt ) Figure 2 T-RLNS based multiplication process with OD technique

The result for other possible combination of trit values remains as per the ST- AND gate operation. This modification is required to get the correct values of split operands satisfying the equation (9). The ST-AND operation is done to find the values of Ct and Dt. After calculating the split operands, the multiplication is performed using OD technique. The process of OD based multiplication process for ternary logic based design is shown in Figure 2. The two product values obtained are added using ripple carry addition process to get the final output value (Zt).

4 SIMULATION RESULTS OBTAINED AND ITS COMPARISON WITH THE EXISTING AND PROPOSED TECHNIQUES Simulation of the circuits proposed are done using Cadence tool, Virtuoso (6.1.5) with TSMC 45nm CMOS technology, with 1 V, 0.5 V and 0 V power supplies used for ternary logic states ‘2’, ‘1’ and ‘0’ respectively. And 0.5 V and 0 V power supplies used for binary logic states ‘1’ and ‘0’ respectively. The proposed RLNS based multiplication structures (both B-RLNS and T-RLNS) with OD technique are analysed with the simulation parameter values, area occupied (µm2), TPD (µW/mW) and delay (ns). In addition the proposed methods are also compared with the existing work (Ramya Muralidaran & Chip Hong 2012). The Average Error Percentage (AEP) value of the final multiplication result obtained with and without using OD techniques is shown in Tables 1 and 2, for binary and ternary logic based design. The percentage of AEP value reduced when used with OD method for both logic is shown in Tables 1 and 2.

Table 1 Average Error Percentage (AEP) value obtained for the proposed B-RLNS based multiplication (with and without OD)

AEP Percentage of Multiplication structure (%) AEP lesser than

without using OD Technique Error Number of Without (%) used correction /trits, OD With OD

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circuits used Nb/ Nt [24] [24] 8 0.62 0.44 29 B-LEC and B-RLNS 16 0.73 0.45 38.3 B-ALEC 32 0.98 0.47 52.2

Table 2 Average Error Percentage (AEP) value obtained for the proposed T-RLNS based multiplication (with and without OD)

AEP Multiplication structure Percentage of (%) AEP lesser than Number of Without Technique Error correction without using OD bits/trits, N / OD used circuits used [25] b With OD (%) Nt [25] 6 5.05 3.41 32.2 T-LEC and T- T-RLNS 11 4.72 2.47 48 ALEC 21 7.51 3.13 58.2

The Error Percentage (EP) values obtained for the randomly chosen input operands, with and without OD technique are shown in Figures 3 – 8. Each graph shows EP values for 250 set of input operands for each Nb and Nt category chosen. For Nb = 8, 16 and 32 the EP values are shown in Figures 3 – 5 and for Nt =6,11 and 21 the EP values are shown in Figures 6 – 8.

EP for 8-bit operands 4 3.6 3.6 3.2 3.2 2.8 2.8 2.4 2.4 2 2 1.6 EP without OD 1.6

1.2 withEP OD EP with OD

EP withoutEP OD 1.2 0.8 0.8 0.4 0.4 0 0 0 50 100 150 200 250 8 bit input operands

Figure 3 EP values calculated for 8 bit B-RLNS design with and without OD

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EP for 16-bit operands 4 4 3.6 3.6 3.2 3.2 2.8 2.8 2.4 2.4 2 2 1.6 1.6 EP without OD

1.2 1.2 withEP OD EP with OD EP wihtoutEP OD 0.8 0.8 0.4 0.4 0 0 0 20000 40000 60000 80000 16 bit input operands

Figure 4 EP values calculated for 16 bit B-RLNS design with and without OD

EP for 32-bit operands 4 4 3.6 3.6 3.2 3.2 2.8 2.8 2.4 2.4 2 2 EP without OD 1.6 1.6

1.2 1.2 withEP OD EP with OD EP withoutEP OD 0.8 0.8 0.4 0.4 0 0 0 500000 1000000 1500000 32 bit input operands

Figure 5 EP values calculated for 32 bit B-RLNS design with and without OD

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EP for 6 trit input values

32 32 28 28 24 24 20 20 16 16 EP without OD

12 12 EP with OD EP withEP OD

EP withoutEP OD 8 8 4 4 0 0 0 100 200 300 6 trit input operands

Figure 6 EP values calculated for 6 trit T-RLNS design with and without OD

EP for 11 trit input values

16 16 14 14 12 12 10 10 8 8 EP without OD

6 6 EP with OD EP withEP OD EP withoutEP OD 4 4 2 2 0 0 250 20250 40250 60250 80250100250 11 trit input operands

Figure 7 EP values calculated for 11 trit T-RLNS design with and without OD

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EP for 21 trit input values 36 16 32 28 12 24 20 8 EP without OD 16 OD-EP

12 withEP OD EP withoutEP OD 8 4 4 0 0 100000 60000011000001600000 21 trit input operands

Figure 8 EP values calculated for 21 trit T-RLNS design with and without OD

From the graphs shown in Figures 3 – 8, the maximum values of EP obtained with Nb and Nt word length input operands are tabulated in Table 3 and Table 4.

Table 3 Maximum values of EP obtained for proposed B-RLNS design

Maximum Error Percentage (EP) Number of value bits, Nb With OD Without OD [24] 8 2.75 3.77 16 1.17 3.38 32 2.01 2.56

Table 4 Maximum values of EP obtained for proposed T-RLNS design

Maximum Error Percentage (EP) value Number of trits, Nt With OD Without OD [25] 6 12.67 22

11 5.45 12

21 5.55 10.5

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From the Table 3 and 4 it is inferred that the maximum value of EP value obtained is reduced when OD technique is used in the multiplier designs (B-RLNS and T-RLNS) along with error correction circuits [24 and 25]. The simulation results for the proposed (B-RLNS and T-RLNS) with OD technique is also compared with [24 and 25] is given in Tables 5-8. The comparison includes the existing work of modulo multiplier design for RNS based system [26]. The percentage of parameter values saved by the proposed techniques (B-RLNS and T-RLNS) with OD over existing research work [26] are tabulated in Table 9 and Table 10. The increase in area, TPD and delay values of the proposed technique with OD when compared with the existingdesigns [24 and 25] is due to use of two B-RLNS and T-RLNS schemes to perform the multiplication operation on the split operands.

Table 5 Comparison of Area among the proposed design (without OD) and existing work

Area (µm2) of multiplier design Number of Existing work B-RLNS T-RLNS Bits/trits [26] With Without With Without (N /N ) b t (binary logic) OD OD [24] OD OD [25] 8/6 117676 78851 41094 24045 12536 16/11 164997 93928 49545 36850 19910 32/21 215781 107102 60364 62368 31734

Table 6 Comparison of TPD among the proposed design (without using OD technique and existing work

TPD (µW*/mW#) of multiplier design Number of Existing work B-RLNS T-RLNS Bits/trits (binary logic) Without OD Without OD (Nb/Nt) With OD With OD [26] [24] [25] 8/6 15.97* 6.653* 2.918* 14.52# 6.96# 16/11 32.15* 8.688* 4.033* 26.91# 15.7# 32/21 53.25* 10.537* 5.169* 49.44# 36.5#

Table 7 Comparison of delay among the proposed designs with and without using OD technique and existing work

Delay (ns) of multiplier design Number of Bits/trits B-RLNS T-RLNS Existing work (Nb/Nt) Without (binary logic) With With Without OD [26] OD OD OD [25] [24] 8/6 130 93.14 78 3.5 2.5 16/11 340 185.2 142 11.62 9.2 32/21 567 340 281 20.12 15.5

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Table 8 Comparison of PDP among the proposed designs with and without using OD technique and existing work

PDP (10-15Joules) of multiplier design Number of Existing work B-RLNS T-RLNS Bits/trits [26] (binary With Without With Without (N /N ) b t logic) OD OD [24] OD OD [25] 8/6 2076.1 619.66 227.6 50820 17400 16/11 10931 1609.01 572.68 312694 144440 32/21 30192.7 3582.58 1452.48 994732 565750

Table 9 Percentage of parameter values of the B-RLNS design (with OD) saved over existing technique [26]

Percentage of parameter values Number of Multiplication saved over existing work(%) bits (N ) / trits structure using b Area TPD Delay PDP (N ) t (µm2) (µW) (ns) (Joules) B-RLNS with OD 8 33 58.3 28.3 49.3 16 43.07 73 45.5 78 32 50.3 80.2 40.3 85

Table 10 Percentage of parameter values of the T-RLNS design (with OD) saved over existing technique [26]

Percentage of parameter values Number of Multiplication saved over existing work bits (N ) / structure using b (%) trits (N ) t Area (µm2) Delay (ns) 6 79.5 97.3 T-RLNS with OD 11 78 96.5 21 71 96.4

The area occupied (µm2) and delay value (ns) of TVL based structure with OD technique is 76% and 97% lesser than the existing technique [26].Similarly B-RLNS based multiplication process with OD technique saves 42% of the area utilized, 70.5% of the TPD values, 38% of delay time and 81.1% of PDP when compared with existing technique [26]. This lesser percentage values are due to the concept of LNS incorporated in the proposed designs whereas existing work [26] uses Radix-8 booth encoding technique for the multiplier design. The increase in TPD in TVL based design is due to three different voltage level used for three different logic states. The increase in TPD value for ternary logic based design is compensated for its minimum area utilization and delay values.

5 SUMMARY The RLNS based multiplier design (both binary and ternary logic) with OD technique proposed in this research work reduce the AEP of the final result. The reduction of AEP with OD technique is in the range of 29to 52.2 % for B-RLNS design and is 32.2 to 58.2 % for T-RLNS design. The simulation parameters obtained for the proposed designs (B- RLNS and T-RLNS) with OD technique is compared with B-RLNS and T-RLNS designs

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without OD technique [24, 25] and with the existing work [26]. In comparison with [24 and 25], the multiplier design with OD (both binary and ternary logic) shows 47% increase in area occupied, 47% increase in TPD value, 21.5% increase in delay and 58.2% increase in PDP value. In comparison with the existing work [26] it is found that proposed B-RLNS and T-RLNS design with OD method show decrease in area, TPD and delay. B- RLNS based design show decrease in the area, TPD and delay by 42%, 70.5% and 38% respectively. Similarly, T-RLNS design shows76% decrease in area occupied and 97% decrease in delay values. Therefore, to reduce the error value for the proposed RLNS based multipliers the idea of OD method along with the error correction circuits may be considered to be optimum.

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14. Mahalingam, V & Nagarajan 2006, ‘Improving Accuracy in Mitchell’s Logarithmic Multiplication using Operand Decomposition’, IEEE Transactions on Computers, vol. 55, no. 12, pp. 1523-1535. 15. Mahalingam, V & Ranganathan, N 2006, An Efficient and Accurate Logarithmic Multiplier based on Operand Decomposition , pp. 3-7 16. Mitchell Jr JN 1962, ‘Computer Multiplication and Division using Binary Logarithms’, IEEE Transactions on Electronic Computers, vol. EC-11, no. 4, pp. 512-517. 17. Khalid H Abed & Raymond E Siferd 2003b, ‘VLSI Implementation of a Low-Power Antilogarithmic Converter’, IEEE Transactions on Computers, vol. 52, no. 9, pp. 1221-1228. 18. Combet, M , Van Zonneveld , H & Verbeek, L 1965, ‘Computation of the Base Two Logarithm of Binary Numbers’, IEEE Transaction on Electronic Computers, pp. 863-867. 19. Arnold, M, Bailey, T & Cowles, J 2003, ‘Error analysis of the Krnetz/Maenner algorithm’, Journal of VLSI signal processing, vol. 33, pp. 37-53. 20. Thomas A Brubaker & John C Becker 1975, ‘Multiplication using logarithms implemented with Read-only-memory’, IEEE Transactions on computers, vol. 24, no. 8, pp. 761-766. 21. Davide De Caro, Nicola Petra & Antonio GMStrollo 2011, ‘Efficient logarithmic converters for digital signal processing applications’, IEEE Transactions on Circuits and systems-II: express briefs, vol. 58, no. 10, pp. 667-671. 22. David M Lewis 1994, ‘Interleaved memory function interpolators with application to accurate LNS arithmetic unit’, IEEE Transactions on computers, vol. 43, no. 8, pp. 974-982. 23. Fang-shi Lai & Ching-Farn Eric Wu 1991, ‘A Hybrid number system processor with geometric and complex arithmetic capabilities’, IEEE Transactions on Computers, vol. 40, no. 8, pp. 652-662. 24. R. V. Shalini and Dr. P. Sampath, “Multiplier Design Incorporating Logarithmic Number System for Residue Number System in Binary Logic”, published in SSRG International Journal of VLSI and signal processing, Volume 5 Issue 3, December 2018. 25. Shalini Radakirishnan Valliammal, Sampath Palaniswami, “Multiplier design utilizing Tri Valued Logic for RLNS based DSP applications”, published in Circuits and System, Volume 7, April 2016. 26. Ramya Muralidaran & Chip Hong Chan 2012, ‘Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1,2n,2n+1} based RNS’, }, IEEE Transactions on Circuits and Systems I Regular papers, 59(10): 2263-2273

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