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Operand Decomposition Technique Based Logarithmic Multipliers for Both Binary and Ternary Logic

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Operand Decomposition Technique Based Logarithmic Multipliers for Both Binary and Ternary Logic Journal of Xi'an University of Architecture & Technology Issn No : 1006-7930 OPERAND DECOMPOSITION TECHNIQUE BASED LOGARITHMIC MULTIPLIERS FOR BOTH BINARY AND TERNARY LOGIC R. V. Shalini1 & Dr. P. Sampath2 1Assistant Professor, Departmentof Biomedical Engineering, Sri Shakthi Instituteof Engineering and Technology, Coimbatore, Tamil Nadu, INDIA. 2Professor, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode, Tamil Nadu, INDIA. ABSTRACT Multipliers have its ineluctable role in many Digital Signal Processing applications such as correlation, convolution, filtering, and frequency analysis and in cryptography. In all these practical applications, Residue Number System (RNS) based multipliers form a reliable alternative technique. Simplified multiplication operation becomes possible with the involvement of logarithmic property as it reduces multiplication to mere addition. Hence the design that incorporates the features of LNS into RNS is taken, that combines the significant features of both the number systems forming Residue Logarithmic Number System (RLNS). The accuracy of the output values is improved by incorporating Operand Decomposition (OD) procedure into the multiplication process for the circuits designed using both binary logic and ternary logic. The comparison of the simulation results gives the significant features of the multiplication proposed with OD technique. The proposed method is compared with the existing technique of multiplier design for RNS based system that utilizes Radix 8 booth encoding concept (binary logic). KEYWORDS: Binary logic, Ternary logic, Residue Logarithmic Number System (RLNS), Operand Decomposition (OD) technique. 1. INTRODUCTION The pertinent features of RNS have come out as an effectual solution in implementing several DSP applications. RNS involves in reducing the longer length input operands to shorter length modulo values, thus providing high processing speed for the system where it is involved. Several research works are found in literature implementing RNS for FIR, IIR filters, and Digital Image Processing applications [1-7]. Another significant application of RNS is in cryptography, providing highly secured transmission of data [8-11]. DSP applications generally deal with repeated multiplication and addition operations, therefore implementation of these designs with reduced computational complexity is more essential. To fulfill the above-mentioned criterion, the method of including logarithmic number system into RNS is analyzed to obtain a resource efficient multiplication structure. The combination of these unusual number systems is initially proposed by Arnold [12]. 2. LITERATURE SURVEY The Operand Decomposition (OD) technique reduces the switching activity of the input operands during calculation and reduces the dynamic power dissipation of the multiplication with increase in delay and area values [13]. In this method the decomposition of input operands is followed by multiplication on the split operands and finding the sum of multiplied results.Combining OD technique in logarithmic multipliers along with error correction techniques provide results with reduced error value compared with error correction methods used without OD [14,15]. The existing works of logarithmic antilogarithmic Volume XII, Issue III, 2020 Page No: 3408 Journal of Xi'an University of Architecture & Technology Issn No : 1006-7930 conversion circuits with error correction procedures include Mitchell’s approximation procedure [16], linear approximation or Divided Approximation (DA) technique [17-23]. Different correction procedures give different percentage of error values for logarithmic and antilogarithmic conversion process. OD technique is applied in the multiplier design for RLNS based system with binary and ternary logic [24, 25]. The main objective of using OD technique is to reduce the Error Percentage (EP) value of multiplication result. This is achieved by combining the error correction methods proposed for binary and ternary logic based RLNS designs [24, 25] with OD technique. The Average Error Percentage (AEP)value and simulation parameters like area occupied, delay and TPD obtained for the proposed Binary and Ternary logic based RLNS multipliers with OD method is compared with results of existing work [24, 25].Simulation of the circuits are made using Cadence tool, Virtuoso 6.1.5 with 45nm TSMC CMOS technology. In this research work linear approximation procedure is followed to reduce the error value of binary logic based multiplier design [24]. And for ternary logic based design error correction circuitsproposed on trial and error method [25] is utilized.Reduction in error value of the multiplication results obtained with the method of OD methodis proposed and the percentage of reduction in EP values is studied in this paper. 3. PROPOSED DESIGN OF B-RLNS AND T-RLNS TECHNIQUES WITH OPERAND DECOMPOSITION METHOD OD is applied in the proposed multiplier designs for RLNS based system (B- RLNS and T-RLNS). The process of finding the split operands for OD process is modified when it is applied for ternary logic based RLNS design. This modification is required to get correct values of split operands whose sum gives the value of final multiplication result. 3.1 Binary Logic based Multiplication Process for RLNS based System (B-RLNS) using OD Methodology The operation of the OD procedure is explained below. Let the two input operands Ab, Bb be decomposed into Cb, Db, Eb, Fb. The suffix ‘b’ denotes binary logic based design. The bitwise operation done with the input operands Ab and Bb to get the split operands are given below, cib a ib b ib (1) dib a ib b ib (2) eib a ib b ib (3) fib a ib b ib (4) where ‘i’ ranges from 0 to Nb-1. The values aib and bib denote the inverted bit of aib and bib respectively by NOT gate. The bitwise operations, and in the equations (1) – (4) denotes OR and AND functions respectively. The multiplication process done by the split operands is explained by the equation given below, Ab×Bb = (Cb×Db) + (Eb×Fb) (5) The B-RLNS based multiplication process using OD technique is shown in Figure 1. The output values of 2Nb bit length from two B-RLNS blocks are added by ripple carry addition operation to get the final multiplication result (‘Zb’). The Average Error Percentage (AEP) of the multiplication with OD technique, obtained for each Nb category are compared with the results of AEP calculated with existing work [24]. The disadvantage in this method is increase in the area occupied, TPD and delay when compared with the proposed design of not using OD technique. The B-RLNS based multiplier design block shown in Figure 1, represents the multiplier design explained in [24]. The two 2Nb bit results obtained represents the Volume XII, Issue III, 2020 Page No: 3409 Journal of Xi'an University of Architecture & Technology Issn No : 1006-7930 multiplication results of spilt operands and the values are added giving the final required multiplication result (Zb), as shown in Figure 1. a (OR) b a ' (AND) b aib (AND) bib ' i b ib ai b(AND) bi b ib ib C D E F N bit N bit Nb bit Nb bit b b B-RLNS based B-RLNS based multiplier design multiplier design 2Nb bit 2Nb bit Addition block (2Nb ) bit Final multiplication result ( Zb ) Figure 1 B-RLNS based multiplication process using OD technique 3.2 Ternary Logic based Multiplication Process for RLNS based System (T-RLNS) using OD Methodology The proposed T-RLNS based multiplier design with T-LEC and T-ALEC circuits proposed are combined with OD method and the AEP value is calculated for the multiplication results obtained. The steps followed in ternary logic based OD method are given as follows. Let At and Bt be the input ternary operands, then the split operands Ct, Dt, Et and Ft are given by the expression as follows, cit= abit it (5) dit= abit it (6) eit= abit it (7) fit= abit it (8) where ‘i’ ranges from 0 to Nt-1. The trit wise operation and in the equations (5) – (8) denotes the Simple Ternary-OR (ST-OR) and Simple Ternary-AND (ST-AND) functions respectively. The values ait and bit denote the inversion operation done on the input trits of the operands using ST-INV. The multiplication result is given by the equation, At×Bt = (CtDt) + (EtFt) (9) The modification in the OD technique in dealing with ternary values is done in finding the operands Et and Ft. In the process of finding Et and Ft, if the trit values given as input for the ST-AND ( abit it and abit it ) as given in equation (7), (8) are both‘1’, then the resulting trit value is considered to be ‘0’ instead of ‘1’, where ‘1’ is the actual output value of ST-AND process. Volume XII, Issue III, 2020 Page No: 3410 Journal of Xi'an University of Architecture & Technology Issn No : 1006-7930 a (ST-OR) b a ' (ST-AND) b ait (ST-AND) bit' it it ait (ST- AND) bit it it C D E F Nt trit Nt trit Nt trit Nt trit T-RLNS based T-RLNS based multiplier design multiplier design (2Nt -1) trit (2Nt -1) trit Addition block (2Nt -1) trit Final multiplication result ( Zt ) Figure 2 T-RLNS based multiplication process with OD technique The result for other possible combination of trit values remains as per the ST- AND gate operation. This modification is required to get the correct values of split operands satisfying the equation (9). The ST-AND operation is done to find the values of Ct and Dt. After calculating the split operands, the multiplication is performed using OD technique. The process of OD based multiplication process for ternary logic based design is shown in Figure 2. The two product values obtained are added using ripple carry addition process to get the final output value (Zt). 4 SIMULATION RESULTS OBTAINED AND ITS COMPARISON WITH THE EXISTING AND PROPOSED TECHNIQUES Simulation of the circuits proposed are done using Cadence tool, Virtuoso (6.1.5) with TSMC 45nm CMOS technology, with 1 V, 0.5 V and 0 V power supplies used for ternary logic states ‘2’, ‘1’ and ‘0’ respectively.
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