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Архитектура Intel От I386 До Xeon Phi: Процессоры, Производительность, Энергопотребление

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Архитектура Intel От I386 До Xeon Phi: Процессоры, Производительность, Энергопотребление Нижегородский государственный университет им. Н.И.Лобачевского Факультет Вычислительной математики и кибернетики Архитектура Intel от i386 до Xeon Phi: процессоры, производительность, энергопотребление Линёв А.В. 2014 Нижний Новгород Содержание Эволюция архитектур центральных процессоров. История появления новых концепций и их реализации в процессорах архитектур Intel. Изменения основных характеристик процессоров. Современные направления развития архитектуры процессоров. Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 2 из 66 Архитектура и микроархитектура CPU Фон Неймановская модель компьютера Разделение программируемой вычислительной машины на компоненты: Центральный обрабатывающий блок (Central Processing Unit, CPU) блок управления (Control Unit ) (декодирование инструкций, порядок операций) тракт данных (Datapath) (регистры, арифметико-логическое устройство, шины) Память: Хранение инструкций и их операндов Подсистема ввода/вывода (Input/Output, I/O sub- system): шина I/O, интерфейсы, устройства Концепция хранения программ: Инструкции из набора команд выбираются из общей памяти и исполняются последовательно Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 4 из 66 Фон Неймановская модель компьютера Компьютерная CPU I/O Devices система Control Memory Datapath Input Registers, (instructions, ALU, buses data) Главное ограничение производительности CPU: фон- Одно из ограничений Неймановская модель вычислений Output производительности: подразумевает последовательное общая память команд и исполнение инструкций по одной данных (потенциальное «узкое место») Процессор - программируемый вычислительный элемент, выполняющий программы, написанные с использованием предопределенного набора инструкций. Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 5 из 66 Шаги обработки инструкций в CPU Выборка Выбрать инструкцию программы из памяти инструкции Программный счетчик (Program Counter, PC / Instruction Pointer, IP) указывает на следующую для обработки инструкцию Декодирование Определить требуемые действия и размер инструкции инструкции Выборка операндов Найти и получить данные операндов Исполнение Вычислить значение результата или статус Сохранение Записать результаты в запоминающее устройство результатов для последующего использования Главное ограничение производительности CPU: фон- Неймановская модель вычислений подразумевает последовательное исполнение инструкций по одной Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 6 из 66 Intel 4004 Первый в мире процессор общего назначения 1971 г. 740 кГц 0,06 MIPS 2250 транзис- торов 12 мм2 10 мкм техпроцесс http://ru.wikipedia.org/wiki/Intel_4004 Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 7 из 66 Характеристики процессоров Процессор 4004 Год выпуска 1971 Тактовая частота 740 кГц Производительность (MIPS) 0,06 Количество транзисторов 2250 Площадь кристалла (кв.мм) 12 Техпроцесс 10 мкм Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 8 из 66 Intel 8008, 8080 Intel 8008 (1972) Первый 8-битный процессор Тактовая частота – 500 (800) кГц Производительность – 0,05 MIPS Количество транзисторов – 3500 Техпроцесс – 10 мкм Поддержка прерываний Intel 8080 (1974) Тактовая частота – 2 (2.5, 3) МГц Производительность – 0,64 MIPS Количество транзисторов – 6000 Техпроцесс – 6 мкм Порты ввода/вывода, Stack Pointer Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 9 из 66 Intel 8086/87 Intel 8086 (1978) Первый процессор архитектуры x86 Тактовая частота – 4 (10) МГц Производительность – 0,33 (0,75) MIPS Количество транзисторов – 29 000 Площадь кристалла – 33 кв.мм Техпроцесс – 3 мкм Потребляемая мощность – 0,65 Вт Тепловыделение – 1,75 Вт Intel 8087 (1980) Математический сопроцессор Производительность – ~50 000 FLOPS Количество транзисторов – 45 000 Техпроцесс – 3 мкм Потребляемая мощность – 2,4 Вт Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 10 из 66 http://faculty.etsu.edu/tarnoff/ntes2150/uproc/arch8088.htm Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 11 из 66 Конвейер команд… Конвейерная обработка инструкций – это метод реализации CPU, при котором множество операции над несколькими инструкциями перекрываются. Конвейерная обработка инструкций использует программный параллелизм уровня инструкций (Instruction- Level Parallelism, ILP) Конвейеризация увеличивает пропускную способность CPU - среднее число инструкций, завершенных за такт. В идеальном случае происходит завершение одной инструкции за машинный такт Конвейеризация не сокращает время выполнения отдельной инструкции (также называемое временем задержки завершения инструкции). Минимальное время задержки завершения инструкции - n тактов, где n – число ступеней конвейера Конвейер, описанный здесь, называется упорядоченным (in-order) конвейером так как инструкции обрабатываются или исполняются в порядке, указанном в исходной программе Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 12 из 66 Однопортовый конвейер MIPS с упорядоченной обработкой целочисленных операций Число тактов до заполнения = время разгона = число ступеней -1 Номер такта Номер инструкции 1 2 3 4 5 6 7 8 9 Время в тактах Инструкция I IF ID EX MEM WB Первая инструкция, I Инструкция I+1 IF ID EX MEM WB завершена Инструкция I+2 IF ID EX MEM WB Инструкция I+3 IF ID EX MEM WB Инструкция I +4 IF ID EX MEM WB Время разгона = 4 такта Последняя инструкция, Ступени конвейера MIPS: I+4 завершена IF = Выборка инструкции (Instruction Fetch) ID = Декодирование инструкции (Instruction Decode) EX = Исполнение (Execution) MEM = Обращение к памяти (Memory Access) WB = Запись результата (Write Back) Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 13 из 66 Intel 80286 Intel 80286 (1982) Тактовая частота – 6 (12,5) МГц Производительность – 0,9 (2,66) MIPS Количество транзисторов – 134 000 Площадь кристалла – 49 кв.мм Техпроцесс – 1,5 мкм 0.21 Instructions Per Clock Конвейер команд (длина - 4) Защищенный режим Linear Memory Management Unit (MMU) Intel 80287 (1983) Математический сопроцессор Производительность – ~65 000 FLOPS Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 14 из 66 Intel 80286 http://en.wikipedia.org/wiki/File:Intel_i80286_arch.svg Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 15 из 66 Intel 80386 Intel 80386DX (1985) Тактовая частота – 12 (33) МГц Производительность – 5 (11,4) MIPS Количество транзисторов – 275 000 Площадь кристалла – 104 (39) кв.мм Техпроцесс – 1,5 (1) мкм Страничное преобразование Аппаратная отладка Встроенный математический сопроцессор 80387 Производительность – ~300 000 FLOPS Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 16 из 66 Intel 80386 http://en.wikipedia.org/wiki/File:80386DX_arch.png Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 17 из 66 Страничная адресация Управляющий Виртуальное Регистр Адресное Таблица страниц Пространство RAM MAX Physical frame number N MAX (4 Гб) … Physical frame number 1 Physical frame number 0 0 HDD 0 Позволяет организовывать ВАП большого размера с линейной адресацией на основе разрывных блоков физической памяти Нижний Новгород 2013 Архитектура Intel Xeon Phi 18 из 45 Конвейер команд – Конфликты Структурные конфликты Возникают из-за недостатков аппаратных ресурсов когда доступное аппаратное обеспечение не в состоянии поддерживать все возможные комбинации инструкций Конфликты данных Возникают когда инструкция зависит от результата выполнения предыдущей инструкции так, что это проявляется при перекрытии инструкций в конвейере Конфликты управления Возникают при конвейеризации условных переходов и других инструкций, которые изменяют PC Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 19 из 66 Единая разделяемая память для инструкций и данных Процессор с блоком памяти, вызывающим структурные конфликты В машине с единственным портом памяти будет возникать конфликт при любом обращении к памяти. Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 20 из 66 Единая разделяемая память для данных и инструкций Разрешение структурного конфликта при помощи тактов простоя Структурный конфликт приводит к необходимости вставки «пузырей» в конвейер. Нижний Новгород Архитектура Intel от i386 до Xeon Phi: процессоры, 2014 производительность, энергопотребление 21 из 66 Многотактовый конвейер вещественных операций Задержка = 6 Целочисленный блок (Задержка= 0 Период запуска = 1) Конфликты: Период запуска = 1 RAW, WAW Конвейеризуемое возможны WAR невозможен Структурные: Вещественное (FP)/целочисленное умножение возможны Управления: возможны EX IF ID FP сумматор MEM WB Задержка = 3 FP/целочисленное деление Период запуска = 1 Задержка = 24 Конвейеризуемое
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