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Instruction Set Reference, A-M IA-32 Intel® Architecture Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M NOTE: The IA-32 Intel Architecture Software Developer’s Manual consists of four volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; and the System Programming Guide, Order Number 253668. Refer to all four volumes when evaluating your design needs. Order Number: 253666-017 September 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EX- PRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RE- LATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FIT- NESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Developers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Improper use of reserved or undefined features or instructions may cause unpredictable behavior or failure in developer's software code when running on an Intel processor. Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use. The Intel® IA-32 architecture processors (e.g., Pentium® 4 and Pentium III processors) may contain design defects or errors known as errata. Current characterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting Hyper-Threading Technology and an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/techtrends/technologies/hyperthreading.htm for more in- formation including details on which processors support HT Technology. Intel, Intel386, Intel486, Pentium, Intel Xeon, Intel NetBurst, Intel SpeedStep, OverDrive, MMX, Celeron, and Itanium are trademarks or registered trademarks of Intel Corporation and its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s website at http://www.intel.com Copyright © 1997-2005 Intel Corporation CONTENTS FOR VOLUME 2A AND 2B PAGE CHAPTER 1 ABOUT THIS MANUAL 1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL . 1-1 1.2 OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTION SET REFERENCE. 1-2 1.3 NOTATIONAL CONVENTIONS. 1-2 1.3.1 Bit and Byte Order. .1-2 1.3.2 Reserved Bits and Software Compatibility . .1-3 1.3.3 Instruction Operands . .1-4 1.3.4 Hexadecimal and Binary Numbers . .1-4 1.3.5 Segmented Addressing . .1-4 1.3.6 Exceptions. .1-5 1.3.7 A New Syntax for CPUID, CR, and MSR Values . .1-5 1.4 RELATED LITERATURE . 1-7 CHAPTER 2 INSTRUCTION FORMAT 2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE . 2-1 2.1.1 Instruction Prefixes . .2-2 2.1.2 Opcodes . .2-3 2.1.3 ModR/M and SIB Bytes . .2-4 2.1.4 Displacement and Immediate Bytes . .2-4 2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes . .2-5 2.2 IA-32E MODE. 2-9 2.2.1 REX Prefixes . .2-9 2.2.1.1 Encoding. .2-10 2.2.1.2 More on REX Prefix Fields . .2-10 2.2.1.3 Displacement . .2-13 2.2.1.4 Direct Memory-Offset MOVs. .2-14 2.2.1.5 Immediates . .2-14 2.2.1.6 RIP-Relative Addressing. .2-14 2.2.1.7 Default 64-Bit Operand Size. .2-15 2.2.2 Additional Encodings for Control and Debug Registers . .2-15 CHAPTER 3 INSTRUCTION SET REFERENCE, A-M 3.1 INTERPRETING THE INSTRUCTION REFERENCE PAGES . 3-1 3.1.1 Instruction Format . .3-1 3.1.1.1 Opcode Column in the Instruction Summary Table . .3-1 3.1.1.2 Instruction Column in the Opcode Summary Table . .3-3 3.1.1.3 64-bit Mode Column in the Instruction Summary Table . .3-6 3.1.1.4 Compatibility/Legacy Mode Column in the Instruction Summary Table . .3-7 3.1.1.5 Description Column in the Instruction Summary Table. .3-7 3.1.1.6 Description Section. .3-7 3.1.1.7 Operation Section. .3-7 3.1.1.8 Intel® C/C++ Compiler Intrinsics Equivalents Section . .3-11 3.1.1.9 Flags Affected Section . .3-14 3.1.1.10 FPU Flags Affected Section . .3-14 Vol. 2A iii CONTENTS PAGE 3.1.1.11 Protected Mode Exceptions Section. .3-14 3.1.1.12 Real-Address Mode Exceptions Section . .3-15 3.1.1.13 Virtual-8086 Mode Exceptions Section. .3-15 3.1.1.14 Floating-Point Exceptions Section . .3-15 3.1.1.15 SIMD Floating-Point Exceptions Section . .3-16 3.1.1.16 Compatibility Mode Exceptions Section . .3-16 3.1.1.17 64-Bit Mode Exceptions Section. .3-16 3.2 INSTRUCTIONS (A-M) . 3-17 AAA—ASCII Adjust After Addition. .3-18 AAD—ASCII Adjust AX Before Division . .3-20 AAM—ASCII Adjust AX After Multiply . .3-22 AAS—ASCII Adjust AL After Subtraction . .3-24 ADC—Add with Carry . .3-26 ADD—Add. .3-29 ADDPD—Add Packed Double-Precision Floating-Point Values . .3-32 ADDPS—Add Packed Single-Precision Floating-Point Values . .3-35 ADDSD—Add Scalar Double-Precision Floating-Point Values . .3-38 ADDSS—Add Scalar Single-Precision Floating-Point Values. .3-41 ADDSUBPD: Packed Double-FP Add/Subtract. .3-44 ADDSUBPS: Packed Single-FP Add/Subtract . .3-48 AND—Logical AND . .3-52 ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point Values. .3-55 ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point Values. .3-57 ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. .3-59 ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. .3-61 ARPL—Adjust RPL Field of Segment Selector . .3-63 BOUND—Check Array Index Against Bounds . .3-65 BSF—Bit Scan Forward . .3-67 BSR—Bit Scan Reverse . .3-69 BSWAP—Byte Swap. .3-71 BT—Bit Test . .3-73 BTC—Bit Test and Complement . .3-76 BTR—Bit Test and Reset . .3-79 BTS—Bit Test and Set . .3-82 CALL—Call Procedure . .3-85 CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword . .3-102 CLC—Clear Carry Flag . .3-103 CLD—Clear Direction Flag . .3-104 CLFLUSH—Flush Cache Line. .3-105 CLI —.
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