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Intel® Celeron® Processor 500 Series for Platforms Based on Mobile Intel® 4 Series Express Chipset Families

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Intel® Celeron® Processor 500 Series for Platforms Based on Mobile Intel® 4 Series Express Chipset Families Intel® Celeron® Processor 500Δ Series Datasheet For Platforms Based on Mobile Intel® 4 Series Express Chipset Family August 2008 Revision 001 Document Number: 320462-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELÆ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Φ64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. Intel, Celeron, Pentium, Intel Core, Intel Core 2, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2008, Intel Corporation. All rights reserved. 2 Datasheet Contents 1Introduction..............................................................................................................7 1.1 Terminology .......................................................................................................8 1.2 References .........................................................................................................9 2 Low Power Features ................................................................................................ 11 2.1 Clock Control and Low Power States .................................................................... 11 2.1.1 Core Low-Power States ........................................................................... 12 2.1.1.1 C0 State .................................................................................. 12 2.1.1.2 C1/AutoHALT Powerdown State .................................................. 12 2.1.1.3 C1/MWAIT Powerdown State ...................................................... 13 2.1.1.4 Core C2 State........................................................................... 13 2.1.1.5 Core C3 State........................................................................... 13 2.1.2 Package Low-Power States ...................................................................... 13 2.1.2.1 Normal State............................................................................ 13 2.1.2.2 Stop-Grant State ...................................................................... 13 2.1.2.3 Stop Grant Snoop State............................................................. 14 2.1.2.4 Sleep State .............................................................................. 14 2.1.2.5 Deep Sleep State ...................................................................... 15 2.2 Low-Power FSB Features .................................................................................... 15 2.3 Processor Power Status Indicator (PSI#) Signal..................................................... 15 3 Electrical Specifications ........................................................................................... 17 3.1 Power and Ground Pins ...................................................................................... 17 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking...................................................... 17 3.3 Voltage Identification......................................................................................... 17 3.4 Catastrophic Thermal Protection .......................................................................... 21 3.5 Reserved and Unused Pins.................................................................................. 21 3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 22 3.7 FSB Signal Groups............................................................................................. 22 3.8 CMOS Signals ................................................................................................... 23 3.9 Maximum Ratings.............................................................................................. 23 3.10 Processor DC Specifications ................................................................................ 24 4 Package Mechanical Specifications and Pin Information .......................................... 29 4.1 Package Mechanical Specifications ....................................................................... 29 4.2 Processor Pinout and Pin List .............................................................................. 32 4.3 Alphabetical Signals Reference ........................................................................... 51 5 Thermal Specifications ............................................................................................ 59 5.1 Thermal Diode .................................................................................................. 60 5.1.1 Thermal Diode Offset .............................................................................. 60 5.2 Intel® Thermal Monitor...................................................................................... 62 5.3 Digital Thermal Sensor....................................................................................... 64 5.4 Out of Specification Detection ............................................................................. 64 5.5 PROCHOT# Signal Pin ........................................................................................ 65 Datasheet 3 Figures 1 Package-Level Low-Power States ................................................................................11 2 Core Low-Power States .............................................................................................12 3 Active VCC and ICC Loadline Standard Voltage .............................................................26 4 1-MB Micro-FCPGA Processor Package Drawing (1 of 2) .................................................30 5 1-MB Micro-FCPGA Processor Package Drawing (2 of 2) .................................................31 Tables 1 Coordination of Core-Level Low-Power States at the Package Level .................................11 2 Voltage Identification Definition .................................................................................18 3 BSEL[2:0] Encoding for BCLK Frequency......................................................................22 4 FSB Pin Groups ........................................................................................................22 5 Processor Absolute Maximum Ratings..........................................................................24 6 DC Voltage and Current Specifications.........................................................................24 7 FSB Differential BCLK Specifications ............................................................................26 8 AGTL+ Signal Group DC Specifications ........................................................................27 9 CMOS Signal Group DC Specifications..........................................................................28 10 Open Drain Signal Group DC Specifications ..................................................................28 11 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 1 of 2) ..........................................................................................................32 12 The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of 2) ..........................................................................................................33 13 Pin Listing by Pin Name .............................................................................................35 14 Pin Listing by Pin Number ..........................................................................................42
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