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Connecting SDR and DDR Memories to SAM9X60

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Connecting SDR and DDR Memories to SAM9X60 AN3310 Connecting SDR and DDR Memories to SAM9X60 Scope The SAM9X60 is a high-performance, ultra-low power ARM926EJ-S CPU-based embedded microprocessor (MPU) running up to 600 MHz, with support for multiple memories such as SDRAM, LP-SDRAM, LP-DDR, DDR2, and QSPI and e.MMC Flash. The device integrates powerful peripherals for connectivity and user interface applications, and offers security functions (tamper detection, secure boot program, secure key storage, etc.), TRNG, as well as high- performance crypto accelerators for AES and SHA. This application note is intended to help the developer design a system based on the SAM9X60 using an external memory by providing examples. Refer to References for board design example files. Abbreviation List • SDRAM – Synchronous Dynamic Random-Access Memory • SDR – Single Data Rate • DDR – Double Data Rate • LP – Low Power • PCB – Printed Circuit Board References The following references are available on https://www.microchip.com/wwwproducts/en/SAM9X60. Type Name Literature No. Data sheet SAM9X60 DS60001579 Errata SAM9X60 Device Silicon Errata and Data Sheet Clarification DS80000846 Application note SAM9X60 Hardware Design Considerations DS00003311 Board design example files SAM9X60 board design example files – © 2019 Microchip Technology Inc. Application Note DS00003310A-page 1 AN3310 Table of Contents Scope............................................................................................................................................................. 1 Abbreviation List.............................................................................................................................................1 References.....................................................................................................................................................1 1. External Bus Interface (EBI) Overview....................................................................................................3 2. Hardware Implementation Examples...................................................................................................... 4 2.1. SDR and LP-SDR SDRAMs on 6-Layer PCB Layout.................................................................. 4 2.2. SDR and LP-SDR SDRAMs on 4-Layer PCB Layout.................................................................. 6 2.3. LP-DDR SDRAM on 6-Layer PCB Layout....................................................................................7 2.4. DDR2 SDRAM on 4-Layer PCB Layout....................................................................................... 9 2.5. Stack-Up Recommendations for 4- and 6-Layer PCBs..............................................................10 3. Software Implementation Considerations............................................................................................. 13 3.1. SDR SDRAM Initialization..........................................................................................................13 3.2. LP-SDR SDRAM Initialization.................................................................................................... 14 3.3. LP-DDR SDRAM Initialization.................................................................................................... 15 3.4. DDR2 SDRAM Initialization........................................................................................................16 3.5. Table Notes................................................................................................................................ 18 4. Appendix............................................................................................................................................... 19 4.1. Bit and Byte Swapping............................................................................................................... 19 4.2. Good Practices...........................................................................................................................20 5. Revision History.................................................................................................................................... 21 5.1. Rev. A - 11/2019.........................................................................................................................21 The Microchip Website.................................................................................................................................22 Product Change Notification Service............................................................................................................22 Customer Support........................................................................................................................................ 22 Microchip Devices Code Protection Feature................................................................................................22 Legal Notice................................................................................................................................................. 22 Trademarks.................................................................................................................................................. 23 Quality Management System....................................................................................................................... 23 Worldwide Sales and Service.......................................................................................................................24 © 2019 Microchip Technology Inc. Application Note DS00003310A-page 2 AN3310 External Bus Interface (EBI) Overview 1. External Bus Interface (EBI) Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded SAM9X60 memory controller. The static memory, MPDDR, SDRAM and ECC controllers are featured external memory controllers on the EBI. These controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash and (DDR2/LP-DDR/SDR/LP-SDR) SDRAM. The EBI operates with 1.8V or 3.3V power supplies (VDDIOM and VDDNF). Before connecting a memory to the EBI, refer to table “EBI Pins and External Device Connections”, in chapter “External Bus Interface (EBI)” of the SAM9X60 data sheet for the correct connections between the EBI controller pins and the interfaced device pins. Note: For DDR2, addresses A0, A1 and A12 are not used on the controller side. Addresses A2 to A11 are connected to A0 to A9 on the memory side, signal SDA10 is connected to A10, addresses A13 to A15 are connected to the last three addresses on the memory side and A16 to A18 are connected to BA0 to BA2. Choose the DDR_CAL value depending on the memory used: • 20kΩ for LP-SDR, LP-DDR and DDR2 SDRAM types • 16.9kΩ for SDR SDRAM Then, connect the DDR_VREF pin to the correct voltage: • VDDIOM/2 for DDR2 and LP-DDR SDRAM types • GND for SDR and LP-SDR SDRAM types For more information, refer to section “DDR/SDR I/O Calibration and DDR Voltage Reference”, in chapter “Memories” of the SAM9X60 data sheet. © 2019 Microchip Technology Inc. Application Note DS00003310A-page 3 AN3310 Hardware Implementation Examples 2. Hardware Implementation Examples This section shows hardware design examples implementing all supported memory types. Extra examples can be found in section “Implementation Examples”, in chapter “External Bus Interface (EBI)” of the SAM9X60 data sheet. Each subsection features schematics describing how to connect the MPU to the related memory device, the resulting layout and the configuration settings corresponding to each type of memory. 2.1 SDR and LP-SDR SDRAMs on 6-Layer PCB Layout Because SDR and LP-SDR SDRAMs have the same pinout, only one implementation example, applicable to both, is presented. Care must be taken when choosing the voltage value for the VDDIOM supply, as SDR memories need 3.3V while LP- SDR memories are powered at 1.8V. 2.1.1 Schematic Figure 2-1. LP-SDR Implementation on 6-Layer PCB Layout SDR-ADDRESS COU1E COU23 i U1E U23 MT48H32M16LFB4-6 IT:C B10 H16 NLSDR0D0SDR_D0 SDR_A2 H7 A8 SDR_D0 PIU10B10 A0 D0PIU10H16 COTP36TP36 PITP3601 PIU230H7 A0 DQ0PIU230A8 PITP3701 TP37COTP37 G16 H10 NLSDR0D1SDR_D1 SDR_A3 H8 B9 SDR_D1 PIU10G16 A1 D1PIU10H10 COTP38TP38 PITP3801 PIU230H8 A1 DQ1PIU230B9 PITP3901 TP39COTP39 NLSDR0A2SDR_A2 A13 H15 NLSDR0D2SDR_D2 SDR_A4 J8 B8 SDR_D2 PIU10A13 A2 D2PIU10H15 PIU230J8 A2 DQ2PIU230B8 NLSDR0A3SDR_A3 D15 H11 NLSDR0D3SDR_D3 SDR_A5 J7 C9 SDR_D3 PIU10D15 A3 D3PIU10H11 PIU230J7 A3 DQ3PIU230C9 NLSDR0A4SDR_A4 B12 J14 NLSDR0D4SDR_D4 SDR_A6 J3 C8 SDR_D4 PIU10B12 A4 D4PIU10J14 PIU230J3 A4 DQ4PIU230C8 NLSDR0A5SDR_A5 E11 J11 NLSDR0D5SDR_D5 SDR_A7 J2 D9 SDR_D5 PIU10E11 A5 D5PIU10J11 PIU230J2 A5 DQ5PIU230D9 NLSDR0A6SDR_A6 A12 J16 NLSDR0D6SDR_D6 SDR_A8 H3 D8 SDR_D6 PIU10A12 A6 D6PIU10J16 PIU230H3 A6 DQ6PIU230D8 NLSDR0A7SDR_A7 B16 J13 NLSDR0D7SDR_D7 SDR_A9 H2 E9 SDR_D7 PIU10B16 A7 D7PIU10J13 PIU230H2 A7 DQ7PIU230E9 NLSDR0A8SDR_A8 F16 G9 NLSDR0D8SDR_D8 SDR_A10 H1 E1 SDR_D8 PIU10F16 A8 D8PIU10G9 PIU230H1 A8 DQ8PIU230E1 NLSDR0A9SDR_A9 D14 D8 NLSDR0D9SDR_D9 SDR_A11 G3 D2 SDR_D9 PIU10D14 A9 D9PIU10D8 PIU230G3 A9 DQ9PIU230D2 NLSDR0A10SDR_A10 C11 F9 NLSDR0D10SDR_D10 SDR_SDA10 H9 D1 SDR_D10 PIU10C11 A10 D10PIU10F9 PIU230H9 A10 DQ10PIU230D1 NLSDR0A11SDR_A11 E13 A9 NLSDR0D11SDR_D11 SDR_A13 G2 C2 SDR_D11 PIU10E13 A11 D11PIU10A9 COTP40TP40 PITP4001 PIU230G2 A11 DQ11PIU230C2 A11 F10 NLSDR0D12SDR_D12 SDR_A14 G1 C1 SDR_D12 PIU10A11 A12 D12PIU10F10 COTP41TP41 PITP4101 PIU230G1 A12 DQ12PIU230C1
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