Lecture 13 - Linear Equivalent Circuits - Outline • Announcements Exam Two - Coming Next Week, Nov
6.012 - Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline • Announcements Exam Two - Coming next week, Nov. 5, 7:30-9:30 p.m. • Review - Sub-threshold operation of MOSFETs • Review - Large signal models, w. charge stores p-n diode, BJT, MOSFET (sub-threshold and strong inversion) • Small signal models; linear equivalent circuits General two, three, and four terminal devices pn diodes: Linearizing the exponential diode Adding linearized charge stores BJTs: Linearizing the F.A.R. β-model Adding linearized charge stores MOSFETs: Linearized strong inversion model Linearized sub-threshold model Adding linearized charge stores
Clif Fonstad, 10/27/09 Lecture 13 - Slide 1 Sub-threshold Operation of MOSFETs, cont. - The barrier at the n+-p junction is lowered near the oxide-Si
interface for any vGS > VFB. - The barrier is lowered by φ(x) - φp for 0 < x < xD. Plot vs y (This is the effective vBE on the lateral BJT between x and x + dx.) at fixed x, φ(0,y) VFB < vGS < VT 0 < x < xD. G vDS > 0 -t S D ox φn++ vDS 0 Injection xD φ - n+ n+ p n+ φp φ(x) tn+ y 0 φ(x)-φp L v = 0 B φ(x) BS φ x y p 0 L Plot vs x - The barrier lowering vGS at fixed y, (effective forward bias) - φ 0 < y < L. p φ(0) (1) is controlled by vGS, φm and (2) decreases x -tox xd quickly with x. vBE,eff(x) φp = [φ(x)− φp] Clif Fonstad, 10/27/09 Injection occurs over this range, Lecture 13 - Slide 2 but is largest near x = 0. Sub-threshold Operation of MOSFETs, cont.
- To calculate iD, we first find the current in each dx thick slab:
V < v < V G v > 0 S FB GS T DS D
-tox 0 x x+dx n+ p n+
xD
vBS = 0 y 0 L x #qv / kT q"(x,vGS )/ kT q"(x,vGS )/ kT n' x,L " n' x,0 e DS n'(x,0) = ni (e #1) $ nie ( ) ( ) n'(x,0) " n'(x,L) W di (x) = qD W dx # D qn 1" e"qvDS / kT ) eq$(x,vGS )/ kT dx D e L L e i ( ) !Clif Fonstad, 10/27/09 ! Lecture 13 - Slide 3
! Sub-threshold Operation of MOSFETs, cont.
- Integrating this from x = 0 to x = xD using the approximate value for the integral derived in Lecture 9, and approximating the
relationship between Δφ(0) and ΔvGS as linear, i.e. Δφ(0) ≈ ΔvGS/n, we arrived at: $ ' 2 W * kT q{vGS "VT } nkT "qvDS / kT iD, s"t (vGS ,vDS ,0) # µ e Cox & ) [n "1] e (1" e ) L % q ( & * where ( 1 # qN ( n " '1 + Si A + = - C* 2 2 )( ox [$ % p ] ,( ! Variations on this form:
It is common to see iD,s-t written using the factors K and γ we defined earlier, and with kT/q replaced by Vt, the thermal voltage, and [n -1] replaced! in the pre-factor. Written this way, we have:
2 $ {vGS "VT } nVt "vDS /Vt iD,s"t (vGS,vDS ,0) # K Vt e (1" e ) 2 ["2% p ] with ( , 2$SiqNA W * * " * " # * , K # µeCox, n(vBS ) % )1 + - Cox L 2 2 v +* [& ' p & BS ] .* Clif! Fonstad, 10/27/09 Lecture 13 - Slide 4
! Sub-threshold Output Characteristic
- We plot a family of iD vs vDS curves with (vGS - VT) as the family variable, after first defining the sub-threshold diode saturation
current, IS,s-t: 2 $ 2 IS,s"t # K Vt = KVt [n "1] 2 ["2% p ]
log iD,s-t
x -1 (vGS-VT) = -0.06 n Volts 10 IS,s-t !
x -2 (vGS-VT) = -0.12 n Volts 10 IS,s-t
(v -V ) = -0.18xn Volts -3 GS T 10 IS,s-t
(v -V ) = -0.24xn Volts -4 GS T 10 IS,s-t
vDS
{vGS VT } nVt vDS /Vt iD,s t (vGS,vDS ,0) IS,s te (1 e )
Clif Fonstad, 10/27/09 Lecture 13 - Slide 5