EUV: The Computational Landscape
Vivek Singh Intel Fellow Director, Computational Lithography Technology Manufacturing Group Intel Corporation
EUVL Workshop, 2014 Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO – “Double” patterning – EUV lithography
Computational techniques for EUV – Flare – Shadowing – Out of band radiation
V. Singh EUVL Workshop, 2014 2 Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO – “Double” patterning – EUV lithography
Computational techniques for EUV – Flare – Shadowing – Out of band radiation
V. Singh EUVL Workshop, 2014 3 The World Ahead Connecting People to a World of Opportunity
Access Connectivity Education Healthcare
Making Extending Transforming Delivering Technology Broadband Education To Innovative Available To Connections Improve Teaching Healthcare More People And Learning Solutions
V. Singh EUVL Workshop, 2014 4 Needs a Continuum of Personal Computing Experiences
Desktops Laptops Ultrabook™ Tablets Smartphones Intelligent Systems
V. Singh EUVL Workshop, 2014 5 And that needs leading edge technology Every new node: more performance on more features at lower power
65nm 45nm 32nm 22nm
1x
0.1x
0.01x
Lower Lower Transistor Leakage 0.001x
* projected
Higher Transistor Performance (Switching Speed)
Source: Intel
V. Singh EUVL Workshop, 2014 6 Such as… 3D transistors!
Intel 22nm technology introduces revolutionary 3-D Tri-Gate transistors
V. Singh EUVL Workshop, 2014 7 Real, high volume stuff
V. Singh EUVL Workshop, 2014 8 22nm Tri-Gate Transistor Benefits
Moore’s Law, at its heart, is about continuing innovation to give the world what it wants
V. Singh EUVL Workshop, 2014 9 But can we afford Moore’s Law?
1010 10 As the number 109 0 10 of transistors 10-1 goes UP 108
The -2 $ 10 107 Benefit: 10-3 Price per transistor goes 106 -4 10 DOWN 105 10-5
-6 104 10 Source: -7 WSTS/Gartner/Intel 10 103 ’70 ’80 ’90 ’00 The FAB $4 B Cost: PILOT LINE $1-2 B
Source: R&D PROCESS TEAM $0.5-1 B Intel Yes. It makes our gadgets cheaper. V. Singh EUVL Workshop, 2014 10 The End of Scaling is Near? Various industry comments over the past 30 years
“Optical lithography will reach its limits in the range of 0.75-0.50 microns”
“Minimum geometries will saturate in the range of 0.3 to 0.5 microns”
“X-ray lithography will be needed below 1 micron”
“Minimum gate oxide thickness is limited to ~2 nm”
“Copper interconnects will never work” Source: Mark “Scaling will end in ~10 years” Bohr ISSCC keynote, Feb. To paraphrase Mark Twain, rumors of 2009 Scaling’s death are greatly exaggerated
In 2014, things look no different
V. Singh EUVL Workshop, 2014 11 Innovation-Enabled Technology Pipeline is Full
Our limit to visibility goes out ~10 years
V. Singh EUVL Workshop, 2014 12 Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO – “Double” patterning – EUV lithography
Computational techniques for EUV – Flare – Shadowing – Out of band radiation
V. Singh EUVL Workshop, 2014 13 Moore’s Law: circa 2008
Intel® Atom™ - dual-core Rice – single grain
47 Million Transistors 45nm node Hi-k Metal Gate 193 dry Litho
In 2012, on 22nm technology, the above chip would be ¼ the size - Smaller than the grain of rice!
V. Singh EUVL Workshop, 2014 14 Moore’s Law: circa 2010
Intel® Xeon® 5500 Processor Intel® “Westmere-EP” Processor (Gainstown), 45 nm Hi-k (Gulftown), 32 nm 2nd Generation Hi-k 731M Transistors, 4 Core, 8 MB Cache 1.17B Transistors, 6 Core, 12 MB Cache
50% More Cores 45 nm 50% More Cache 32 nm
1.8x transistors/mm2
263 mm2 240 mm2
Perf. 130W 4 Core, 3.33 GHz 6 Core, 3.33 GHz
Volume 95W 4 Core, 2.93 GHz 6 Core, 2.93 GHz
V. Singh EUVL Workshop, 2014 15 Moore’s Law: circa 2012
22nm Intel Microprocessor codenamed Ivy Bridge (image released at Sept IDF)
V. Singh EUVL Workshop, 2014 16 Too small for the light we use… …have to find ways to bridge the gap
1 1000
Wavelength 248nm 193nm
micron 0.1 Co-optimization100 nm Computational Litho Multi-patterning
32nm 22nm EUV Feature Size 13.5nm 14nm 0.01 10 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025
V. Singh EUVL Workshop, 2014 17 Co-optimization: Living within your means
90nm 65nm 45nm/32nm • All gates in one direction • All gates in one direction • All gates in one direction except SRAM. everywhere. and one pitch. • Different rules for minimum • Trench contact local pitch, larger gate pitch and routing replaces orthogonal gate routing. to gate routing.
45nm 32nm
V. Singh EUVL Workshop, 2014 18 Layout has adapted to litho constraints, without affecting Moore’s march 65 nm Layout Style 32 nm Layout Style
• Bi-directional features • Uni-directional features • Varied gate dimensions • Uniform gate dimension • Varied pitches • Gridded layout M. Bohr, ISCC, 2009
V. Singh EUVL Workshop, 2014 19 Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO – “Double” patterning – EUV lithography
Computational techniques for EUV – Flare – Shadowing – Out of band radiation
V. Singh EUVL Workshop, 2014 20 Lithography stepper, simplified
Light Source Image Lens Mask
Wafer When feature is small, image is blurred
V. Singh EUVL Workshop, 2014 21 Can we “bend” light by inverting the problem?
Target Image
Light Source Lens Mask
Wafer Given an image, what mask and source do I need?
V. Singh EUVL Workshop, 2014 22 Answer: Inverse Lithography (ILT) Input = design, Output = mask + source
Target Image
Light Source Computational Litho Software Mask
Wafer
V. Singh EUVL Workshop, 2014 23 Increasing need for mask “correction”
no correction dog ears model-based OPC + rule based OPC assist features
1990 2000 2010
From simple decorations to complex “distortions” Intuition finally breaks down, optimal solution comes from math/computation
ILT V. Singh EUVL Workshop, 2014 24 ILT is non-intuitive
V. Singh EUVL Workshop, 2014 25 Changing shape of light source helps
Traditional light sources
lens must capture at least two diffracted orders
Normal Incidence Oblique Incidence light ray light ray
ILT source
-1 +1 0
V. Singh EUVL Workshop, 2014 26 Solving the two problems simultaneously
+
ILT+SMO are used to sharpen the image of critical masks for 14nm and 10nm nodes
V. Singh EUVL Workshop, 2014 27 Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO – “Double” patterning – EUV lithography
Computational techniques for EUV – Flare – Shadowing – Out of band radiation
V. Singh EUVL Workshop, 2014 28 Double Patterning: Capability…..with headaches!
A A A A A B A B A A B A C A B A
Conventional Pitch Halving Pitch Quartering All linewidths 2 linewidth types 3 linewidth types correlated A & B anti-correlated A uncorrelated B & C anti-correlated Problems: Cost, Complexity, Design Impact
V. Singh EUVL Workshop, 2014 29
Pitch halving and gate CD matching
860 1262 A A A 1264 1266
B B B B SRAM Vccmin SRAM
Gate CD mismatch s Pitch halving eliminates the close correlation which currently exists between the CDs of adjacent gates This has implications for memory cells and other circuits which depend upon this CD matching C. Kenyon, TOK conf., Dec. 2008
V. Singh EUVL Workshop, 2014 30 Misalignment in double-patterning
Misalignment
Normalized IDSAT
Print 1 Print 2 Registration (nm) K. Kuhn, ICVC, 2009 Misalignment between the 2 exposures is a crucial liability for this technique and can limit its usability
Transistor parameters can be affected by asymmetry between the source and drain regions
V. Singh EUVL Workshop, 2014 31 EUV to the rescue! …can help contain rising cost of DP
Source: ITRS 2009
V. Singh EUVL Workshop, 2014 32 Single exposure EUV, simplified DRs
Advantages of EUV
High k1 relative to ArF Single exposure simplifies process flow
OPC is simpler
SE provides simpler DRs
Source: Obert Wood, EUV Workshop, July 2010 S. Sivakumar, SPIE 2011
V. Singh EUVL Workshop, 2014 33 Originally from S. Sivakumar, 2013 International Workshop on EUV Lithography The Challenges of EUV
Resists Tool Patterning requirements... Source Resolution – On track Availability - Critical LWR/Dose – Need high power Power - Critical Outgassing - Testing issues slow development Scanner Hardware IDM TPT requirements - On track Scanner outgassing requirements
Reticle Defectivity Killer defect impact >> wafer process defect impact – Need pellicle Mitigation strategies Reticle inspection - A-PI late, sources for A-PI, AIMS, A-BI are inadequate Patterned wafer inspection - not a substitute for A-PI or pellicle in HVM Alternative strategies
EUV HVM implementation depends on satisfactory progress on all these fronts! M. Phillips, SPIE, 2014 V. Singh EUVL Workshop, 2014 34 Short-term power outlook
• Need 40~80W stable MOPA+PP sources in the field linked to NXE:3300B scanners
• Not enough power for HVM, but enough to start TD and re-establish confidence in EUVL
• Seems achievable by Q1’14 given current status of program
• Need to look at remainder of EUV infrastructure and make sure it is on track for HVM introduction ~2017
M. Phillips, SPIE, 2014
V. Singh EUVL Workshop, 2014 35 The current lithography plan
Node Intel Approach 14nm ArF DP EUV Pilot Line 10nm ArF Extension EUV Pilot Line
V. Singh EUVL Workshop, 2014 36 Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO – “Double” patterning – EUV lithography
Computational techniques for EUV – Flare – Shadowing – Out of band radiation
V. Singh EUVL Workshop, 2014 37 Computational Lithography Infrastructure extends to EUV
Flare
Out-of-Band (OOB) Radiation
Computational Litho Infrastructure
Shadowing (Not to scale)
V. Singh EUVL Workshop, 2014 38 Lets start with Flare
0.166 1 PSF for r 600nm, zero otherwise r 2.39 nm2
0.2
4.00E-08 0.19 3.50E-08 0.18 3.00E-08 0.17 2.50E-08 0.16 PSFsc (1/nm2) 2.00E-08 0.15
1.50E-08 Flare
1.00E-08 0.14 10000 5.00E-09 5000 0.13 0 0.00E+00 y (nm) -5000 0.12
0 -10000
-8000 -6000
-10000 0.11
-4000
-2000
2000
4000
6000 8000
x (nm) 10000 0.1 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 80,000 90,000 100,000 Radial distance (nm)
After a sharp fall, PSF decays As a result, “far away” layout very slowly geometry affects local flare
V. Singh EUVL Workshop, 2014 39 Components of flare contributions
Short range (mm) component Long range (mm) component
V. Singh EUVL Workshop, 2014 40 Final flare result for 3mm2 patch
Max = 16.9% Min = 0.54% Rng = 16.4% Avg = 5.62%
V. Singh EUVL Workshop, 2014 41 Full Chip Flare Compensation
(work is in handling boundaries)
Effect of flare on Image intensity Domain with Flare Data
V. Singh EUVL Workshop, 2014 42 Modeling of Mask Shadowing
3. Calculate 1. Create Mask Geometry 2. Calculate E-fields Wafer Image
V. Singh EUVL Workshop, 2014 43 H-V Delta for 0.25NA vs 0.35NA
V. Singh EUVL Workshop, 2014 44 OOB: Out-of-band radiation Problem: Resist is more sensitive to OOB
Source: J. Roberts, R.Bristol. T. Younkin, T. Fedynyshyn, D. Astolfi, A.Cabral Proc. SPIE 7272 (2009) V. Singh EUVL Workshop, 2014 45 EUV image comparison with OOB (rigorous simulation is too slow) Resulting EUV+OOB images match within 0.003 (assuming 4% total flare from OOB).
EUV+OOB (fast)
EUV+OOB (rigorous)
V. Singh EUVL Workshop, 2014 46 Computational Litho for EUV is not a problem
V. Singh EUVL Workshop, 2014 47 “If you build it, they will come”
V. Singh EUVL Workshop, 2014 48 Summary
What the world wants (hint: 3D transistors) –Demand and Economics drive Moore’s Law
Lithography: Choices for 14 nm and 10 nm –Double Patterning is the workhorse, with caveats
Computational techniques for EUV –Computational Litho for EUV is not a problem
V. Singh EUVL Workshop, 2014 49 How will this mask print?
V. Singh EUVL Workshop, 2014 50 The image from 193 pixelation
V. Singh EUVL Workshop, 2014 51 …if you used EUV, however…
V. Singh EUVL Workshop, 2014 52 Acknowledgments
Kenny Toh, Principal Engineer
Sam Sivakumar, Intel Fellow, Director of Lithography
Yan Borodovsky, Senior Intel Fellow, Director of Advanced Lithography
Michael C. Mayberry, Intel Vice President, Director of Components Research
Mark Phillips, Senior Principal Engineer
Richard Schenker, Senior Principal Engineer
V. Singh EUVL Workshop, 2014 53