Strain Analysis in Daily Life Lecture 9 • Strained-Si Technology I: Device Physics – Background – Planar MOSFETs –FinFETs Reading: • Y. Sun, S. Thompson, T. Nishida, “Strain Effects in Semiconductors,” Springer, 2010. • multiple research articles (reference list at the end of this lecture) Mechanical Stress/Strain Analysis

Fs Stress: results from the repulsive electromagnetic force between Fn ionic cores when the lattice L ∆L atoms deviate from their equilibrium positions. Stress = lim Strain = lim

Stress Types Stress Tensor Extensional Shear

Tensile

Compressive

10/25/2013 Nuo Xu EE 290D, Fall 2013 2 Strain-Stress Relationship Elasticity Tensor: • assuming strain has linear response to stress (Hooke’s Law) • can be simplified into 3 independent variables, for cubic lattices (e.g. Si)

If x, y, z along main crystal axis: OR for a certain direction:

Extensional Strain/Stress

Shear Strain/Stress

10/25/2013 Nuo Xu EE 290D, Fall 2013 3 Impact of Strain on Semiconductors • Energy Band Splitting • Evs. k curvature change

Si

Ge

w/o s w/ hs w/ us  GaAs CB 4 2 VB HH 1GPa <110> LH Unstrained Compressive Y. Sun, JAP (2007) 10/25/2013 Nuo Xu EE 290D, Fall 2013 4 Strain Impact on Si Bandstructure: Planar N-MOSFET Gate Gate Gate [110] Source Drain Source Drain Source Drain Unstrained Longitudinal Vertical Electrons

Δ2 Electron

applying strain Energy Splitting E-k Curvature Lower DOS available for Sub-band reoccupation Change Scattering Lowered average m* Transport m* Reduced (Inter-valley) Reduction Scattering Rates

10/25/2013 Nuo Xu EE 290D, Fall 2013 K. Uchida, IEDM (2008) 5 Strain Impact on Si Bandstructure: Planar P-MOSFET

[110] Gate Gate Gate Source Drain Source Drain Source Drain Unstrained Longitudinal Vertical Holes

Heavy Hole Light Hole Split-off Hole

applying strain Energy Splitting E-k Curvature Change Lower DOS available for Sub-band reoccupation Transport m* Reduction Scattering Lowered average m* Reduced (Inter-sub-band) Scattering Rates

10/25/2013 Nuo Xu EE 290D, Fall 2013 6 Strain Enhancement on Si MOSFET Carrier Mobility [110] Electron Hole

D. Esseni, JCE (2009) F. Conzati, SSE (2009) • For N-MOSFET, electron mobility enhancement saturates at ~1.5 GPa <110>-uniaxial tensile stress . • For P-MOSFET, hole mobility enhancement saturates at very high <110>-uniaxial compressive stress.

10/25/2013 Nuo Xu EE 290D, Fall 2013 7 Impact of Quantum Confinement Electrons under Biaxial Tensile Stress Holes under Uniaxial Comp. Stress

O. Weber, IEDM (2007) E. X. Wang, TED (2006)

• N-MOSFET: e% degrades at higher Eeff, due to the quantum confinement counters the strain-induced sub-band splitting. * • P-MOSFET: h% maintains vs. Eeff due to the dominant m reduction.

10/25/2013 Nuo Xu EE 290D, Fall 2013 8 Analytical Modeling for Carrier Mobility Enhancement due to Strain • Piezoresistance (PR) Model  Too simple  Limited predictive ability

(by ignoring Eeff, Strain- dependence…) • Sub-band Reoccupation Model

 Analytically models the energy-band top and m* change vs. strain  Trade-off between computing loads and accuracy

J.-S. Lim, EDL (2004) 10/25/2013 Nuo Xu EE 290D, Fall 2013 9 Numerical Approach: Self-Consistent Poisson-Schrödinger Simulation

scPS Approach 6x6 Luttinger-Kohn Hamiltonian for Holes

Schrödinger equation  L  2 PQ L  M02  M  222 22  2  Pkkk () d   2m 1 x yz   3  0 ez() () z   E () z LPQ 02  M Q  L *2 nnn  2  2 2mdzz   Qkkk  (2)22 2  3  2 x yz   M 02PQ L L Q 2m0 2 2 gn   nz() dkfE ( ) (,) kz  L  nn2  k 02MLPQM  2 2   2   k   Lkikk3( 3 x yz )  m  L 3  0  22QLMP 0 2  2  2  22 nz() n () z   M 3[23 (kkxy  )  ikk 2 xy ) n 3 L 2m   220MLQ  P 0 n  2 2  ddz () ()z eNDA N pz () nz ()  Impacts of strain on energy-band dz dz  top as well as curvature change Poisson equation will be completely included into the Hamiltonian.  Computationally intensive.

10/25/2013 Nuo Xu EE 290D, Fall 2013 10 Impact of Si Body Thickness Scaling

[110] scPS simulations, N. Xu, VLSI-T (2011)

N-Channel (Electron) P-Channel (Hole) 400 0.35 1.4 160 Electron Mobility Change Change Mobility Electron 380 0.30 1.2 Change Hole Mobility ) 140 1GPa Longi. Comp.

) 1.0 /V.s 0.25 2 360 1GPa Longitudinal Tensile 1GPa Verti. Tens. 1GPa Trans. Tens. /V.s cm 1GPa Vertical Compressive 2 0.8 ( 120 Unstrained 0.20 Unstrained

340 cm ( 0.6 0.15 100 320 0.4

(100)/<110> 0.10 80 ( N =1.0e13cm-2  300 inv 0.2 h (  0.05  Hole Mobility Mobility Hole h Electron Mobility

60 ) e

 0.0 280 -2 e (100)/<110> P =1.0e13cm 0.00 ) inv 40 4 6 8 10 12 14 4 6 8 10 12 14 Silicon Film Thickness (nm) Silicon Film Thickness (nm)

• Stress enhancement diminishes for electrons as tSOI scaled below 5nm, but not for holes.

10/25/2013 Nuo Xu EE 290D, Fall 2013 11 Impact of tSi Scaling on Piezoresistive Coefficients [110] Open symbols  Simulated Closed Symbols  Measured N-Channel (Electron) P-Channel (Hole) 80 20  zz 60 ) )

-1 Vertical  zz 10 -1 

Pa Transverse  xx yy Pa 40 Longitudinal 

-11 xx Longitudinal  -11 10 0 xx Transverse  (

10 yy  Uchida, IEDM 04,08 ( 20 yy Vertical  -10 Xu, VLSI 11 zz

Uchida, IEDM 08 0 Xu, VLSI 11 -20 -20 -30  xx  Piezo-Coefficient yy -40 Piezo-Coefficient -40  zz -50 -60 246810122 4 6 8 10 12 Silicon Body Thickness (nm) Silicon Body Thickness (nm)

• As tSi decreases, Πxx decreases due to diminished sub-band reoccupation and inter-valley scattering reduction. N. Xu, SOI Conf. (2012)

10/25/2013 Nuo Xu EE 290D, Fall 2013 12 Strain Enhancement on FinFET [110] Carrier Mobility: Electrons (110)-sidewall N-FinFET Unstrained Strained

nd ∆4, 2 st ∆2,1 st ∆4, 1 (100)-sidewall N-FinFET (110)-sidewall N-FinFET

N. Serra, TED (2010) 10/25/2013 Nuo Xu EE 290D, Fall 2013 13 Strain Enhancement on FinFET Carrier Mobility: Holes

Equi-energy contours from the 1st HH

Planar MOSFET (100)/<110> (100) Surface

[110]

FinFET (110)/<110>

[110] (110) Surface

unstrained σx = -1 GPa

Courtesy of L. Smith (Synopsys)

10/25/2013 Nuo Xu EE 290D, Fall 2013 14 Impact of Fin Width Scaling on

[110] Piezoresistive Coefficients Open symbols  Simulated Closed Symbols  Measured N-Channel (Electron) P-Channel (Hole) 80 80  60

zz ) ) -1

-1 60  Pa Pa 40 xx -11

-11 40 Saitoh, VLSI 08 20 Xu, EDL 12 Shin, EDL 06 20 Xu, EDL 12 Saitoh, VLSI 08 Serra, TED 10 Suthram, EDL 08 Krishinamohan, IEDM 08 Suthram, EDL 08 0 0  yy  -20 zz -20 -40  Piezo-Coefficient (10 Piezo-Coefficient Piezo-Coefficient (10 xx -40  yy -60 6 9 12 15 18 21 24 6 9 12 15 18 21 24 Silicon Fin Width (nm) Silicon Fin Width (nm) • No substantial degradation in piezo-resistance is seen with decreasing fin width. N. Xu, SOI Conf. (2012)

10/25/2013 Nuo Xu EE 290D, Fall 2013 15 Impact of Fin Aspect-Ratio

scPS simulations, N. Xu, IEDM (2010) N-Channel (Electron) P-Channel (Hole)

12 -2 Open: H = 58nm, W = 20nm 400 N = 9x10 cm 500 Si Si inv Filled: H = 20nm, W = 58nm Si Si CESL(Uniaxial) /Vs)

2 Biaxial Compressive

/Vs) 400 2 Biaxial Tensile 300 <110> Fin

<100> CESL (Uniaxial) 300 <100> Biaxial Tensile 200 <110> CESL (Uniaxial) <110> Biaxial Tensile 200 Hole Mobility (cm Mobility Hole Open: H = 58nm, W = 20nm Electron Mobility (cm Electron Si Si P =1x1013cm-2 Filled: H = 20nm, W = 58nm inv Si Si 100 100 0 200 400 600 800 1000 1200 1400 0 200 400 600 800 1000 1200 1400 Stress (MPa) Stress (MPa)

• μn is highest for <100> uniaxial-strained Tri-Gate, μp is highest for <110> uniaxial-strained Tri-Gate at high level stress.

10/25/2013 Nuo Xu EE 290D, Fall 2013 16 Strain Enhancement on Short-Channel MOSFET Performance Expt. results, N. Xu, VLSI-T (2011,2012)

Mobility vs. Gate Length ΔION/ION vs. Δidlin/I dlin under strain 12 14 p-channel FDSOI S = 0.59

Long Channel +12% 10 Lg = 30nm ~ 80nm 12 -2 P =7.0e12cm inv 8 |=1V (%)

10 ds Forward Back Bias

6 V = -0.5 ~ -1.0V S = 0.54 8 back 300K 4 P =9.5e12cm-2 6 inv Increase @ |V on short channel % I 2 Wafer Bending S = -70 ~ -170MPa 4 I % xx d,lin

Stress-induced Enhancement (%) 0 30 40 50 60 70 80 90 100 0 2 4 6 8 101214161820 I Increase @ |V |=10mV (%) Gate Length (nm) d,lin ds

• Enhancement in apparent mobility is maintained vs. Lg scaling.

• ~50% of Δµ/µ can be transferred to ΔION/ION. 10/25/2013 Nuo Xu EE 290D, Fall 2013 17 References 1. Y. Sun et al., “Physics of Strain Effects in Semiconductors and metal-oxide-semiconductor field- effect transistors,” Journal of Applied Physics, 101, 104503, 2007. 2. F. Conzati et al., ”Drain Current Improvements in Uniaxially Strained P-MOSFETs: A Multi-Subband Monte Carlo Study,” Solid-State Electronics, vol.53, pp.706-711, 2009. 3. D. Esseni et al.,”Semi-Classical Transport Modeling of CMOS Transistors with Arbitrary Crystal Orientations and Strain Engineering,” Journal of Computational Electronics, vol.8, pp.209-224, 2009. 4. N. Xu et al., “Stress-induced Performance Enhancement in Ultra-Thin-Body Fully Depleted SOI MOSFETs: Impacts of Scaling,” Symposium on VLSI Technology Dig., p.162-163, 2011. 5. K. Uchida et al., “Physical Mechanisms of Electron Mobility Enhancement in Uniaxial Stressed MOSFETs and Impacts of Uniaxial Stress Engineering in Ballistic Regime,” IEEE International Electron Device Meeting, Tech. Dig., p.229-232, 2004. 6. K. Uchida et al., “Carrier Transport and Stress Engineering in Advanced Nanoscale Transistors From (100) and (110) Transistors To Carbon Nanotube FETs and Beyond,” IEEE International Electron Device Meeting, Tech. Dig., p.569-572, 2008. 7. N. Serra et al., ”Mobility Enhancement in Strained n-FinFETs: Basic Insight and Stress Engineering,” IEEE Transactions on Electron Devices, vol.57, p.482-490, 2010. 8. T. Krishnamohan et al., “Comparison of (001), (110) and (111) Uniaxial- and Biaxial- Strained-Ge and Strained-Si PMOS DGFETs for All Channel Orientations: Mobility Enhancement, Drive Current, Delay and Off-State Leakage,” IEEE International Electron Device Meeting, Tech. Dig., p.899-902, 2008. 9. M. Saitoh et al., ”Three-Dimensional Stress Engineering in FinFETs for Mobility/On-Current Enhancement and Gate Current Reduction,” Symposium on VLSI Technology Dig., p.18-19, 2008. 10. K. Shin et al., “Study of Bending-Induced Strain Effects on MuGFET Performance,” IEEE Electron Device Letters, vol.27, p.671-673, 2006.

10/25/2013 Nuo Xu EE 290D, Fall 2013 18 References 11. S. Suthram et al., “Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs,” IEEE Electron Device Letters, vol.29, p.480-482, 2008. 12. J.-S. Lim et al., “Comparison of Threshold Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed n-MOSFETs,” IEEE Electron Device Letters, vol.25, no.11, pp.731-733, 2004. 13. E. X. Wang et al., “Physics of Hole Transport in Strained Si MOSFET Inversion Layers,” IEEE Transactions on Electron Devices, vol.53, no.8, pp.1840-1851, 2006. 14. O. Weber et al., “Examination of Additive Mobility Enhancement for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs,” IEEE International Electron Device Meeting, Tech. Dig., p.719-722, 2007. 15. N. Xu et al., “MuGFET Carrier Mobility and Velocity: Impacts of Fin Aspect Ratio, Orientation and Stress,” IEEE International Electron Device Meeting, Tech. Dig., p.194-197, 2010. 16. N. Xu et al., “Impact of Back Biasing on Carrier Transport in Ultra-Thin Body and BOX (UTBB) Fully Depleted SOI MOSFETs,” Symposium on VLSI Technology Dig., p.113-114, 2012.

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