J Supercomput (2013) 66:431–487 DOI 10.1007/s11227-013-0916-9 High-performance optimizations on tiled many-core embedded systems: a matrix multiplication case study Arslan Munir · Farinaz Koushanfar · Ann Gordon-Ross · Sanjay Ranka Published online: 5 April 2013 © Springer Science+Business Media New York 2013 Abstract Technological advancements in the silicon industry, as predicted by Moore’s law, have resulted in an increasing number of processor cores on a single chip, giving rise to multicore, and subsequently many-core architectures. This work focuses on identifying key architecture and software optimizations to attain high per- formance from tiled many-core architectures (TMAs)—an architectural innovation in the multicore technology. Although embedded systems design is traditionally power- centric, there has been a recent shift toward high-performance embedded computing due to the proliferation of compute-intensive embedded applications. The TMAs are suitable for these embedded applications due to low-power design features in many of these TMAs. We discuss the performance optimizations on a single tile (processor core) as well as parallel performance optimizations, such as application decompo- sition, cache locality, tile locality, memory balancing, and horizontal communica- tion for TMAs. We elaborate compiler-based optimizations that are applicable to A. Munir () · F. Koushanfar Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA e-mail:
[email protected] F. Koushanfar e-mail:
[email protected] A. Gordon-Ross Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA e-mail:
[email protected]fl.edu A. Gordon-Ross NSF Center for High-Performance Reconfigurable Computing (CHREC), University of Florida, Gainesville, FL, USA S.