Powerhouse Performance with Intel® Core™ I9 Mobile Processor
Total Page：16
File Type：pdf, Size：1020Kb
Load more
Recommended publications
-
Webcore: Architectural Support for Mobile Web Browsing
WebCore: Architectural Support for Mobile Web Browsing Yuhao Zhu Vijay Janapa Reddi Department of Electrical and Computer Engineering The University of Texas at Austin [email protected], [email protected] Abstract The Web browser is undoubtedly the single most impor- Browser Browser tant application in the mobile ecosystem. An average user 63% 54% spends 72 minutes each day using the mobile Web browser. Web browser internal engines (e.g., WebKit) are also growing 23% 8% 32% Media 6% in importance because they provide a common substrate for 7% 7% Others developing various mobile Web applications. In a user-driven, Media Games Others interactive, and latency-sensitive environment, the browser’s Email performance is crucial. However, the battery-constrained na- (a) Time dist. of window focus. (b) Time dist. of CPU processing. ture of mobile devices limits the performance that we can de- Fig. 1: Mobile Web browser share study conducted by our industry liver for mobile Web browsing. As traditional general-purpose research partner on their employees’ devices [2]. Similar observa- techniques to improve performance and energy efficiency fall tions were reported by NVIDIA on Tegra-based mobile handsets [3,4]. short, we must employ domain-specific knowledge while still maintaining general-purpose flexibility. network limited. However, this trend is changing. With about In this paper, we first perform design-space exploration 10X improvement in round-trip time from 3G to LTE, network to identify appropriate general-purpose architectures that latency is no longer the only performance bottleneck [51]. uniquely fit the characteristics of a popular Web browsing Prior work has shown that over the past decade, network engine. -
EVA: an Efficient Vision Architecture for Mobile Systems
EVA: An Efficient Vision Architecture for Mobile Systems Jason Clemons, Andrea Pellegrini, Silvio Savarese, and Todd Austin Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, Michigan 48109 fjclemons, apellegrini, silvio, [email protected] Abstract The capabilities of mobile devices have been increasing at a momen- tous rate. As better processors have merged with capable cameras in mobile systems, the number of computer vision applications has grown rapidly. However, the computational and energy constraints of mobile devices have forced computer vision application devel- opers to sacrifice accuracy for the sake of meeting timing demands. To increase the computational performance of mobile systems we Figure 1: Computer Vision Example The figure shows a sock present EVA. EVA is an application-specific heterogeneous multi- monkey where a computer vision application has recognized its face. core having a mix of computationally powerful cores with energy The algorithm would utilize features such as corners and use their efficient cores. Each core of EVA has computation and memory ar- geometric relationship to accomplish this. chitectural enhancements tailored to the application traits of vision Watts over 250 mm2 of silicon, typical mobile processors are limited codes. Using a computer vision benchmarking suite, we evaluate 2 the efficiency and performance of a wide range of EVA designs. We to a few Watts with typically 5 mm of silicon [4] [22]. show that EVA can provide speedups of over 9x that of an embedded To meet the limited computation capability of mobile proces- processor while reducing energy demands by as much as 3x. sors, computer vision application developers reluctantly sacrifice image resolution, computational precision or application capabili- Categories and Subject Descriptors C.1.4 [Parallel Architec- ties for lower quality versions of vision algorithms. -
Memorandum in Opposition to Hewlett-Packard Company's Motion to Quash Intel's Subpoena Duces Tecum
ORIGINAL UNITED STATES OF AMERICA BEFORE THE FEDERAL TRADE COMMISSION ) In the Matter of ) ) DOCKET NO. 9341 INTEL. CORPORATION, ) a corporation ) PUBLIC ) .' ) MEMORANDUM IN OPPOSITION TO HEWLETT -PACKARD COMPANY'S MOTION TO QUASH INTEL'S SUBPOENA DUCES TECUM Intel Corporation ("Intel") submits this memorandum in opposition to Hewlett-Packard Company's ("HP") motion to quash Intel's subpoena duces tecum issued on March 11,2010 ("Subpoena"). HP's motion should be denied, and it should be ordered to comply with Intel's Subpoena, as narrowed by Intel's April 19,2010 letter. Intel's Subpoena seeks documents necessary to defend against Complaint Counsel's broad allegations and claimed relief. The Complaint alleges that Intel engaged in unfair business practices that maintained its monopoly over central processing units ("CPUs") and threatened to give it a monopoly over graphics processing units ("GPUs"). See CompI. iiii 2-28. Complaint Counsel's Interrogatory Answers state that it views HP, the world's largest manufacturer of personal computers, as a centerpiece of its case. See, e.g., Complaint Counsel's Resp. and Obj. to Respondent's First Set ofInterrogatories Nos. 7-8 (attached as Exhibit A). Complaint Counsel intends to call eight HP witnesses at trial on topics crossing virtually all of HP' s business lines, including its purchases ofCPUs for its commercial desktop, commercial notebook, and server businesses. See Complaint Counsel's May 5, 2010 Revised Preliminary Witness List (attached as Exhibit B). Complaint Counsel may also call HP witnesses on other topics, including its PUBLIC FTC Docket No. 9341 Memorandum in Opposition to Hewlett-Packard Company's Motion to Quash Intel's Subpoena Duces Tecum USIDOCS 7544743\'1 assessment and purchases of GPUs and chipsets and evaluation of compilers, benchmarks, interface standards, and standard-setting bodies. -
6Th Generation Intel® Core™ Processors Based on the Mobile U-Processor for Iot Solutions (Intel® Core™ I7-6600U, I5-6300U, and I3-6100U Processors)
PLATFORM BRIEF 6th Generation Intel® Core™ Mobile Processor Family Internet of Things 6th Generation Intel® Core™ Processors Based on the Mobile U-Processor for IoT Solutions (Intel® Core™ i7-6600U, i5-6300U, and i3-6100U Processors) Harness the Performance, Features, and Edge-to-Cloud Scalability to Build Tomorrow’s IoT Solutions Today Product Overview Stunning Visual Performance Intel is proud to announce its 6th The 6th generation Intel Core generation Intel® Core™ processor processors utilize the new Gen9 family featuring ultra low-power, graphics engine, which improves 64-bit, multicore processors built on graphic performance by up to the latest 14 nm technology. Designed 34 percent.1 The improvements are for small form-factor applications, this demonstrated through faster 3-D multichip package (MCP) integrates graphics performance and rendering a low-power CPU and platform applications at low power. Video controller hub (PCH) onto a common playback is also faster and smoother package substrate. thanks to the new multiplane overlay capability. The new generation offers The 6th generation Intel Core processor up to three independent audio streams family offers dramatically higher CPU and displays, Ultra HD 4K support, and and graphics performance, a broad workload consolidation for lower BOM range of power and features scaling costs and energy output. the entire Intel product line, and new, advanced features that boost edge-to- Users will also enjoy enhanced cloud Internet of Things (IoT) designs high-density streaming applications in a wide variety of markets. These and optimized 4K videoconferencing processors run at 15W thermal design with accelerated 4K hardware media power (TDP) and are ideal for small, codecs HEVC (8-bit), VP8, VP9, and energy-efficient, form-factor designs, VDENC encoding, decoding, and including digital signage, point-of-sale transcoding. -
PART I ITEM 1. BUSINESS Industry We Are
PART I ITEM 1. BUSINESS Industry We are the world’s largest semiconductor chip maker, based on revenue. We develop advanced integrated digital technology products, primarily integrated circuits, for industries such as computing and communications. Integrated circuits are semiconductor chips etched with interconnected electronic switches. We also develop platforms, which we define as integrated suites of digital computing technologies that are designed and configured to work together to provide an optimized user computing solution compared to ingredients that are used separately. Our goal is to be the preeminent provider of semiconductor chips and platforms for the worldwide digital economy. We offer products at various levels of integration, allowing our customers flexibility to create advanced computing and communications systems and products. We were incorporated in California in 1968 and reincorporated in Delaware in 1989. Our Internet address is www.intel.com. On this web site, we publish voluntary reports, which we update annually, outlining our performance with respect to corporate responsibility, including environmental, health, and safety compliance. On our Investor Relations web site, located at www.intc.com, we post the following filings as soon as reasonably practicable after they are electronically filed with, or furnished to, the U.S. Securities and Exchange Commission (SEC): our annual, quarterly, and current reports on Forms 10-K, 10-Q, and 8-K; our proxy statements; and any amendments to those reports or statements. All such filings are available on our Investor Relations web site free of charge. The SEC also maintains a web site (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC. -
NVIDIA Tegra 4 Family CPU Architecture 4-PLUS-1 Quad Core
Whitepaper NVIDIA Tegra 4 Family CPU Architecture 4-PLUS-1 Quad core 1 Table of Contents ...................................................................................................................................................................... 1 Introduction .............................................................................................................................................. 3 NVIDIA Tegra 4 Family of Mobile Processors ............................................................................................ 3 Benchmarking CPU Performance .............................................................................................................. 4 Tegra 4 Family CPUs Architected for High Performance and Power Efficiency ......................................... 6 Wider Issue Execution Units for Higher Throughput ............................................................................ 6 Better Memory Level Parallelism from a Larger Instruction Window for Out-of-Order Execution ...... 7 Fast Load-To-Use Logic allows larger L1 Data Cache ............................................................................. 8 Enhanced branch prediction for higher efficiency .............................................................................. 10 Advanced Prefetcher for higher MLP and lower latency .................................................................... 10 Large Unified L2 Cache ....................................................................................................................... -
Why 8Th Gen Intel® Core™ Vpro® Processors?
SALES BRIEF Why 8th Gen Intel® Core™ vPro® Processors? Top Reasons to Transition to 8th Gen Intel® Core™ vPro® Processors for Your Business PCs Lower support costs with Intel® Active The highest performing ultra-thin Management Technology (Intel® AMT) 1 notebook processor for business1 3 built into the Intel vPro® platform4 The 8th Gen Intel Core vPro processor adds performance— Intel AMT can help save IT time and money when managing 10 percent over the previous generation1—plus optimization a PC fleet. By upgrading to systems employing current and engineering for mobile performance. generation Intel Core vPro processors, organizations can help solve common IT issues with a more secure and manageable • Increased OEM expertise in power management is yielding system while reducing service delivery costs.4 systems that are power-efficient with long battery life. • Optimization for commercial—with Intel® Wireless-AC • Annual reduction of 7680 security support hours with Intel integrated into the Platform Controller Hub (PCH) vPro® platform-based devices, resulting in $1.2 million in risk-adjusted savings over 3 years and 832 hours saved • Windows integration: Modern devices with Windows® 10, with automatic remote patch deployment through Intel® Office 365, and the Intel vPro® platform enable fast startup, Active Management Technology, resulting in risk-adjusted amazing multitasking, and have long-lasting battery life2,3 cost savings of $81,000 over 3 years as estimated using a for anytime, anywhere productivity. composite organization modeled by Forrester Consulting In addition, the 8th Gen Intel Core vPro processor improves in an Intel commissioned TEI study. Read the full study at on the previous generation with: Intel.com/vProPlatformTEI.5 • Intel® Optane™ Memory H10: Accelerated systems • Intel® AMT can also help minimize downtime and help responsiveness create environments that are simpler to manage. -
Architectural Support for Javascript Type-Checking on Mobile Processors
Checked Load: Architectural Support for JavaScript Type-Checking on Mobile Processors Owen Anderson Emily Fortuna Luis Ceze Susan Eggers Computer Science and Engineering, University of Washington http://sampa.cs.washington.edu Abstract applications, including Google Maps, Twitter, and Face- book would not be feasible without both high-throughput Dynamic languages such as Javascript are the de-facto and low-latency JavaScript virtual machines on the client. standard for web applications. However, generating effi- At the same time, innovations in mobile device pro- cient code for dynamically-typed languages is a challenge, grammability have opened up embedded targets to the same because it requires frequent dynamic type checks. Our anal- class of programmers. Today’s smart mobile devices are ysis has shown that some programs spend upwards of 20% expected to provide a developer API that is usable by of dynamic instructions doing type checks, and 12.9% on normal application developers, as opposed to the special- average. ized embedded developers of the past. One such plat- In this paper we propose Checked Load, a low- form, HP/Palm’s WebOS [17], uses JavaScript as its pri- complexity architectural extension that replaces software- mary application development language. Others encourage based, dynamic type checking. Checked Load is comprised JavaScript-heavy web applications in addition to their na- of four new ISA instructions that provide flexible and au- tive development environments, as a means of providing tomatic type checks for memory operations, and whose im- feature-rich, portable applications with minimal develop- plementation requires minimal hardware changes. We also ment costs. propose hardware support for dynamic type prediction to Because of their power and space constraints, embedded reduce the cost of failed type checks. -
Intel® Core™2 Duo Mobile Processor for Intel® Centrino® Duo Mobile Processor Technology
Intel® Core™2 Duo Mobile Processor for Intel® Centrino® Duo Mobile Processor Technology Datasheet September 2007 Document Number: 314078-004 INFORMATIONLegal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. -
Intel® Processor Identification Utility Installation Guide for Windows*
Intel® Processor Identification Utility Installation Guide for Windows* Follow these steps to install the Microsoft Windows* version of the Intel® Processor Identification Utility. Users must have system administrator rights for successful installation with Windows XP* Note and Windows 2000*. 1. Download and save the Windows version of the Intel® Processor Identification Utility. 2. Click Windows Start, and browse the location for the Intel® Processor Identification Utility program. 3. Click the Intel® Processor Identification Utility program, click Open, and click OK. 4. Click Next at the InstallShield* wizard. If a previous version is installed, the InstallShield wizard provides three options: Modify, Note repair, and remove. The previous version of the Intel® Processor Identification Utility should be removed before installing the newer version. 5. At the Software License screen, click Agree to the terms of the license agreement and click Next. 6. In the custom setup installation screen, choose the destination location and folder name for the program installation. Click Next to continue. By default, the Intel® Processor Identification Utility is installed under the programs Note folder in the start menu. 7. Follow the on-screen installation instructions. 8. Click Finish in the Setup Complete window. The installation is now complete. You do not need to restart the computer before running the Intel® Processor Identification Utility. Running the Intel® Processor Identification Utility 1. Click Start > All Programs > Intel Processor ID Utility > Processor ID Utility. 2. At the Intel® Processor Identification Utility license agreement screen, click Accept. The Processor Identification Utility screen displays information about your processor. Intel® Processor Support for Microsoft Windows® 10 Identify the processor in your system. -
Design and Implementation of Low Power 5 Stage Pipelined 32 Bits MIPS Processor Using 28Nm Technology
International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-8 Issue-4S2 March, 20 Design and implementation of low power 5 stage Pipelined 32 bits MIPS Processor using 28nm Technology V.Prasanth, V.Sailaja, P.Sunitha, B.Vasantha Lakshmi processor. The operations used by MIPS processor in Abstract— MIPS is a simple streamlined highly scalable instruction set which are generally used to access memory in RISC architecture is most used in android base devices and best MIPS processor are load and Store and other operations suited for portable mobile devices. This Paper presents a design which are remaining are performed on register to register of 5 stage pipelined 32 bit MIPS processor on a 28nm basis [2] this results in more clear instruction set design Technology. The processor is designed using Harvard architecture. The most important feature of pipelining is where it allows execution of one instruction-per cycle rate. performance and speed of the processor, this results in increase The pipelining uses parallelism at instruction level to execute of device power. To reduce dynamic power using RTL clock multiple instructions simultaneously using a single processor gating inside FPGA device we presented a novel approach in this [2]. The major disadvantage with MIPS processor design is paper. Design functionality in terms of area power and speed is dynamic power consumption results due to clock power and analyzed using kintex 7 platform board. switching-activity. Clock Gating is a method which employed in the design to reduce power consumption [17] by Keywords: RISC,MIPS, Clock Gating, Dynamic Power, reducing switching activity of non active blocks. -
Designcon 2003 Tecforum I2C Bus Overview January 27 2003
DesignCon 2003 TecForum I2C Bus Overview January 27 2003 Philips Semiconductors Jean Marc Irazabal –Technical Marketing Manager for I2C Devices Steve Blozis –International Product Manager for I2C Devices Agenda • 1st Hour • Serial Bus Overview • I2C Theory Of Operation • 2nd Hour • Overcoming Previous Limitations • I2C Development Tools and Evaluation Board • 3rd Hour • SMBus and IPMI Overview • I2C Device Overview • I2C Patent and Legal Information • Q & A Slide speaker notes are included in AN10216 I2C Manual 2 DesignCon 2003 TecForum I C Bus Overview 2 1st Hour 2 DesignCon 2003 TecForum I C Bus Overview 3 Serial Bus Overview 2 DesignCon 2003 TecForum I C Bus Overview 4 Com m uni c a t i o ns Automotive SERIAL Consumer BUSES IEEE1394 DesignCon 2003 TecForum I UART SPI 2 C Bus Overview In d u s t r ia l 5 General concept for Serial communications SCL SDA select 3 select 2 select 1 READ Register or enable Shift Reg# enable Shift Reg# enable Shift Reg# WRITE? // to Ser. // to Ser. // to Ser. Shift R/W Parallel to Serial R/W R/W “MASTER” DATA SLAVE 1 SLAVE 2 SLAVE 3 • A point to point communication does not require a Select control signal • An asynchronous communication does not have a Clock signal • Data, Select and R/W signals can share the same line, depending on the protocol • Notice that Slave 1 cannot communicate with Slave 2 or 3 (except via the ‘master’) Only the ‘master’ can start communicating. Slaves can ‘only speak when spoken to’ 2 DesignCon 2003 TecForum I C Bus Overview 6 Typical Signaling Characteristics LVTTL 2 RS422/485