Cubesat and Mobile Processors
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Fill Your Boots: Enhanced Embedded Bootloader Exploits Via Fault Injection and Binary Analysis
IACR Transactions on Cryptographic Hardware and Embedded Systems ISSN 2569-2925, Vol. 2021, No. 1, pp. 56–81. DOI:10.46586/tches.v2021.i1.56-81 Fill your Boots: Enhanced Embedded Bootloader Exploits via Fault Injection and Binary Analysis Jan Van den Herrewegen1, David Oswald1, Flavio D. Garcia1 and Qais Temeiza2 1 School of Computer Science, University of Birmingham, UK, {jxv572,d.f.oswald,f.garcia}@cs.bham.ac.uk 2 Independent Researcher, [email protected] Abstract. The bootloader of an embedded microcontroller is responsible for guarding the device’s internal (flash) memory, enforcing read/write protection mechanisms. Fault injection techniques such as voltage or clock glitching have been proven successful in bypassing such protection for specific microcontrollers, but this often requires expensive equipment and/or exhaustive search of the fault parameters. When multiple glitches are required (e.g., when countermeasures are in place) this search becomes of exponential complexity and thus infeasible. Another challenge which makes embedded bootloaders notoriously hard to analyse is their lack of debugging capabilities. This paper proposes a grey-box approach that leverages binary analysis and advanced software exploitation techniques combined with voltage glitching to develop a powerful attack methodology against embedded bootloaders. We showcase our techniques with three real-world microcontrollers as case studies: 1) we combine static and on-chip dynamic analysis to enable a Return-Oriented Programming exploit on the bootloader of the NXP LPC microcontrollers; 2) we leverage on-chip dynamic analysis on the bootloader of the popular STM8 microcontrollers to constrain the glitch parameter search, achieving the first fully-documented multi-glitch attack on a real-world target; 3) we apply symbolic execution to precisely aim voltage glitches at target instructions based on the execution path in the bootloader of the Renesas 78K0 automotive microcontroller. -
MSP430FR2433 Mixed-Signal Microcontroller
Product Order Technical Tools & Support & Folder Now Documents Software Community MSP430FR2433 SLASE59C –OCTOBER 2015–REVISED AUGUST 2018 MSP430FR2433 Mixed-Signal Microcontroller 1 Device Overview 1.1 Features 1 • Embedded Microcontroller Storage – 16-Bit RISC Architecture – 1015 Write Cycle Endurance – Clock Supports Frequencies up to 16 MHz – Radiation Resistant and Nonmagnetic – Wide Supply Voltage Range From 3.6 V Down – High FRAM-to-SRAM Ratio, up to 4:1 to 1.8 V (Minimum Supply Voltage is Restricted • Clock System (CS) by SVS Levels, See the SVS Specifications) – On-Chip 32-kHz RC Oscillator (REFO) • Optimized Ultra-Low-Power Modes – On-Chip 16-MHz Digitally Controlled Oscillator – Active Mode: 126 µA/MHz (Typical) (DCO) With Frequency-Locked Loop (FLL) – Standby: <1 µA With VLO – ±1% Accuracy With On-Chip Reference at – LPM3.5 Real-Time Clock (RTC) Counter With Room Temperature 32768-Hz Crystal: 730 nA (Typical) – On-Chip Very Low-Frequency 10-kHz Oscillator – Shutdown (LPM4.5): 16 nA (Typical) (VLO) • High-Performance Analog – On-Chip High-Frequency Modulation Oscillator – 8-Channel 10-Bit Analog-to-Digital Converter (MODOSC) (ADC) – External 32-kHz Crystal Oscillator (LFXT) – Internal 1.5-V Reference – Programmable MCLK Prescalar of 1 to 128 – Sample-and-Hold 200 ksps – SMCLK Derived from MCLK With • Enhanced Serial Communications Programmable Prescalar of 1, 2, 4, or 8 – Two Enhanced Universal Serial Communication • General Input/Output and Pin Functionality Interfaces (eUSCI_A) Support UART, IrDA, and – Total of 19 I/Os on -
Webcore: Architectural Support for Mobile Web Browsing
WebCore: Architectural Support for Mobile Web Browsing Yuhao Zhu Vijay Janapa Reddi Department of Electrical and Computer Engineering The University of Texas at Austin [email protected], [email protected] Abstract The Web browser is undoubtedly the single most impor- Browser Browser tant application in the mobile ecosystem. An average user 63% 54% spends 72 minutes each day using the mobile Web browser. Web browser internal engines (e.g., WebKit) are also growing 23% 8% 32% Media 6% in importance because they provide a common substrate for 7% 7% Others developing various mobile Web applications. In a user-driven, Media Games Others interactive, and latency-sensitive environment, the browser’s Email performance is crucial. However, the battery-constrained na- (a) Time dist. of window focus. (b) Time dist. of CPU processing. ture of mobile devices limits the performance that we can de- Fig. 1: Mobile Web browser share study conducted by our industry liver for mobile Web browsing. As traditional general-purpose research partner on their employees’ devices [2]. Similar observa- techniques to improve performance and energy efficiency fall tions were reported by NVIDIA on Tegra-based mobile handsets [3,4]. short, we must employ domain-specific knowledge while still maintaining general-purpose flexibility. network limited. However, this trend is changing. With about In this paper, we first perform design-space exploration 10X improvement in round-trip time from 3G to LTE, network to identify appropriate general-purpose architectures that latency is no longer the only performance bottleneck [51]. uniquely fit the characteristics of a popular Web browsing Prior work has shown that over the past decade, network engine. -
Using Energia (Arduino)
Using Energia (Arduino) Introduction This chapter of the MSP430 workshop explores Energia, the Arduino port for the Texas Instruments Launchpad kits. After a quick definition and history of Arduino and Energia, we provide a quick introduction to Wiring – the language/library used by Arduino & Energia. Most of the learning comes from using the Launchpad board along with the Energia IDE to light LED’s, read switches and communicate with your PC via the serial connection. Learning Objectives, Requirements, Prereq’s Prerequisites & Objectives Prerequisites Basic knowledge of C language Basic understanding of using a C library and header files This chapter doesn’t explain clock, interrupt, and GPIO features in detail, this is left to the other chapters in the MSP430 workshop Requirements - Tools and Software Hardware Windows (XP, 7, 8) PC with available USB port MSP430F5529 Launchpad Software Already installed, if you Energia Download have installed CCSv5.x Launchpad drivers (Optional) MSP430ware / Driverlib Objectives Define ‘Arduino’ and describe what is was created for Define ‘Energia’ and explain what it is ‘forked’ from Install Energia, open and run included example sketches Use serial communication between the board & PC Add an external interrupt to an Energia sketch Modify CPU registers from an Energia sketch MSP430 Workshop - Using Energia (Arduino) 8 - 1 What is Arduino Chapter Topics Using Energia (Arduino) ............................................................................................................ -
EVA: an Efficient Vision Architecture for Mobile Systems
EVA: An Efficient Vision Architecture for Mobile Systems Jason Clemons, Andrea Pellegrini, Silvio Savarese, and Todd Austin Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, Michigan 48109 fjclemons, apellegrini, silvio, [email protected] Abstract The capabilities of mobile devices have been increasing at a momen- tous rate. As better processors have merged with capable cameras in mobile systems, the number of computer vision applications has grown rapidly. However, the computational and energy constraints of mobile devices have forced computer vision application devel- opers to sacrifice accuracy for the sake of meeting timing demands. To increase the computational performance of mobile systems we Figure 1: Computer Vision Example The figure shows a sock present EVA. EVA is an application-specific heterogeneous multi- monkey where a computer vision application has recognized its face. core having a mix of computationally powerful cores with energy The algorithm would utilize features such as corners and use their efficient cores. Each core of EVA has computation and memory ar- geometric relationship to accomplish this. chitectural enhancements tailored to the application traits of vision Watts over 250 mm2 of silicon, typical mobile processors are limited codes. Using a computer vision benchmarking suite, we evaluate 2 the efficiency and performance of a wide range of EVA designs. We to a few Watts with typically 5 mm of silicon [4] [22]. show that EVA can provide speedups of over 9x that of an embedded To meet the limited computation capability of mobile proces- processor while reducing energy demands by as much as 3x. sors, computer vision application developers reluctantly sacrifice image resolution, computational precision or application capabili- Categories and Subject Descriptors C.1.4 [Parallel Architec- ties for lower quality versions of vision algorithms. -
Design Considerations When Using the MSP430 Graphics Library, and Provides an Example of Implementation and Optimization
www.ti.com 1 Trademarks MSP430, MSP430Ware are trademarks of Texas Instruments. Stellaris is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. SLAA548–October 2012 1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Application Report SLAA548–October 2012 Design Considerations When Using MSP430 Graphics Library Michael Stein ABSTRACT LCDs are a growing commodity in today’s market with products as diverse as children’s toys to medical devices. Modern LCDs, along with the graphics displayed on them, are growing in complexity. A graphics library can simplify and accelerate development while creating the desired user experience. TI provides the MSP430 Graphics Library for use in developing products with the MSP430™ MCU. This application report describes design considerations when using the MSP430 Graphics Library, and provides an example of implementation and optimization. Project collateral discussed in this application report can be downloaded from the following URL: www.ti.com/lit/zip/SLAA548. Contents 2 Introduction to the MSP430 Graphics Library............................................................................ 2 3 System Overview ............................................................................................................ 3 4 Hardware Implementation - LCD Bus Type .............................................................................. 4 5 Software Implementation- LCD Display Driver Layer .................................................................. -
6Th Generation Intel® Core™ Processors Based on the Mobile U-Processor for Iot Solutions (Intel® Core™ I7-6600U, I5-6300U, and I3-6100U Processors)
PLATFORM BRIEF 6th Generation Intel® Core™ Mobile Processor Family Internet of Things 6th Generation Intel® Core™ Processors Based on the Mobile U-Processor for IoT Solutions (Intel® Core™ i7-6600U, i5-6300U, and i3-6100U Processors) Harness the Performance, Features, and Edge-to-Cloud Scalability to Build Tomorrow’s IoT Solutions Today Product Overview Stunning Visual Performance Intel is proud to announce its 6th The 6th generation Intel Core generation Intel® Core™ processor processors utilize the new Gen9 family featuring ultra low-power, graphics engine, which improves 64-bit, multicore processors built on graphic performance by up to the latest 14 nm technology. Designed 34 percent.1 The improvements are for small form-factor applications, this demonstrated through faster 3-D multichip package (MCP) integrates graphics performance and rendering a low-power CPU and platform applications at low power. Video controller hub (PCH) onto a common playback is also faster and smoother package substrate. thanks to the new multiplane overlay capability. The new generation offers The 6th generation Intel Core processor up to three independent audio streams family offers dramatically higher CPU and displays, Ultra HD 4K support, and and graphics performance, a broad workload consolidation for lower BOM range of power and features scaling costs and energy output. the entire Intel product line, and new, advanced features that boost edge-to- Users will also enjoy enhanced cloud Internet of Things (IoT) designs high-density streaming applications in a wide variety of markets. These and optimized 4K videoconferencing processors run at 15W thermal design with accelerated 4K hardware media power (TDP) and are ideal for small, codecs HEVC (8-bit), VP8, VP9, and energy-efficient, form-factor designs, VDENC encoding, decoding, and including digital signage, point-of-sale transcoding. -
PART I ITEM 1. BUSINESS Industry We Are
PART I ITEM 1. BUSINESS Industry We are the world’s largest semiconductor chip maker, based on revenue. We develop advanced integrated digital technology products, primarily integrated circuits, for industries such as computing and communications. Integrated circuits are semiconductor chips etched with interconnected electronic switches. We also develop platforms, which we define as integrated suites of digital computing technologies that are designed and configured to work together to provide an optimized user computing solution compared to ingredients that are used separately. Our goal is to be the preeminent provider of semiconductor chips and platforms for the worldwide digital economy. We offer products at various levels of integration, allowing our customers flexibility to create advanced computing and communications systems and products. We were incorporated in California in 1968 and reincorporated in Delaware in 1989. Our Internet address is www.intel.com. On this web site, we publish voluntary reports, which we update annually, outlining our performance with respect to corporate responsibility, including environmental, health, and safety compliance. On our Investor Relations web site, located at www.intc.com, we post the following filings as soon as reasonably practicable after they are electronically filed with, or furnished to, the U.S. Securities and Exchange Commission (SEC): our annual, quarterly, and current reports on Forms 10-K, 10-Q, and 8-K; our proxy statements; and any amendments to those reports or statements. All such filings are available on our Investor Relations web site free of charge. The SEC also maintains a web site (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC. -
NVIDIA Tegra 4 Family CPU Architecture 4-PLUS-1 Quad Core
Whitepaper NVIDIA Tegra 4 Family CPU Architecture 4-PLUS-1 Quad core 1 Table of Contents ...................................................................................................................................................................... 1 Introduction .............................................................................................................................................. 3 NVIDIA Tegra 4 Family of Mobile Processors ............................................................................................ 3 Benchmarking CPU Performance .............................................................................................................. 4 Tegra 4 Family CPUs Architected for High Performance and Power Efficiency ......................................... 6 Wider Issue Execution Units for Higher Throughput ............................................................................ 6 Better Memory Level Parallelism from a Larger Instruction Window for Out-of-Order Execution ...... 7 Fast Load-To-Use Logic allows larger L1 Data Cache ............................................................................. 8 Enhanced branch prediction for higher efficiency .............................................................................. 10 Advanced Prefetcher for higher MLP and lower latency .................................................................... 10 Large Unified L2 Cache ....................................................................................................................... -
Differences Between the TI MSP430 and MC9S08QE128 And
Freescale Semiconductor Document Number: AN3502 Application Note Rev. 0, 09/2007 Differences between the TI MSP430 and MC9S08QE128 and MCF51QE128 Flexis Microcontrollers by: Inga Harris 8-bit Microcontoller Applications Engineer East Kilbride, Scotland 1 Introduction Contents 1 Introduction . 1 From the RS08 to our highest-performance ColdFire® 2 Top Level Specification Comparison . 2 3 Module Comparisons. 3 V4 devices, the Controller Continuum provides 3.1 12-bit Analog to Digital Convertor (ADC). 3 compatibility for an easy migration path up or down the 3.2 Analog Comparators . 4 performance spectrum. The connection point on the 3.3 Real Time Counter / Clock (RTC) . 5 3.4 I/O and Keyboard Interrupts . 6 Controller Continuum is where complimentary families 3.5 Hardware Multiplier . 7 of the S08 and ColdFire V1 (CFV1) microcontrollers 3.6 Low Voltage Detect (LVD). 7 3.7 Timer . 8 share a common set of peripherals and development tools 3.8 Interrupt Request (IRQ). 9 to deliver the ultimate in migration flexibility. 3.9 Watchdog . 9 Pin-for-pin compatibility between many devices allows 3.10 Flash Comparison . 9 3.11 Communications Peripherals. 11 controller exchanges without redesigning the board. The 3.12 Debugger. 13 MC9S08QE128 and the MCF51QE128 are the first 4 Clock Generator Module . 14 4.1 Functional Differences. 17 products in this series known as Flexis. 4.2 Clock Modes . 18 4.3 Clock Gating . 18 The term Flexis means a single development tool to ease 5 CPU Cores . 19 migration between 8-bit (S08) and 32-bit (CFV1), a 5.1 CPU Performance . 19 common peripheral set to preserve software investment 5.2 CPU Modes . -
Architectural Support for Javascript Type-Checking on Mobile Processors
Checked Load: Architectural Support for JavaScript Type-Checking on Mobile Processors Owen Anderson Emily Fortuna Luis Ceze Susan Eggers Computer Science and Engineering, University of Washington http://sampa.cs.washington.edu Abstract applications, including Google Maps, Twitter, and Face- book would not be feasible without both high-throughput Dynamic languages such as Javascript are the de-facto and low-latency JavaScript virtual machines on the client. standard for web applications. However, generating effi- At the same time, innovations in mobile device pro- cient code for dynamically-typed languages is a challenge, grammability have opened up embedded targets to the same because it requires frequent dynamic type checks. Our anal- class of programmers. Today’s smart mobile devices are ysis has shown that some programs spend upwards of 20% expected to provide a developer API that is usable by of dynamic instructions doing type checks, and 12.9% on normal application developers, as opposed to the special- average. ized embedded developers of the past. One such plat- In this paper we propose Checked Load, a low- form, HP/Palm’s WebOS [17], uses JavaScript as its pri- complexity architectural extension that replaces software- mary application development language. Others encourage based, dynamic type checking. Checked Load is comprised JavaScript-heavy web applications in addition to their na- of four new ISA instructions that provide flexible and au- tive development environments, as a means of providing tomatic type checks for memory operations, and whose im- feature-rich, portable applications with minimal develop- plementation requires minimal hardware changes. We also ment costs. propose hardware support for dynamic type prediction to Because of their power and space constraints, embedded reduce the cost of failed type checks. -
Intel® Core™2 Duo Mobile Processor for Intel® Centrino® Duo Mobile Processor Technology
Intel® Core™2 Duo Mobile Processor for Intel® Centrino® Duo Mobile Processor Technology Datasheet September 2007 Document Number: 314078-004 INFORMATIONLegal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.