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Systemc Implementation of a Risc-Based Microcontroller Architecture SYSTEMC IMPLEMENTATION OF A RISC-BASED MICROCONTROLLER ARCHITECTURE A THESIS SUBMITTED TO THE GRADUATE SCHOOL OF NATURAL AND APPLIED SCIENCES OF MIDDLE EAST TECHNICAL UNIVERSITY BY SAL İH ZENG İN IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN ELECTRICAL AND ELECTRONICS ENGINEERING DECEMBER 2006 i Approval of the Graduate School of Natural and Applied Sciences Prof. Dr. Canan Özgen Director I certify that this thesis satisfies all the requirements as a thesis for the degree of Master of Science. Prof. Dr. İsmet Erkmen Head of Department This is to certify that we have read this thesis and that in our opinion it is fully adequate, in scope and quality, as a thesis for the degree of Master of Science. Prof. Dr. Murat A şkar Supervisor Examining Committee Members Prof. Dr. Hasan Güran (METU, EE) Prof. Dr. Murat A şkar (METU, EE) Prof. Dr. Tayfun Akın (METU, EE) Assist. Prof. Dr Cüneyt Bazlamaçcı (METU, EE) M.Sc. Lokman Kesen (ASELSAN) ii I hereby declare that all information in this document has been obtained and presented in accordance with academic rules and ethical conduct. I also declare that, as required by these rules and conduct, I have fully cited and referenced all material and results that are not original to this work. Name, Last name: Salih ZENG İN Signature : iii ABSTRACT SYSTEMC IMPLEMENTATION OF A RISC-BASED MICROCONTROLLER ARCHITECTURE ZENG İN, Salih M.S., Department of Electrical and Electronics Engineering Supervisor: Prof. Dr. Murat A şkar December 2006, 174 Pages Increasing the complexity of modern electronic systems leads to Electronic System Level (ESL) modeling concept, which supports hardware and software co- design and co-verification environment in a single framework. SystemC language, which is an IEEE approved electronic design standard for system design and verification processes, provides such an environment by supporting a wide range of abstraction levels from system-level to register-transfer level (RTL). In this thesis, two different models of a processor core, whose instruction set architecture (ISA) is compatible with 16-bit TI MSP430 microcontroller, are designed by employing the classical hardware modeling capability of the SystemC language. With its well-designed orthogonal instruction set, elegant addressing modes, useful constant generators and flexible von-Neumann architecture, 16-bit RISC-like processor of the MSP430 microcontroller is an ideal selection for the system-on-a-chip (SoC) designs. Instruction set and addressing modes of the designed processors are simulated thoroughly. In addition, original 16-bit and 32- bit cyclic redundancy code (CRC) programs are used in order to verify the processor cores. In this study, SystemC to hardware flow is also illustrated by synthesizing the Arithmetic and Logic Unit (ALU) part of the processor into a Xilinx-based hardware. Keywords: SystemC, SystemC Synthesis, MSP430, Computer Design iv ÖZ RISC TABANLI M İCRODENETLEY İCİ YAPISININ SYSTEMC İLE GERÇEKLENMES İ ZENG İN, Salih Yüksek Lisans., Elektrik ve Elektronik Mühendisli ği Bölümü Tez Yöneticisi : Prof. Dr. Murat A şkar Aralık 2006, 174 Sayfa Elektronik sistemlerin gittikçe karma şıkla şması, tek bir ortamda yazılım ve donanım birimlerinin birlikte tasarlanmasını ve do ğrulanmasını destekleyen, sistem düzeyinde modelleme kavramını ortaya çıkarmı ştır. SystemC, böyle bir ortamı sa ğlayan, sistem seviyesinden yazmaç transfer seviyesine kadar (RTL) geni ş bir soyutlama aralı ğını destekleyen, IEEE onaylı, sistem tasarımı ve do ğrulanması için geli ştirilmi ş elektronik tasarım standardıdır . Bu tezde, SystemC dilinin klasik donanım modelleme yetene ği kullanılarak, 16-bit’lik TI MSP430 mikrodenetleyicisinin komutlarına uyumlu, iki adet farklı i şlemci modelleri tasarlanmı ştır. İyi tasarlanmı ş ortagonal komutlarıyla, kullanı şlı adresleme şekilleriyle, yararlı sabit sayı üreteçleriyle ve esnek von-Neumann mimarisi ile, 16- bit’lik RISC-benzeri MSP430 mikrodenetleyicileri, SoC tasarımları için ideal bir seçimdir. Tasarlanan i şlemcilerin komut kümesi ve adresleme şekilleri tamamiyle denenmi ştir. Bunun yanı sıra, orjinal 16-bit ve 32-bit’lik CRC programları da işlemcilerin çalı şmalarını do ğrulamak için kullanılmı ştır. Ayrıca, SystemC’den donanıma geçi ş, bahsedilen i şlemcilerin arithmetik ve mantık birimi (ALU), Xilinx tabanlı donanıma dönü ştürülerek bu çalı şmada gösterilmi ştir. Anahtar Kelimeler: SystemC, SystemC Sentezlenmesi, MSP 430, Bilgisayar Tasarımı v To my family, To my wife vi ACKNOWLEGMENTS I am most thankful to my supervisor Prof. Dr. Murat A şkar for sharing his invaluable ideas and experiences on the subject of my thesis. I would like to extend my thanks to all lecturers at the Department of Electrical and Electronics Engineering, who greatly helped me to store the basic knowledge onto which I have built my thesis. I am very grateful to TÜB İTAK-SAGE for providing tools and other facilities throughout the production of my thesis. I would like to forward my appreciation to all my friends and colleagues who contributed to my thesis with their continuous encouragement. I would like to express my deep gratitude to my family, who has always provided me with constant support and help. Special thanks to my wife for all her help and showing great patience during the writing process of my thesis. vii TABLE OF CONTENTS ABSTRACT........................................................................................................ IV ÖZ ....................................................................................................................... V ACKNOWLEGMENTS....................................................................................... VII TABLE OF CONTENTS ................................................................................... VIII LIST OF TABLES............................................................................................. XIII LIST OF FIGURES ..........................................................................................XVII LIST OF SYMBOLS .........................................................................................XXI LIST OF ABBREVIATIONS.............................................................................XXII CHAPTERS 1 INTRODUCTION ...........................................................................................1 2 SYSTEMC AND MSP430 MICROCONTROLLER.........................................6 2.1 SystemC ................................................................................................6 2.1.1 Traditional System Design Flow.......................................................8 2.1.2 System Design with SystemC........................................................12 2.1.2.1 Advantages of SystemC Design Flow.....................................14 2.2 MSP430 Microcontroller .....................................................................15 2.2.1 Central Processing Unit Registers .................................................18 2.2.1.1 Registers That Have Pre-defined Functions............................19 2.2.1.1.1 Program Counter-PC/R0 .....................................................19 2.2.1.1.2 Stack Pointer-SP/R1 ...........................................................20 2.2.1.1.3 Status Register (Constant Generator1)-SR/CG1/R2............21 2.2.1.1.4 Constant Generator2-CG2/R3.............................................23 viii 2.2.1.2 General Purpose Registers (from R4 to R15) .........................23 2.2.2 Instruction Set Architecture............................................................23 2.2.2.1 Core Instructions.....................................................................24 2.2.2.1.1 Double Operand Instructions...............................................25 2.2.2.1.2 Single Operand Instructions ................................................27 2.2.2.1.3 Jump Instructions ................................................................28 2.2.2.2 Emulated Instructions .............................................................30 2.2.3 Addressing Modes .........................................................................30 2.2.3.1 Decoding Addressing Modes ..................................................33 2.2.3.2 Register Direct Addressing Mode ...........................................34 2.2.3.3 Indexed Addressing Mode ......................................................36 2.2.3.4 Symbolic Addressing Mode ....................................................38 2.2.3.5 Absolute Addressing Mode .....................................................39 2.2.3.6 Indirect Register Addressing Mode .........................................41 2.2.3.7 Indirect Register Auto-increment Addressing Mode ................42 2.2.3.8 Immediate Addressing Mode ..................................................43 3 DESIGN OF MSP430 CPU CORE MODELS WITH SYSTEMC...................45 3.1 Introduction.........................................................................................45 3.2 Processor Cores.................................................................................46 3.3 Datapath Architecture ........................................................................54 3.3.1 Register Block ...............................................................................56 3.3.1.1 Registers of the Central Processing Unit ................................58 3.3.1.1.1 Address Register (Ra).........................................................59 3.3.1.1.2 Data Register (Rd) ..............................................................60
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