Tools Help You Lose the HARDWARE EDA SOFTWARE SEEMS to BE the ONLY SILICON Blues ASSISTANCE THAT SOME

coverstory By Brian Dipert, Technical Editor

Tools help you lose the HARDWARE EDA SOFTWARE SEEMS TO BE THE ONLY SILICON blues ASSISTANCE THAT SOME

PROGRAMMABLE-LOGIC

COMPANIES WANT TO

TALK ABOUT NOWADAYS.

WHAT OTHER TOOLS ARE

AVAILABLE TO SIMPLIFY

YOUR TASK OF—AS THESE

SUPPLIERS SEEM TO HAVE

FORGOTTEN—DESIGNING

HARDWARE?

At a glance ...... 37 A tools-table teaser ...... 38 For more information ...... 42

Photo courtesy Altera

36 edn | April 18, 2002 www.ednmag.com n the early days of semiconductors, digital-system design was almost completely Ia hardware-intensive-tools task. User-customizable-logic chips (with the exception of software-configurable microprocessors) just didn’t exist. Instead, you dealt with

collections of transistors, subsequently followed by dis- er, covers only conditions that you explicitly describe crete-logic gates, and then by single-chip assemblages in your test-vector file.What about those “real-world” of multiple gates. You interconnected them on the sys- combinations of input signals and sequences of those tem board to construct a desired function, maybe with signals that you haven’t predicted? Clearly, relying only the assistance of a DeMorgan Law logic-transformation on simulation is insufficient; old-school debugging program, but more likely with nothing more glamorous techniques still have value. Throughout the four main than a No. 2 pencil and paper.And when, invariably, the stages of product development—definition, design, circuit’s function didn’t match what you expected, you prototyping, and production—plenty of other op- powered up your trusty oscilloscope and logic analyz- portunities for hardware help exist, too. er to track down what went wrong. The hardware-to-software tools shift began with PAL THE EVOLUTION OF EVALUATION (programmable-array-logic) devices. Now, you could Before you can begin designing with a chip, you interconnect AND and OR gates, inverters, and flip- have to pick a chip. In appraising various vendors and flops via on-chip (rather than on- the options within each vendor’s board) routing resources. First product portfolio, it’s often ben- ATAGLANCE low-level ABEL (advanced Bool- eficial not only to compare data- ean equation language), then ୴ Testdrive chip and software options sheet specifications, but also to higher abstraction-level design during system definition before you see how well the device and its compilation and fitting software, proceed to design. corresponding development- created the bit streams that con- tool set tackle the types of cir- figured the devices’ routing fuses, ୴ Application-tuned device features have cuits you commonly use in your antifuses, and pass transistors. transformed evaluation kits into more designs (references 1 and 2). Next came design-simulation soft- focused but fuller featured reference This hands-on assessment is the ware, which let you test your cir- designs. primary function of evaluation cuits’functions before committing boards, as their name suggests them to silicon, a capability of par- ୴ STAPL and IEEE 1532 further expand (Figure 1a). ticular economic advantage if the vendor-agnostic JTAG. Stand-alone pro- Take a look at any of the chip device wasn’t reprogrammable, grammers offer a higher performance alter- vendor’s Web sites, which list and a misconfiguration, therefore, native, particularly for production. both the vendors’and their part- meant an expensive addition to ners’ evaluation boards, or at an the trash bin. And as the chips’ ୴ As board traces have transformed into independent resource, such as routing architectures grew more internal routing lines in the system-on-chip the Programmable Logic Jump hierarchical—culminating in the integration era, embedded-logic analyzers Station, and you’ll discover long fine-grained and segmented FP- still let you probe around. lists of products. They all contain GA—dual-pass simulation, which some means of downloading combines a speedy first-pass functional test after design data to the PLD or the FPGA. They usually also offer compilation with a more in-depth timing-inclusive some method of obtaining visible feedback that the simulation after design place and route or fitting, chip is operating properly, such as blinking LEDs or a gained prominence. single- or multiple-segment LCD. Aside from the fact Nowadays, multimillion-gate FPGAs and 1000- that the boards contain different device architectures macrocell CPLDs, the epitome of VLSI, integrate so and different device sizes within an architecture, what much and such diverse analog and digital circuitry and other feature disparities justify this multiplicity and, memory that they might, at first glance, seem to make often, seeming duplicity? hardware tools obsolete. Simulation software, howev- If the device you’re evaluating supports separate

www.ednmag.com April 18, 2002 | edn 37 coverstory Programmable-logic hardware tools voltages for the core and I/O buffers, and if your design will take advantage of this feature, make sure that the board Figure 1 supports corresponding voltage flexibility. Some chips, in fact, offer multiple I/O banks, each capable of running at a different voltage range. Multiple clock inputs or onboard crystal oscilla- tors provide additional evaluation- board-usage options. Test points enable you to monitor device inputs and outputs with an oscilloscope or a logic analyzer and are particularly valuable with (b) hard-to-probe narrow- and numerous- lead packages, such as QFPs. Test points are essential when you use BGAs, because the package lids completely obscure their board-connection matrices (often to internal-layer board traces), making them otherwise unable to be probed. (a) Some evaluation boards contain a breadboard area to which you can attach other devices you plan to include in your end design. Socket adapters from companies such as Emulation Technology modify surface-mount packages to comprehend the through-hole requirements of this breadboard area. In addition to, or perhaps instead of, a supplemental pro- (d) totyping area, some boards come with Evaluation boards let you test- other preinstalled chips: banks of drive product features before you DRAM, SRAM, and flash memory; mi- buy and are applicable to both chips crocontrollers; UARTs; keyboard and (a, courtesy Lattice Semiconductor) mouse controllers; ADCs and DACs; and and embedded programmable logic others. Other boards handle expansion (b, courtesy Actel). Some boards are via daughtercards in PC-104, PMC, and tailored to specific product features other standard formats. and capabilities, such as “hard” (c, Beyond the hardware differences courtesy Atmel) and “soft” (d, cour- among various boards, you find varying tesy Altera) CPU cores. amounts of supplied documentation in- (c) cluding, in some cases, schematics and Gerber-layout files.You also come across the device range, whereas another’s JTAG-configuration options, cables, doc- different mixes of bundled software. might support an entire product family, umentation, and a user guide. Integrated Whereas a chip manufacturer’s board multiple product families, or even prod- Circuit Technology plans to offer simi- might reflect a partnership with Synop- ucts from multiple chip suppliers. Dis- lar boards for its long-delayed embed- sys, for example, a third-party board tributors are now even offering evalua- ded-PLD technology, but embedded- might include a Mentor Graphics or Syn- tion boards and corresponding technical FPGA supplier Adaptive Silicon currently plicity tool set. One board’s tools might support in the hope that when your de- has no evaluation aspirations. support only a single device or subset of sign goes into production, they’ll get your business. REFLECTING ON REFERENCES Evaluation boards aren’t restricted Programmable logic’s generic nature A TOOLS-TABLE TEASER solely to programmable-logic chips. Ac- has historically enabled it to serve a tel provides a developer kit that lets you plethora of applications. In recent times, Not all specs and prices for vendors’ eval- try out the company’s Varicore embed- though, the suppliers have integrated ad- uation boards, reference designs, pro- ded FPGA cores (Reference 3, Figure ditional features, such as embedded grammers, and logic analyzers arrived by 1b). The evaluation board includes a memory, DLLs, PLLs, high-speed I/O press time. Check out the version of this 4ϫ4-logic-block Varicore test chip with buffers, and arithmetic-function blocks, article at www.ednmag.com for tables supporting logic, an LCD, both a bread- all with specific high-volume applica- containing this information. board area and a daughtercard connections in mind. And, correspondingly, the tion, nonvolatile memory, serial- and devices’ evaluation boards have become

38 edn | April 18, 2002 www.ednmag.com coverstory Programmable-logic hardware tools more optimized for applications and functions, transforming themselves into 1394 DV DATA reference platforms applicable to both 1394 (iLINK) 1394 PHY LINK device evaluation and subsequent system LAYER design. One of the first examples of this Figure 2 27-MHz ANALOG IN 8051 trend began when, in response to chips VIDEO VCXO DIVIO S VIDEO/ DRAM MICRO- DECODER NW701 such as Xilinx’s now-discontinued COMPOSITE CONTROLLER XC6200 series, a number of third-party vendors unveiled reconfigurable-logic boards. These development platforms are CCIR 656/601 ANALOG OUT VIDEO VIDEO notable for their large amounts of on- S VIDEO/ ENCODER COMPOSITE SPARTAN-II board configuration memory (either FPGA nonvolatile or volatile), along with high- speed interfaces to external hardware. In- ANALOG stead of a serial JTAG cable, for example, IN/OUT AUDIO I2S AUDIO they might support a parallel wiring har- LEFT PLUS CODEC RIGHT ness or even take the form of an ISA or a PCI add-in card. All of these features- VOLUME CONTROL boost partial- and full-reconfiguration performance.An Ethernet controller, in- A video-codec reference-design kit that Xilinx developed in partnership with Divio represents just tended for remote configuration pur- one of the numerous applications that has captured the attention of the eSP program. poses, may even be onboard. These boards also typically include reconfig- they don’t have minimum-order quan- gained prominence when devices got urable-computing-tailored design-and- tities. In recent years, programmable-log- large and fast enough to house PCI ini- debugging software, such as C compilers ic companies have taken a more active tiator and target cores and has gained and other software-to-hardware migra- approach to ensuring their presence in momentum as those and other cores tion utilities. others’ reference designs in applications have migrated onto dedicated ASIC sili- Xilinx has been aggressive in tailoring that represent large amounts of business con. QuickLogic, one of the first compa- its collateral and tools for specific appli- potential. The advantage to those of you nies to move into the programmable-log- cations. The company devotes an entire who work in one of these application ar- ic/ASIC “hybrid” space, with its ESP area of its Web site to what it calls “eSPs” eas, regardless of what company provides (Embedded Standard Product) line, lists (emerging standards and protocols), the reference design, is that you can di- on its Web site more than 10 reference- areas in which the company sees com- rectly apply the supplied schematics, de- design kits that allow you to exercise the pelling high-growth opportunities for its sign files, and software source code to features of its QuickDSP, QuickFC, chips. At the eSP portal (www.xilinx. your projects. QuickMIPS, QuickPCI, and QuickSD com/esp), you’ll find information on Reference designs might focus on a products. wired interfaces, such as HomePNA, certain device feature that you can apply Other hybrid chip suppliers, such as IEEE 1394, and USB 2.0; wireless inter- to a variety of applications rather than on Altera (Mercury and ARM-based Excal- faces, such as Bluetooth and IEEE 802.11; a specific application. This trend first ibur), Atmel (FPSLIC), Cypress (Pro- and other applications, such as grammable Serial Interface), Lat- encryption and decryption, and tice (via its acquisition of Agere digital video encoding and de- Systems’ FPGA line), NEC (SoC coding. You’ll also find a Lite), Triscend (E5 and A7), and number of reference de- Figure 3 Xilinx (Virtex-II Pro), have sim- signs, the fruits of Xilinx’s part- ilar ambitions, if not equally nu- nerships with companies such as merous board options (Figure 4Links (IEEE 1355), Broadcom 1c). Feature-optimized tool kits (Bluetooth), Convergent Design aren’t restricted to “hard” CPU and Digital Harmony (IEEE cores; both Altera (Nios) and Xil- 1394), Divio (video), and inx (MicroBlaze) directly and in Kawasaki LSI and Mentor partnership with distributors Graphics (USB 2.0) (Figure 2). supply CPU soft-core reference PLDs and FPGAs have always designs (Figure 1d). And, as de- been a natural fit in other man- vices grow, nontraditional con- ufacturers’ evaluation boards, figuration devices, such as Com- which tend to have production pactFlash cards, become more runs of only dozens or hundreds Evaluation boards also let you try out new configuration-down- appealing. Evaluation boards let of units, because, unlike ASICs, load and -storage options (courtesy Xilinx). you try out these emerging alter-

40 edn | April 18, 2002 www.ednmag.com coverstory Programmable-logic hardware tools natives, and, with the appropriate software stack, you might even be able to plug network cards into the Compact- Flash-module connector (Figure 3). GET WITH THE PROGRAM Now that you’ve got a design complete and ready to fire up, how do you get it into the programmable-logic device or, for SRAM-based parts, its companion configuration memory? IEEE 1149.1, commonly known as JTAG, is one of to- day’s most popular device-programming techniques (figures 4a and 4b). After years of fractious debate between Altera and Cypress’ Jam, Lattice’s ispVM, and other vendors’ proposals, the next-generation STAPL (Standard Test and Programming Language) in-system Figure 4 algorithm has secured broad-based industry support. JEDEC-approved STAPL (a) defines a file format containing each chip’s programming information. The companion IEEE-defined 1532 specifi- cation, a superset of 1149.1, is a hardware standard defining the programming-algorithm details (http://grouper.ieee.org/ groups/1532). JTAG’s test-access port is, in many respects, an ideal programming interface— especially if the device internally gener- ates all the “extra” voltages necessary to alter stored contents—because it’s dedi- (b) (c) cated to programming and testing and JTAG is an attractive programming option for both CPLDs (a, courtesy Lattice Semiconductor) and doesn’t interfere with other device and FPGAs (b, courtesy Actel); stand-alone programmers offer a higher performance alternative (c, cour- board functions. However, its serial and tesy Lattice Semiconductor).

FOR MORE INFORMATION... For more information on products such as those discussed in this article, go to www.ednmag.com/info and enter the reader service number. When you contact any of the following manufacturers directly, please let them know you read about their products in EDN. Actel Integrated Circuit Triscend BP Microsystems First Silicon Solutions 1-408-739-1010 Technology 1-650-968-8668 www.bpmicro.com www.fs2.com www.actel.com 1-408-434-0678 www.triscend.com Broadcom 4Links Enter No. 318 www.ictpld.com Enter No. 326 www.broadcom.com www.4links.co.uk Enter No. 322 Convergent Design Kawasaki LSI Altera Xilinx www.convergent-design.com www.klsi.com 1-408-544-7000 Lattice Semiconductor 1-408-991-2000 Digital Harmony Mentor Graphics www.altera.com 1-503-268-8000 www.xilinx.com www.digitalharmony.com www.mentorg.com Enter No. 319 www.latticesemi.com Enter No. 327 Divio Programmable Logic Enter No. 323 www.divio.com Jump Station Atmel OTHER COMPANIES MEN- Electronic Trend www.optimagic.com 1-408-441-0311 NEC TIONED IN THIS ARTICLE Publications Synopsys www.atmel.com 1-408-588-6000 Adaptive Silicon www.electronictrendpubs.com www.synopsys.com Enter No. 320 www.necel.com www.adaptivesilicon.com Emulation Technology Synplicity Enter No. 324 Agere Systems www.emulation.com www.synplicity.com Cypress Semiconductor www.agere.com 1-408-943-2600 Quicklogic Advanced RISC Machines SUPER INFO NUMBER www.cypress.com 1-408-990-4000 (ARM) For more information on the products available from all of the Enter No. 321 www.quicklogic.com www.arm.com vendors listed in this box, enter no. 328 at www.ednmag. Enter No. 325 com/info.

42 edn | April 18, 2002 www.ednmag.com coverstory Programmable-logic hardware tools low-speed attributes contribute to its low programming performance. These char- acteristics may not be a problem in the development lab and during pro- Figure 5 totyping, but they can be an expensive bottleneck in high-volume production (Reference 4). Instead, you might want to harness a wide and fast onboard programming interface (for which you’ll have to comprehend function mul- tiplexing in your system hardware and software designs). Alternatively, you can program the chips before installing them on the system board (Figure 4c). Chip suppliers often partner with programmer manufacturers to offer a version of the manufacturer’s product un- der the supplier’s name. For example, Actel’s single-site Silicon Sculptor and multisite Silicon Sculptor 6X antifuse (a) FPGA programmers are variants of BP Microsystems’ programmers, bundled I/O PADS with Actel chip-specific software. Actel’s Flash Pro for the company’s ProASIC ILA ILA and ProASIC Plus flash-based FPGAs is IP IBA CUSTOM the fruit of Actel’s partnership with First CORE LOGIC Silicon Solutions and supports STAPL EMBEDDED SYSTEM BUS and IEEE 1149.1. Before deciding on a CUSTOM PPC405 ILA I/O PADS silicon-vendor-sourced programmer, in- CORE CORE I/O PADS vestigate whether you can later upgrade NOTES: its firmware to support other vendors’ MEMORY ILA:INTEGRATED LOGIC ANALYZER. ARRAY ILA IBA: INTEGRATED BUS ANALYZER. products. Otherwise, if you switch chip ICON: INTEGRATED CONTROLLER. suppliers in the future, you might be left with an expensive paperweight. Spend- ICON ing more money up-front for the origi- BOUNDARY SCAN TAP CONTROLLER nal manufacturer’s more versatile version of the programmer might be cost-effec- TARGET CONNECTION tive in the long run. LOGICAL ANALYSIS You’ve programmed your chip, you (b) turn on the system power, and...nothing Some embedded-logic analyzers employ devices’ built-in logic circuits and routing resources (a, happens. Or something happens, but it’s courtesy Actel); others take the form of a “soft” core (b, courtesy Xilinx). not even close to what you expected.Your design has already passed the simulation you don’t know in advance what errors Probe documentation admits, “Signals tests with flying colors. What do you do your design has and, therefore, what might not always find successful re- now? Test points on the board, along with nodes you want to bring out to pins. route.” careful connection of test clips to the Your lack of foreknowledge means Keep in mind, too, that the added im- chip’s package leads, might let you ana- that, to monitor internal nodes, you need pedance of the logic analyzer or oscillo- lyze its inputs and outputs. But what to tap into incremental internal-routing scope test probe alters the electrical char- about signals running around inside the resources. In other words, you need to re- acteristics of the internal node and, chip? compile your design—a process that may therefore, the circuitry that influences it For a long time, your only option was change the design’s timing and, in- and that it influences. Despite these po- to route internal nodes that you wanted evitably, its function (obscuring the very tential pitfalls, routing nodes to pins to inspect out to device pins. Silicon ven- phenomena you’re trying to observe).Al- might still allow you to gain valuable in- dors love this alternative, because, as the tera claims that the LogicLock and Sig- sight into what’s wrong with the design number of nodes increases, so do the re- nalProbe features of its latest Quartus II and how to fix it. But now what do you quired device pin count and price. It’s not design software preserve your design and do: Leave the added nodes-to-pins por- ideal to you for other reasons, too. Unless enable fast incremental compilation to tions of the design alone and use a more you employ the services of a fortuneteller, bring nodes out to pins. But the Signal- expensive chip with a higher pin count

44 edn | April 18, 2002 www.ednmag.com than you need, or remove the test circuitry and risk breaking the design TABLE 1—SIGNALTAP PRIMARY- TABLE 2—APEX 20K LOGIC- again? MODE LOGIC-ELEMENT USAGE ELEMENT RESOURCES There has to be a better way. And Ac- Apex 20K Device Total logic elements Channels logic elements used* tel, followed by Altera and Xilinx, believes EP20K100 4160 One 136 it has found it in the form of the embed- EP20K100E 4160 Two 144 EP20K160E 6400 ded logic analyzer (Figure 5a).Actel’s an- Four 160 EP20K200 8320 tifuse-chip implementations differ Eight 192 EP20K200E 8320 slightly from Altera and Xilinx’s SRAM- 16 256 EP20K300E 11,520 based FPGAs, but the basic concept is the 32 384 EP20K400 16,640 same: You tell the tool what nodes to 64 640 EP20K400E 16,640 monitor, for how many cycles, and with 128 1152 EP20K600E 24,320 what trigger conditions. It communicates *Preliminary estimates EP20K1000E 42,240 this information over the JTAG interface to circuitry within the chip, which sends peers in that it can observe internal nodes grammable antifuse technology. Once the node data back out over JTAG or a in real time by tapping into hard-wired you discover the problem, you have to dedicated trace port to a PC or logic an- connections used for programming the discard the chip containing the faulty de- alyzer for display. FPGA antifuses. It outputs as many as sign and program a circuit that you hope two nodes’ states over dedicated pins is fixed into a fresh FPGA.And, unlike the CH-CH-CH-CH-CHANGES PRA and PRB and can monitor as many more flexible soft-core approach, you can Actel’s Silicon Explorer 2 differs from as 16 additional nodes via the FPGA’s monitor only 18 signals at a time. Noth- the first-generation Silicon Explorer in general-purpose I/O pins. Its Silicon Ex- ing’s free, it seems.˿ several areas. (Ironically, Silicon Explor- plorer 2 Lite variant enables only the er was designed by a company that Altera Command module and relies on an ex- References subsequently acquired to develop Signal- ternal scope or logic analyzer for viewing 1. Dipert, Brian, “Lies, damn lies, and Tap and the Nios CPU core.) It supports signals. benchmarks: The race for the truth is an external power supply, enabling it to Silicon Explorer 2 employs dedicated on,” EDN, May 27, 1999, pg 54. probe devices with multiple operating ActionProbe circuitry within the FPGA 2. Dipert, Brian, “Synthesis shoot-out voltages; delivers acquisition capability to to implement the logic-analysis function. at the EDN corral,” EDN, Sept 11, 1998, 100 MHz; and offers four levels of trig- In contrast, Altera’s SignalTap and Xil- pg 95. gering and decompression on download. inx’s ChipScope are soft cores, meaning 3. Dipert, Brian, “Do combo chips Silicon Explorer 2 is unique among its that you have to compile them into the compute (or even compile)?” EDN,Feb design (Figure 5b). There- 15, 2001, pg 101. fore, although they con- 4. Dipert, Brian, “Focusing on chip TABLE 3—SIGNALTAP PRIMARY-MODE sume no incremental de- programming,” EDN, Jan 7, 1999, pg 58. EMBEDDED-SYSTEM-BLOCK USAGE vice-I/O buffers like the Memory depth: samples bring-the-node-to-a-pin Acknowledgments Channels 128 256 512 1024 2048 technique or Actel’s ap- Programmable Logic News and Views, One One Two One Two proach with more than two edited by Murray Disman and published by Four One Two Four monitored nodes, they still Electronic Trend Publications, is a concise Eight One Two Four Eight consume incremental in- yet comprehensive monthly newsletter 16 One Two Four Eight 16 ternal logic, memory, and summarizing all that’s new in the pro- 32 Two Four Eight 16 32 routing resources (tables 1 grammable-logic industry. Check out www. 64 Four Eight 16 32 64 through 4). electronictrendpubs.com/plnvbro.htm for 128 Eight 16 32 64 128 Once you debug your sample content. Embedded-system blocks required design using SignalTap or ChipScope, you probably Author’s biography TABLE 4—APEX 20K EMBEDDED- won’t want to rip out the logic analyzer Technical editor Brian SYSTEM-BLOCK RESOURCES core and recompile the design. So, you Dipert yearns for the still have a bigger chip than you’d other- good old days when Device Embedded-system blocks wise need—but one containing a design programmable-logic EP20K100 26 EP20K100E 26 that now works. Pick your poison, and design meant filling in EP20K160E 40 ponder how big that logic-analyzer core Karnaugh maps and EP20K200 52 will get when you start not just monitor- debugging meant probing low-pin-count EP20K200E 52 ing individual signal nodes, but also trac- DIPs (containing chips that he regularly EP20K300E 72 ing entire buses (in conjunction with an blew up by inserting them in their sockets EP20K400 104 embedded processor, for example). Ac- upside-down). You can reach Brian the EP20K400E 104 tel’s approach seems elegant in contrast, Luddite at 1-916-454-5242, fax 1-916- EP20K600E 152 and, in many respects, it is, but keep in 454-5101, [email protected], and EP20K1000E 264 mind that you’re dealing with nonrepro- www.bdipert.com. www.ednmag.com April 18, 2002 | edn 45