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Tools Help You Lose the HARDWARE EDA SOFTWARE SEEMS to BE the ONLY SILICON Blues ASSISTANCE THAT SOME coverstory By Brian Dipert, Technical Editor Tools help you lose the HARDWARE EDA SOFTWARE SEEMS TO BE THE ONLY SILICON blues ASSISTANCE THAT SOME PROGRAMMABLE-LOGIC COMPANIES WANT TO TALK ABOUT NOWADAYS. WHAT OTHER TOOLS ARE AVAILABLE TO SIMPLIFY YOUR TASK OF—AS THESE SUPPLIERS SEEM TO HAVE FORGOTTEN—DESIGNING HARDWARE? At a glance ..........................37 A tools-table teaser ..........38 For more information ......42 Photo courtesy Altera 36 edn | April 18, 2002 www.ednmag.com n the early days of semiconductors, digital-system design was almost completely Ia hardware-intensive-tools task. User-customizable-logic chips (with the exception of software-configurable microprocessors) just didn’t exist. Instead, you dealt with collections of transistors, subsequently followed by dis- er, covers only conditions that you explicitly describe crete-logic gates, and then by single-chip assemblages in your test-vector file.What about those “real-world” of multiple gates. You interconnected them on the sys- combinations of input signals and sequences of those tem board to construct a desired function, maybe with signals that you haven’t predicted? Clearly, relying only the assistance of a DeMorgan Law logic-transformation on simulation is insufficient; old-school debugging program, but more likely with nothing more glamorous techniques still have value. Throughout the four main than a No. 2 pencil and paper.And when, invariably, the stages of product development—definition, design, circuit’s function didn’t match what you expected, you prototyping, and production—plenty of other op- powered up your trusty oscilloscope and logic analyz- portunities for hardware help exist, too. er to track down what went wrong. The hardware-to-software tools shift began with PAL THE EVOLUTION OF EVALUATION (programmable-array-logic) devices. Now, you could Before you can begin designing with a chip, you interconnect AND and OR gates, inverters, and flip- have to pick a chip. In appraising various vendors and flops via on-chip (rather than on- the options within each vendor’s board) routing resources. First product portfolio, it’s often ben- ATAGLANCE low-level ABEL (advanced Bool- eficial not only to compare data- ean equation language), then ୴ Testdrive chip and software options sheet specifications, but also to higher abstraction-level design during system definition before you see how well the device and its compilation and fitting software, proceed to design. corresponding development- created the bit streams that con- tool set tackle the types of cir- figured the devices’ routing fuses, ୴ Application-tuned device features have cuits you commonly use in your antifuses, and pass transistors. transformed evaluation kits into more designs (references 1 and 2). Next came design-simulation soft- focused but fuller featured reference This hands-on assessment is the ware, which let you test your cir- designs. primary function of evaluation cuits’functions before committing boards, as their name suggests them to silicon, a capability of par- ୴ STAPL and IEEE 1532 further expand (Figure 1a). ticular economic advantage if the vendor-agnostic JTAG. Stand-alone pro- Take a look at any of the chip device wasn’t reprogrammable, grammers offer a higher performance alter- vendor’s Web sites, which list and a misconfiguration, therefore, native, particularly for production. both the vendors’and their part- meant an expensive addition to ners’ evaluation boards, or at an the trash bin. And as the chips’ ୴ As board traces have transformed into independent resource, such as routing architectures grew more internal routing lines in the system-on-chip the Programmable Logic Jump hierarchical—culminating in the integration era, embedded-logic analyzers Station, and you’ll discover long fine-grained and segmented FP- still let you probe around. lists of products. They all contain GA—dual-pass simulation, which some means of downloading combines a speedy first-pass functional test after design data to the PLD or the FPGA. They usually also offer compilation with a more in-depth timing-inclusive some method of obtaining visible feedback that the simulation after design place and route or fitting, chip is operating properly, such as blinking LEDs or a gained prominence. single- or multiple-segment LCD. Aside from the fact Nowadays, multimillion-gate FPGAs and 1000- that the boards contain different device architectures macrocell CPLDs, the epitome of VLSI, integrate so and different device sizes within an architecture, what much and such diverse analog and digital circuitry and other feature disparities justify this multiplicity and, memory that they might, at first glance, seem to make often, seeming duplicity? hardware tools obsolete. Simulation software, howev- If the device you’re evaluating supports separate www.ednmag.com April 18, 2002 | edn 37 coverstory Programmable-logic hardware tools voltages for the core and I/O buffers, and if your design will take advantage of this feature, make sure that the board Figure 1 supports corresponding voltage flexibility. Some chips, in fact, offer mul- tiple I/O banks, each capable of running at a different voltage range. Multiple clock inputs or onboard crystal oscilla- tors provide additional evaluation- board-usage options. Test points enable you to monitor device inputs and out- puts with an oscilloscope or a logic ana- lyzer and are particularly valuable with (b) hard-to-probe narrow- and numerous- lead packages, such as QFPs. Test points are essential when you use BGAs, because the package lids completely obscure their board-connection matrices (often to in- ternal-layer board traces), making them otherwise unable to be probed. (a) Some evaluation boards contain a breadboard area to which you can attach other devices you plan to include in your end design. Socket adapters from com- panies such as Emulation Technology modify surface-mount packages to com- prehend the through-hole requirements of this breadboard area. In addition to, or perhaps instead of, a supplemental pro- (d) totyping area, some boards come with Evaluation boards let you test- other preinstalled chips: banks of drive product features before you DRAM, SRAM, and flash memory; mi- buy and are applicable to both chips crocontrollers; UARTs; keyboard and (a, courtesy Lattice Semiconductor) mouse controllers; ADCs and DACs; and and embedded programmable logic others. Other boards handle expansion (b, courtesy Actel). Some boards are via daughtercards in PC-104, PMC, and tailored to specific product features other standard formats. and capabilities, such as “hard” (c, Beyond the hardware differences courtesy Atmel) and “soft” (d, cour- among various boards, you find varying tesy Altera) CPU cores. amounts of supplied documentation in- (c) cluding, in some cases, schematics and Gerber-layout files.You also come across the device range, whereas another’s JTAG-configuration options, cables, doc- different mixes of bundled software. might support an entire product family, umentation, and a user guide. Integrated Whereas a chip manufacturer’s board multiple product families, or even prod- Circuit Technology plans to offer simi- might reflect a partnership with Synop- ucts from multiple chip suppliers. Dis- lar boards for its long-delayed embed- sys, for example, a third-party board tributors are now even offering evalua- ded-PLD technology, but embedded- might include a Mentor Graphics or Syn- tion boards and corresponding technical FPGA supplier Adaptive Silicon currently plicity tool set. One board’s tools might support in the hope that when your de- has no evaluation aspirations. support only a single device or subset of sign goes into production, they’ll get your business. REFLECTING ON REFERENCES Evaluation boards aren’t restricted Programmable logic’s generic nature A TOOLS-TABLE TEASER solely to programmable-logic chips. Ac- has historically enabled it to serve a tel provides a developer kit that lets you plethora of applications. In recent times, Not all specs and prices for vendors’ eval- try out the company’s Varicore embed- though, the suppliers have integrated ad- uation boards, reference designs, pro- ded FPGA cores (Reference 3, Figure ditional features, such as embedded grammers, and logic analyzers arrived by 1b). The evaluation board includes a memory, DLLs, PLLs, high-speed I/O press time. Check out the version of this 4ϫ4-logic-block Varicore test chip with buffers, and arithmetic-function blocks, article at www.ednmag.com for tables supporting logic, an LCD, both a bread- all with specific high-volume applica- containing this information. board area and a daughtercard connec- tions in mind. And, correspondingly, the tion, nonvolatile memory, serial- and devices’ evaluation boards have become 38 edn | April 18, 2002 www.ednmag.com coverstory Programmable-logic hardware tools more optimized for applications and functions, transforming themselves into 1394 DV DATA reference platforms applicable to both 1394 (iLINK) 1394 PHY LINK device evaluation and subsequent system LAYER design. One of the first examples of this Figure 2 27-MHz ANALOG IN 8051 trend began when, in response to chips VIDEO VCXO DIVIO S VIDEO/ DRAM MICRO- DECODER NW701 such as Xilinx’s now-discontinued COMPOSITE CONTROLLER XC6200 series, a number of third-party vendors unveiled reconfigurable-logic boards. These development platforms are CCIR 656/601 ANALOG OUT VIDEO VIDEO notable for their large amounts of on- S VIDEO/ ENCODER COMPOSITE SPARTAN-II board configuration memory (either FPGA nonvolatile or volatile), along with high- speed interfaces to external hardware. In- ANALOG stead of a serial JTAG cable, for example, IN/OUT AUDIO I2S AUDIO they might support a parallel wiring har- LEFT PLUS CODEC RIGHT ness or even take the form of an ISA or a PCI add-in card. All of these features- VOLUME CONTROL boost partial- and full-reconfiguration performance.An Ethernet controller, in- A video-codec reference-design kit that Xilinx developed in partnership with Divio represents just tended for remote configuration pur- one of the numerous applications that has captured the attention of the eSP program.
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