Wright State University Fabrication EE480/680 Fabrication Micro-Electro-Mechanical Systems (MEMS) Summer 2006
LaVern Starman, Ph.D. Assistant Professor Dept. of Electrical and Computer Engineering Email: [email protected] Help !
Spin-coating photoresist onto a wafer
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 1 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 2
MEMS Fabrication MEMS Fabrication
Micromachining consists of • Micromachining combines Lithography, Thin Film four separate areas: Processing, and Sacrificial Etching to form • Substrates and Dopants – Starting point mechanical devices • Patterning - Lithography • Three Types of Fabrication Processes • Additive Processes - Deposition • Subtractive Process - Etching • Surface Micromachining Combining Lithography with • Bulk Micromachining • Substrates and Dopants • Additive Processes • Microforming • Subtractive Process Results in Micromachining!!
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 3 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 4
1 MEMS Fabrication Overview Microforming
Surface Bulk • Materials micromachining Micromachining • Microelectronics Fabrication • Bulk Micromachining • Surface Micromachining • Micromolding • Packaging
Substrate
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 5 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 6
Why Silicon Processing? Materials
• Traditionally, MEMS have been fabricated using the same materials used in silicon (Si) based microelectronics - this is what we will concentrate on. 1) Abundant and Inexpensive • Crystalline Si • Polycrystalline Si (polysilicon) 2) Billions invested in developing pure • Oxides of Si wafers and Silicon processing • Polycrystalline or Amorphous Dielectric Layers • Metal Films 3) Native Oxide with good electrical properties
Addison Engineering
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 7 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 8
2 Materials Materials
• Si crystal structure • Miller Indices • Diamond, or equivalently, two interpenetrating FCC lattices by a/4 along • Specific plane (hkl), set of equivalent planes {hkl} <111> • Specific direction [hkl] parallel to normal of plane (hkl), set of equivalent directions
a (111) = 1/1, 1/1, 1/1
(100) = 1/1, 1/∞,1/∞
y (b)
a a x (a) “a” is the lattice constant, for Si, a = 5.43 Å at 300 K EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 9 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 10
Materials: Properties Materials: Properties
Kovacs, Micromachined Transducers Sourcebook, 1998 Gardner, Microsensors, 1994.
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 11 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 12
3 Materials: Properties Primary Micromachining Substrates
Elemental Semiconductors (Group IV) • Silicon •Germanium Compound Semiconductors (III-V) • Gallium Arsenide • Indium Phosphide Non-Semiconductor Substrates • Quartz Gardner, Microsensors, 1994. Gardner, Microsensors, MEMS and Smart Devices, 2001. • Sapphire
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 13 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 14
Overview Microelectronics Fabrication
Impurity Anneal Doping Design • Materials Wafer Surface Film Photolithography • Microelectronics Fabrication Preparation Formation • Bulk Micromachining • Surface Micromachining Etching 1. . . • Micromolding 13 Mask Set • Packaging Subdice Inspection/Test
Packaging Final Test
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4 MEMS Fabrication Microelectronics Fabrication
Impurity Anneal Doping Chemical/mechanical Design • Wafer Fabrication polishing of wafers Wafer • Czochralski (CZ) (CMP) Surface Film Photolithography • Float Zone (FZ) Preparation Formation
Bonding and/or 1. . . Etching 13 Mask Set Wafer standard Subdice Inspection/Test markings. Primary Etching flats are shown down. Etching (CZ) Final Test Packaging, Integration, and/or Assembly Gardner, Microsensors, MEMS and Smart Devices, 2001. EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 17 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 18
MEMS Fabrication MEMS Fabrication
• Primarily Integrated Circuit type fabrication • Direct Mechanical-Electrical Integration • One fab process for both IC and MEMS • Allows Batch Fabrication • Direct Sensor, Processor, Actuator Integration
Interface Circuitry
MEMS Sense Devices Circuitry
picture of ADXL202 from www.analog.com EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 19 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 20
5 MEMS Fabrication Microelectronics Fabrication
• Film Formation (thin < 5µm, thick < 50 µm) • Thermal Oxidation (wet/dry)
• The enhancement of the transformation of Si into SiO2, consumption ratio 0.44 Si/SiO2 • Amorphous thin films, conformal coating • 1000 - 1200 °C, atmospheric pressure, hours deposition times • Passivation, sacrificial layers, hard etch/diffusion mask, insulation • Chemical Vapor Deposition (CVD) • LPCVD, MOCVD, PCVD • The nucleation of a gaseous species on a substrate to form a film • Polycrystalline or Amorphous thin films, conformal coating Micromachining is not 3D • ≈ 600 °C, low - atmospheric pressure, on order of 1 µm/hour deposition rates • Structural layers, passivation, sacrificial layers, hard etch/diffusion mask, insulation,
While a large variety of some metals, SiO2, Si3N4, polySi, phosphosilicate glass (PSG) structures are possible, arbitrary 3D structures are difficult to fabricate EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 21 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 22
Microelectronics Fabrication Microelectronics Fabrication
• Film Formation (thin < 5µm, thick < 50 µm) • Film Formation (thin < 5µm, thick < 50 µm) • Evaporation • Sputtering • The physical removal of atoms from a target by energized ions (plasma) and • The evaporation of metals by resistive, inductive, or electron beam heating in reformation of a film on a substrate order for condensation to occur on a substrate, thereby, forming a film • Amorphous thin films, conformal/nonconformal coatings • Amorphous thin films, semi-conformal coating • High vaccum • From melting temperature of metal to 200 °C, high vacuum, on order of 2 • Most materials can be sputtered: metals, organics, inorganics µm/hour deposition rates • Electroplating • Metal conductor lines, solder • The electrochemical reaction of a solution, on a seed surface, to form a metal film deposition, mirror surfaces, • Amorphous thick and greater films electrical contacts • Spin Casting • Thin film material dissolved in a volatile liquid solvent, spin coated onto a substrate to form films • Low quality, but convenient amorphous thin or thick films • Room temperature application, ≈ 100 °C cure temperatures • Organic polymers, inorganic glasses
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6 Sputtering System Microelectronics Fabrication
Dopant Ions • Impurity Doping Source Dopant • Si or polysilicon doped for the purpose of Gas or Doped increasing conductivity or creating etch stops Layer Mask • Constant/Limited Source Diffusion or Ion Implantation Substrate • B in Si is p-type • P in Si is n-type
Si Si
Si Si Spire Corporation
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Microelectronics Fabrication Microelectronics Fabrication
• Photolithography • Photolithography - Mask Production • The technique of transferring a pattern to • When masks are designed, each design layer must be specified as either: UV light a surface • Light Field or Dark Field • Etch masks (soft), insulating layers, passivation, • With light field, a polygon on your design will appear as a polygon of chrome (which will block UV) on the mask. Conversely for dark field. protection, structures • The type of photoresist (positive or negative) will determine what the developed features look like. • Contact, Proximity, and Printing
Design layer (as seen on computer screen) Glass or Quartz Mask Plate
Chromium Dark Field Pattern Light Field
Shadow
Gardner, Microsensors, MEMS and Smart Photoresist Devices, 2001. Chromium layer (as seen on mask) EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 27 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 28
7 Lithography Microelectronics Fabrication
• Photolithography
Substrate
Negative Resist
Substrate
Substrate Spinner Bench and Relevant Mask Aligner Chemicals & Supplies Positive Resist
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 29 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 30
Microelectronics Fabrication Microelectronics Fabrication
• Etching • Etching Etchant Products • The process of selectively removing material Mask • Wet, Gas, Plasma Assisted (RIE)
Wet or Gas: Isotropic unless material to be etched exhibits anistropic behavior Etchant
Mask Gardner, Microsensors, MEMS and Smart Devices, 2001.
Nippon Scientific Co., Ltd Reactive Ion Etcher RIE: Anistropic Wet Bench
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 31 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 32
8 Microelectronics Fabrication: Dicing Microelectronics Fabrication: Wire Bonding
• To connect electrical contacts on chip to package or • Precision slices of semiconductor or other chips ceramic wafers • Gold or Aluminum wires 25 µm in diameter • 100 µm wide cuts in Si with a diamond blade Ball Bond
75 - 125 µm
Wedge Bond
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 33 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 34
Microelectronics Fabrication Overview
• Lift-Off Technique for Patterning Metal UV light Mask Photoresist • Materials Substrate Thin Film • Microelectronics Fabrication • Bulk Micromachining
1. Start 2. Spin/Spray coat photoresist 3. Expose • Surface Micromachining At least Solvent/Stripper • Micromolding Gold Film 4 × taller • Packaging
4. Develop 5. Deposit gold film 6. Perform lift-off by dissolving resist
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9 Bulk Micromachining: Si Bulk Micromachining • Processing of a Bulk Material
• Substrate is key Bulk • Customized Processing Micromachining
• A Subtractive Process • Large • Beginning with a Si substrate, Si is removed from the bulk • Features of the substrate, using etching, to form features. • Structures
Substrate
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Bulk Micromachining Topics Primary Micromachining Substrates
Elemental Semiconductors (Group IV) • Silicon • Substrates • Germanium • Masking Compound Semiconductors (III-V) • Thin Film Processing • Gallium Arsenide • Indium Phosphide • Etching Non-Semiconductor Substrates • Removing Undesired Material • Quartz • Wafer Bonding Why Silicon Processing? • Adding Additional Material 1) Abundant and Inexpensive 2) Billions invested in developing pure wafers and Silicon processing 3) Native Oxide with good electrical properties EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 39 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 40
10 Bulk Substrate Advantages Masking
Purity • Masking is the process of protecting the • Standard IC Issues • High quality substrates are readily available and substrate for a following etch process • MEMS related issues relatively inexpensive • Standard thin film techniques • Selectivity Material Properties • Ideal mask properties • Mask thickness • Mechanical and electrical properties are typically • Easy to deposit and pattern • Two sided processing well known • Non reactive - particularly to the bulk • Non-planar surfaces • Properties are more uniform than thin film etchant • IC Compatibility properties • Easily removed • Fewer issues with internal stresses • Typical Films Used Include •SiO Structure 2 •SixNy • Typically well known • Why not Photoresist?
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 41 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 42
Mechanical Properties Bulk Micromachining: Si
• Isotropic vs. Anisotropic Yield Knoop Young’s Thermal Thermal Strength Hardness Modulus Density Conductivity Expansion (1010 dyne/cm2) (kg/mm2) (1012 dyne/cm2) (gr/cm3) (W/cmoC) (10-6 /oC) *Diamond 53 7000 10.35 3.5 20 1.0 *SiC 21 2480 7.0 3.2 3.5 3.3 Concave Corners *TiC 20 2470 4.97 4.9 3.3 6.4
*Al2O3 15.4 2100 5.3 4.0 0.5 5.4 Isotropic *Si3N4 14 3486 3.85 3.1 0.19 0.8 *Iron 12.6 400 1.96 7.8 0.803 12 Convex Corner
SiO2 (fibers) 8.4 820 0.73 2.5 0.014 0.55 *Si 7.0 850 1.9 2.3 1.57 2.33 Steel 4.2 1500 2.1 7.9 0.97 12 W 4.0 485 4.1 79.3 1.78 4.5 Stainless Steel 2.1 660 2.0 7.9 0.329 17.3 Mo 2.1 275 3.43 10.3 1.38 5.0 Al 0.17 130 0.70 2.7 2.36 25 *single crystal.
(From “Silicon as a Mechanical Material,” K.E. Petersen, Proc. of the IEEE, Vol. 70, No. 5, pp. Anisotropic 420-457, May 1982.)
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11 Etching Etch Directivity
• Isotropic - Non-directional Etching is the process of removing a material. The key to making etching useful is to precisely and repeatably control the material that is removed. • Anisotropic - not isotropic (i.e. directional) Isotropic Anisotropic Types of Etches • Environment Etch Etch •Wet •Dry •Plasma • Mechanism • Physical To date, the majority of MEMS processing has been done with the wet bulk etching of silicon. This is primarily due to availability of the substrate materials and chemicals. Recent work has been looking at two • Chemical promising etch processes: deep RIE and xenon difluoride etching Example of a wet etch setup Thermometer Wet Isotropic Etching
SiO2 Reflux Container • Etch proceeds nearly equally in all directions Silicon Deionized Water • Primarily a diffusion limited process • Most common etchant:
Etch Solution Example wet bench “HNA” = HF/HNO3/Acetic Acid : 10/30/80 picture from: Wafer Carrier http://www.vinylglass.com/instant.shtml EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 45 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 46
Wet Anisotropic Etching SEMI Standard Wafer Flats
<111> SiO2 n-Type p-Type (100) Silicon (100) (100)
o SiO o 90 <111> 2 135 (110) Silicon
• Etch rate varies with the etch direction n-Type p-Type • Typically determined by the crystal planes (111) (111) Miller Indices 45o
The primary flat is specified to be the (110) crystal plane (100) (110) (111) EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 47 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 48
12 Anisotropic Etching Wet Anisotropic Etching
(100) Si Wafer 100 μm
• Etching a 100 micron wide via (110) 525 μm through a 525 micron wafer θ requires an opening that is 742 microns wide 742 μm
θ = 54.74o
(110) Si Wafer
ϕ1 (111) ϕ2
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 49 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 50
Suspended Structures Anisotropic Etching
• Primary Etchants • Alkali hydroxyls (KOH) •EDP • Quaternary ammonium hydroxides (TMAH) • Choice of etchant depends on: • Etch Rate • (100)/(111) Etch Ratio • Hillock formation • Potassium Hydroxide (KOH) • High Etch Rate • Good Masking Selectivity • Excellent (110) to (111) Etch Selectivity • 50% By Wt. at 85 deg. C •2.0 μm/min (110)
• > 200:1 selectivity for (110) SiO2 • > 250:1 selectivity for (110):(111) • (110):(111) selectivity depends on alignment EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 51 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 52
13 Potassium Hydroxide (KOH) Anisotropic Etching
Temp. Etch Rate (100)/(111) Masking Films • Hillock Formation Formulation (oC) (μm/min) Etch Ratio (etch rate) • Results from hydrogen bubbles KOH (44 g) • Generally a function of etch rate and selectivity 85 1.4 400:1 SiO2 (1.4 nm/min) Water, Isopropanol (100 ml) Si3N4 (negligible)
KOH (50 g) 50 1.0 400:1 Same as above Water, Isopropanol (100 ml)
KOH (10 g) 65 0.25 - 1.0 - SiO2 (0.7 nm/min) Water, Isopropanol (100 ml) Si3N4 (negligible)
• Ethylene diamine Pyrocatechol (EDP) • TetraMethyl Ammonium Hydroxide (TMAH) • EDP (750 ml) • Wide Availability • Pyrocatechol (120 g) • Excellent Masking Selectivity (> 1000/1) • Water (100 ml) • Al selectivity varies with solution ph • 22% by wt. TMAH in DIW at 90 oC • At 115 oC • approx. 1.0 μm/min • 0.75 μm/min (100) • approx. 25/1 (100)/(111) etch ratio (From: O. Tabata, et al., “Anisotropic etching of silicon in TMAH • 35:1 (100)/(110) Etch Ratio solutions”, Sensors and Actuators A, vol. 34, pp. 51-57, 1992. EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 53 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 54
Wet Anisotropic Etching Dopant Dependent
10 μm • Electrochemical Etching (ECE) • Etch rate controlled by electrical potential 525 μm • Dopant Dependent • Etch rate is modulated by wafer doping • Precision depth control is difficult to achieve • Three techniques are common: Silicon Diffusion • Timed Etches ECE + V - • IR Absorption IR Radiation Drive In • Etch cavities Silicon and Diffusion Wafer Electrode Etch Solution Etching
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14 Dry Etching XeF2 Etching
N2 • Vapor Phase Etching N2
•XeF2 • Plasma Etching Pulse/ • Deep RIE Roughing Etching Chamber Expansion Pump Chamber Why XeF2? • Provides a non-plasma isotropic dry etch Valves • Excellent selectivity for CMOS materials XeF2 • Excellent Photoresist selectivity Chamber • Simple System Set Up 2 XeF + Si => Xe + SiF • Good Etch Rate 3D Profile of silicon 2 4 etched using XeF2 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 57 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 58
XeF2 Etching Deep RIE • Commercial Systems are now available • Modified from standard reactive ion etching • Allows vertical side walls on (100) wafers • Pictures here are from www.xactix.com • Good Etch Profiles • Etching up to 1 mm deep • Masking with photoresist • IC Process Compatible • 200:1 Aspect Ratios •Also done with GaAs
Picture of the Stanford Nanotechnolgy Centers ICP RIE system http://snf.stanford.edu/Equipment/stsetch/stsetch2.jpg
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 59 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 60
15 Bulk Micromachining: Si Etchants Bulk Micromachining: Si Etchants
† • Deep Reactive Ion Etch DRIE
• Alternating steps of etching (SF6) and polymer formation (C4F8). isotropic RIE note: RIE is mainly used for its anisotropy Courtesy of IMO Wetzlar
anisotropic KOH † (an Alkali Hydroxide) Scallops Senturia, Microsystem Design, 2001 Technical University Berlin
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Bulk Micromachining: Etch Stops Bulk Micromachining: Case Study
100 µm Etchant - p+ V 40 μm p • A post-processing + step after MEMS fab n • Crystallographic diffusion or Etch stops at p-n junction Membrane • (111) stop epi-layers • Doping • p+ (Boron) stops the etch “p-stop” • Electrochemical deep pit • Higher potential relative to etchant 40 µm promotes oxide growth • A post-processing • “Junction-stop” step after microeletronics fab
Flexures 7 μm
• Reactant Limited • Reaction products form bubble Layouts and SEM courtesy that blocks arrival of reactants • Dielectric Film Stop of Li-Anne Liew, 2001
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16 Bulk Micromachining: Case Study Wafer Bonding
• Used to create high-aspect ratio: multilayer structures, sealed • A custom process step: Motorola MPX4080D series piezoresistive cavities, multilevel chambers, etc. differential pressure sensor • Anodic Bonding
• Glass to Si or SiO2 • 0.5 µm metal lines can pass under seal • 1.2 kV @ 400 °C, + (anode) on Si • Si to deposited glass on Si substrate • 30 - 60 V @ 400 °C, + (anode) on Si • Fusion Bonding
• Si to Si with or “without” SiO2 • Clean wafers at ≈ 800 °C • Other Low Temperature Methods • Temperature limit for IC processed standard substrates is 450 °C
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Wafer Bonding Fusion Bonding
• Three Basic Steps Surface Preparation • Surface Preparation • Residue Free Organic Etch •Flat • Sulfuric Acid • Roughness less than 0.5 nm • Acetone/Methyl • The permanent joining of two • Silicon Fusion Bonding • Hydrophilic * • Boiling Nitric Acid Solutions substrates • Hydrophilic vs. Hydrophobic • Si-Si, Si-O-Si • Contacting • RT bonding is due to Hydrogen bonding • Immediately after preparation • Covalent bonding • Anodic Bonding •H-N • Annealing •H-O Contacting • Glue layer • Electrostatic Force • Bond Depends on Temperature •H-F ) • Widely applicable to •Si-Glass 2 Micromachining • Low Temperature Melting Glass • Three Phases • Buried layers • Si-Glass-Si • Below 300 deg. C • Packaging • 300-800 deg. C Annealing • Metal Bonding • Above 800 deg. C Interface Energy (erg/cm Energy Interface Excerpted from: “Semiconductor wafer bonding: recent developments,” Materials Chemistry and Physics, 37 (1994), pp. 101-127. Annealing Temperature (deg. C) EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 67 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 68
17 Anodic Bonding Anodic Bonding
GND EV Group EVG 501 manual bonder
www.evgroup.como Temp: up to 550 C Force: up to 3400N (765 lbf) Opt. to 7000 N Alignment: +/- 5 μm Max. Field: 1.2 kV (2kV opt.) Wafer size: up to 6 in dia. Pressure: 1E-5 mBarr – 2 Barr EV Group Gemini production bonder F => 350 PSI + + + + + + + + + + + + + + + + + + Potential -
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 69 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 70
Anodic Bonding Anodic Bonding
AML Wafer Bonder AML-402
www.aml.co.uk o • Low bonding temperature giving more design flexibility (300-500 C) Temp: up to 560 C • Thermally matched stress free bond Force: up to 2000N (450 lbf) Alignment: +/- 5 μm • No measurable flow of the glass occurs Max. Field: 2.5 kV • Since glass is an electrical insulator, parasitic capacitances are kept Wafer size: up to 6 in dia. extremely small Chamber Pressure: 1E-5 mBarr - ? • Hermetic seals. • High strength bond - higher than the fracture strength of glass Low Melting Point Glass High Pressure and Temperature • Primary Problems • Thermal Mismatch • Dirty Surfaces • 1 μm particle -> 5 mm unbonded region
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18 Bulk Micromachining and Bonding: Case Study Wafer Bonding Example
• MIT micro shirt-button-sized turbine:
A H. Epstein, et al., "Shirtbutton- Sized Gas Turbines: The engineering Challenges of Micro High Speed Rotating Machinery," Symp. on Transport Phenomena and Dynamics of Rotating Machinery, March 2000.
Figures from: “An Inertial-Grade, Micromachined Vibrating Beam Accelerometer”, IC Sensors white paper L. G. Fréchette, et al., “An Electrostatic Induction Micromotor Supported On Gas-lubricated Bearings,” MEMS 2001
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Wafer Bonding Example CMOS Post Processing
Notional process – Cap wafers 1. Deposit and pattern masks – silicon oxide on front, nitride on back
2. Bulk Etch (KOH)
3. Mask Strip Standard IC process – But all oxide cuts are 4. Deposit and pattern 2nd mask aligned to expose bare 5. Bulk Etch silicon in some regions 6. Mask Strip
Notional process – Bottom wafer 1. Protect front with thick resist (spray on) After IC fabrication is 2. Bulk Etch (KOH) complete, a bulk silicon 3. Strip Resist and Back side mask etch is performed
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19 Overview Surface Micromachining
• Materials • Microelectronics Fabrication • An Additive Process • Bulk Micromachining • Beginning with a substrate, thin films are deposited on top • Surface Micromachining of the substrate and patterned, using etching, to form features. • Micromolding • Structural layers are separated by “sacrificial layers” which • Packaging are removed at the end of the fabrication process.
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MEMS Fabrication Surface Micromachining
• Building on top of the substrate 1) Deposit A Passivation Layer • Substrate is less important Surface • Highly dependent upon IC 2) Deposit and Pattern the micromachining processing Sacrificial Layer • Precise control • Highly repeatable 3) Deposit and Pattern the Structural Layer
4) Remove the Sacrificial Layer
Substrate Structural Layer (Au) Passivation Layer (Nitride) Sacrificial Layer (Polyimide) Substrate (Silicon) EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 79 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 80
20 Surface Micromachining Surface Micromachining
Cantilevers Structural Layers Sacrificial Layers
Si3N4 SiO2, Photoresist Anchors Electrodes Al, SiO2 Polysilicon Polysilicon SiO2 Al Photoresist Polyimide Al
Note, many of the sacrificial layers are used in the design of IC’s
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Surface Micromachining
$1000 MEMS vs. ICs E-Beam Lithography
• Fewer processing steps Wafer Stepper System $1000 + $500 = $1500 • Increased feature sizes • Substrate independent processing
$1500 + $500 = $2000 Nitrogen Wet Bench Office Fill & E-Beam Area E Beam Garage Support Control CAD $100 Area SE M
• Lower cost Gowning Area Maintenance Area Acid/Base St o r a ge Test & Areas Assembly Tube RIEs Profilometer Wet Benches Area Furnace De-ionized Water So l v e n t Digital Wet St o r a ge Plant Go ld P lat in g
Etch Etch Ovens Asher DUV DUV Area Shop Office St a t io n µScope s Mask Aligners Area Evaporator Sp ut t er e r On-Wafer Pump & Reliability Vacuum Maintenance Chase $400 Room AFM $5,000 Evaporator Sp ut t er e r St e p p er RTAs Reliability Test ICP RIE System MBE Equip P rep CVD DC/RF
FIB AFM Pol aron Ellipsometer Test Curve Tracer
FIB/SEM $5,500 $500
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 83 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 84
21 Surface Micromachining Steps Basic Switch Design
• Lithography Substrate Side View • Alignment (Up position) CPW Dielectric • Resolution Membrane Contact Area • Masking Side View • Material Deposition (Down position) • Material Selection and Properties Port 2 • Conformance Top View • Sacrificial Etching • Stiction Port 1 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 85 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 86
Process Flow Substrate Choices
• Substrate Requirements: • MUST be flat 1. Pattern and evaporate 1st • Compatible with all processes metal layer. • Desired attributes • 200 Å Ti, 3000 Å Au • Cheap and available • Metal lift-off process Problems with Substrate Independence •3”GaAssubstrates • Easy to work with • Surface quality: • Device specific • Roughness Questions: • Material choice • Uniformity 1. What substrate should we use? • Device specific • Process and equipment compatibility 2. What material should we use? • Adhesion 3. How do we deposit the first layer? • Type of substrate (square or round) 4. How do we pattern the first layer? • Etch steps • Photoresist EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 87 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 88
22 Example Substrates Fabrication Processes
• Silicon • Primary Metal Deposition Evaporation • Cheapest and Largest area (up to 300 mm diameter) Techniques Wafers • Low resisistance • Sputtering Bell Jar Source • Most widely used • Evaporation (E-beam) • Gallium Arsenide • Electroplating • Fragile • Commonly used metals Vacuum Port Sputtering Shield • Sizes up to 150 mm • Adhesion layers: Cr and Ti • Most commonly used RF Substrate Source •Aluminium (Cathode) • Sapphire • Gold Wafers • Exceptional RF Substrate Anodes • Copper • High εr • Nickel To Vacuum Pump • Quartz Gas EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 89 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) Inlet 90
Evaporation/Sputtering Exposure Evaporation E-Beam Filament
Crucible Source
Ar+ Contact Proximity Stepper: - -+ Typically reduces + Sputtering image
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 91 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 92
23 Lithography Patterning
Etch Back Lift Off Substrate Substrate Substrate Negative Resist Substrate
Substrate Substrate Substrate Substrate Substrate Positive Resist Substrate
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 93 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 94
Exposure Patterning
• Lift off • Often results in wings • Does not require as many chemicals • Limits Process Temperatures Expose Develop - Positive Etch - Positive • Etch Back Positive Resist • Often provides better results Etch Back • Etch can be done with a variety of techniques Film matches mask Strip • May be undercut problems Conformance The deposition of a material onto a non-planar surface often results in a poor coating of the sides of a structure
Expose Develop - Positive Deposit Positive Resist Mask PR Process Type Image YBCO Postive Etch Back Copy Lift Off Nitride Positive Lift Off Inverse Lift Off Film is inverse of mask Bridge Positive Lift Off Inverse This can result in two layers that were supposed to be isolated being connected EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 95 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 96
24 Evaporation Lift-Off
Silicon
Silicon
Silicon 2. Deposit and pattern dielectric material.
• 2000 Å sputtered silicon nitride • Dry etch process (Freon 14)
Questions: 1. What material should we use? 2. How do we deposit this material?
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 97 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 98
Material Choices Silicon Dioxide (SiO2)
• Device dependent • Most commonly available • Quality • AKA • Phosphosilicate glass • Uniformity • Borosilicate glass • Defects
• Film Properties SiO2 Properties Dielectric • Material properties Deposition Step Thermal Density Refractive Stress Strength Method Coverage Stability (g/cm3) Index (MPa) 6 • Mechanical properties (10 V/cm) PECVD Varies Looses H 2.3 1.47 300 C 3 to 6 to 300 T Thermal Conformal Excellent 2.2 1.46 300 C 4?
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 99 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 100
25 Silicon Nitride (Si3N4) Fabrication Processes
• Common Dielectric Deposition Techniques • Excellent Dielectric • Sputtering • Requires Boiling Phosphoric Acid for a wet etch • Reactive • Excellent barrier for Alkali ions •CVD •PECVD Si N Properties • LPCVD (Shown) 3 4 •APCVD Dielectric Deposition Deposition Si/N Density Refractive Stress Strength Wafers o 3 Method Temp. ( C) Ratio (g/cm ) Index (MPa) (106 V/cm) Vacuum Port LPCVD 700 - 800 0.75 2.9 to 3.1 2.01 1,00 T 10
PECVD < 350 0.8 to 1.2 2.4 to 2.8 1.8 to 2.5 200 C to 5 500 T Gas Three Zone Furnace Inlet EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 101 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 102
Deposition/Sacrificial Sacrificial Layer Choices • Requirements • Selective etch available • Compatibility 3. Deposit and pattern sacrificial layer. • Materials •PMGI resist • Polymers (Photosensitive?) • 2 µm - 5 µm thick • Reflow above 200 ºC • Oxides (SiO2) • Metals • Others (Silicon) Questions: 1. What material? • Considerations 2. Patterning? • Profile • Processing limitations EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 103 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 104
26 Dimple/Bridge Metal Polysilicon/ Deposition Concerns
• Also Widely Used • Thin Film Properties • High value resistors •Stress • Young’s modulus 4. Etch bridge dimples in PMGI • Piezoresistors • Landing bumps • Thermal properties (stability, • Metal-to-metal contacts • Mechanical structures expansion, conductivity) 5. Pattern and deposit bridge • Typically Deposited with • Ion penetration metal. LPCVD • 200 Å Ti, 6000 Å Au • Step Coverage • Evaporated or plated • Doped in-situ • Uniformity/Pinhole defects • IC Compatibility • Availability
Questions: 1. Why Dimples? 2. How are they formed? 3. Bridge material? EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 105 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 106
Bridge Metalization Release
6. Plate overlay layer
• 3 µm - 5 µm plated gold • Strengthen bridge landings 7. Remove PMGI sacrificial layer • Compensate stress gradients • Wet release process • All organic solvents • End with acetone • Boil off acetone in vacuum Questions: 1. Material? 2. Deposition? EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 107 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 108
27 Sacrificial Etch Etch Holes
The etch rate (x/t) is diffusion limited s x • Etch Holes are placed with a maximum center to center spacing, l
l • The etch holes must have a minimum size, s Note that the etch rate may slow down over time Structural Layer (Au) Passivation Layer (Nitride) Sacrificial Layer (Polyimide) Substrate (Silicon)
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 109 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 110
Stiction Stiction
• When two flat, smooth surfaces come into contact they tend to stick • This problem can be solved by several methods • This is a problem • Coating the structures with a solution • During the release process • Optimizing the temperature • During device operation • Final Methyl Rinse • During the drying process, the water evaporates slowly from under the released • Dimples structures Stiction (Dimples) • Dimples are formed by partially etching the underlying sacrificial layer • The deposited structural layer is then contoured around the • The evaporation of the water results in an attractive force pulling the released indentation structure towards the substrate • Dimples prevent large flat areas of the substrate from coming into • When the surfaces come into contact they are held together by atomic bonds contact, thus reducing the effect of stiction EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 111 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 112
28 Stiction (Critical Point Dryer) Thin Film Properties
• Not well understood • Use Supercritical Region • Properties are often not uniform For CO2, the Supercritical point is where there is no surface 31.1 oC and 72.8 atm (1073 psi) • Variation from run to run tension, and liquid and gas • Polycrystalline materials phase are blurred • Material Stresses • Buckling • Change in Mechanical Properties Liquid Supercritical Region Compressive Stress Solid 1 2 Pressure
3 Tensile Stress Gas Temperature
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 113 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 114
Thin Film Properties Measuring Stress
• Wafer Bow • Stress gradients: • Not Accurate locally, or for actual release values • MicroRaman • Allows local stress measurement • Non-destructive • Young’s Modulus Varies • Pre-release • Test Structures l • Cantilevers • Buckled Beams d • Guckel Rings F • Pointers
t F* l3 d = 3 w E * w * t
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 115 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 116
29 Cantilevers Buckled Beams
• Cantilevers • Measured with an interferometer Poly1 • Gives a ‘feel’ for stress effects, but is not accurate • Buckled Beams Buckled Beams 1st Buckled • Provides a process control monitor – total tip deflection • Arrays can be used to get Beams 120 µm 240 µm MMPOLY1/2/3 a good estimate of
MMPOLY1/2 compressive stresses
MMPOLY1 • As a PCM, they take up a Buckled Beams Cantilever up deflected toward Cantilevers stuck to lot of space substrate substrate • Visually readable Poly2
Not buckled
Buckled (a) Polysilicon Cantilevers (b)
Substrate EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 117 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 118
Guckel Rings Controlling Stress
• Guckel Rings Annealing • Allows measurement of tensile stresses • Design • Must have a good knowledge of the stress to be effectively used • Multiple layers • Thicker materials • Deposition • Substrate heating • Process parameters • Annealing • Ion Implantation
Graph from University of Wisconsin -Work done by Prof. H. Guckel Images from “Diagnostic microstructures for the measurement of intrinsic strain in thin films,” H. Guckel, et al, J. Micromech. Microeng. 2 (1992) 86-95. http://mems.engr.wisc.edu/research/strain EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 119 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 120
30 IC Compatibility Building Blocks
Cantilevers Bridges Single Layer Structures • Material Selectivity 2 Poly • Sacrificial Layer • Temperature Two Layer Structures/3 Poly Flip Chip Technology Sliders • Annealing CMOS Substrate • Current and Voltage Levels Two Layer Structures/3 Poly Pin-Joints • Solutions Two Layer Structures/3 Poly MEMS Substrate • Packaging Hinges • Modify MEMS Processes • Isolation
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 121 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 122
Building Blocks –Flip-Up Structures Surface Micromachining
Self Engaging Substrate DARPA Sponsored Multi-User MEMS Process Lock Hinges (MUMPs)
Scissors Hinges
Flip-Up Plates
mems.mcnc.org/mumps.html
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 123 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 124
31 Lucent LamdaRouter mirror Lucent LamdaRouter mirror Lucent LamdaRouter Operation
Picture from http://www.bell- labs.com/news/1999/november/10/single_color.tiff
http://www.bell-labs.com/org/physicalsciences/projects/mems/mems3.html EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 125 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 126
iMEMS Comparing iMEMS and MUMPS
Process iMEMS poly MUMPS Masks 27 8 Processing Steps > 410 >70 Structural Layers 12 Structural Layer Types Polysilicon Polysilicon Layer Thickness 2 - 4 1.5 - 2 Min Feature Size 12 Mechanical Yes Yes Integrated Cicruits Yes No
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 127 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 128
32 Surface Micromachining: Surface Micromachining: Polysilicon Polysilicon
• Ex. The making of an electrostatic micromotor: • The first step is to deposit and pattern a layer of structural polysilicon. This layer often serves as a structural base or an electrical path.
Step 1
1st Polysilicon Layer Cross section of motor Silicon wafer Cronos
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 129 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 130
Surface Micromachining: Surface Micromachining: Polysilicon Polysilicon
• The second step is to deposit and pattern an oxide sacrificial layer. • Next, a second polysilicon structural layer is added and etched to This layer is used to separate and define the shape of subsequent obtain a desired shape. polysilicon layers. Step 2 Step 3 Etched 2nd Polysilicon 1st Oxide Layer Areas Layer
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 131 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 132
33 Surface Micromachining: Surface Micromachining: Polysilicon Polysilicon
• Another oxide sacrificial layer is then added and patterned. • The 3rd and final polysilicon structural layer is then deposited and etched to a desired shape.
Step 4 Step 5 3rd Polysilicon Layer 2nd Oxide Layer
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 133 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 134
Surface Micromachining: Surface Micromachining: Polysilicon Polysilicon
• The final step is to dissolve the oxide sacrificial layers with • After the release, all unattached parts usually settle into contact with Hydrofluoric (HF) acid. This leaves behind the complete and free whatever is beneath them. polysilicon MEMS structure. Pin Step 6: Release Rotor
Cronos Stator
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 135 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 136
34 Surface Micromachining: Step MUMPs Fabrication Image Coverage
MUMPs Foundry Fabrication • Primary foundry fabrication used in this research • Conformal or Nonconformal • Known to exhibit inherent residual stress • Fairly inexpensive (~ $3,100) • Timely (new die every 2-months)
MUMPs Metal (0.5 μm) logy and Devices, 94 logy and Devices, Poly2 (1.5 μm) Oxide2 (0.75 μm) Poly1 (2.0 μm)
Oxide1 (2 μm) Techno Ristic, Sensor
Poly0 (0.5 μm) 2 µm thick PSG using LPCVD: SiH4, 2 µm thick PSG using PCVD: TEOS, O , and PH at 425 °C and 280 mtorr SiN (0.6 μm) 2 3 TMP, and O2 Substrate
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 137 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 138
Commercial Surface Micromachining: Surface Micromachining: MUMPs Examples Polysilicon
• MEMSCAP -- The Polysilicon Multi-User Metal (gold) MEMS Processes, or polyMUMPs® Polycrystalline Silicon (doped with P) • Started in 1992 • www.memscap.com/memsrus/ Oxide (PSG: Si02 doped with P) • 15 copies of a 1 cm × 1 cm die, $3,200.00 Nitride (Si3N4) Crystalline Silicon 1.5 μm poly2 0.5 μm 0.02 μm Cr 0.75 μm oxide2 via metal
2 μm poly1
2 μm oxide1 Phosphosilicate Glass 0.75 μm anchor1 dimple 0.5 μm poly0 anchor2 0.6 μm anchor1 & via anchor1 & highly doped with P region MEMS self- assembled mirror (100) silicon wafer, n-type (P), 1-2 ohm-cm resistivity Designed and imaged by J. R. Reid, AFIT 100 mm diameter, 500 - 550 μm thickness
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 139 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 140
35 Surface Micromachining: MUMPs Examples Surface Micromachining: MUMPs Examples
Hinge
Designed Designed and and imaged by imaged by W. D. Cowan, Spaces and widths are J. R. Reid, AFIT incremented by 0.25 µm AFIT Laser Blast! 2 µm width
2 µm space
Fab Gauges Motor Designed and imaged by P. E. Kladitis, AFIT Mirror
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 141 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 142
Surface Micromachining: MUMPs Examples Surface Micromachining: MUMPs Examples
Designed and imaged by P. E. Kladitis Wheels on Square Micro Chains Axles
Designed and imaged by P. E. Kladitis
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 143 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 144
36 Surface Micromachining: MUMPs Surface Micromachining: MUMPs Examples Examples
• What does this look like after assembly?
Springs and Things
Designed and imaged by P. E. Kladitis EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 145 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 146
Surface Micromachining: MUMPs Examples Foundry Fabrication Etch
Vertical diffusion • MUMPs Foundry BOE Lateral Lateral Fans, Hubs, diffusion diffusion Substrate Poly1 Contact,
Heaters Vertical diffusion Nitride Substrate Denotes phosphorous diffusion
Stringer Etch Poly1 Stringer etch Designed and imaged by undercut undercut P. E. Kladitis Nitride Substrate
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 147 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 148
37 Bonus Slide Commerical Surface Micromachining: Polysilicon
Available CAD Layers • SUMMiT IV & V, Sandia & Minimum Width (μm): mmpoly1_cut mmpoly3_cut 1 mmpoly3 1 National Laboratory Polycrystalline Silicon sacox2 sacox3_cut 2 Oxide (Si0 deposited from Dimple • 100 copies of a 6.34 mm × 2 dimple3_cut 1.5 2.82 mm die, $10,000 TEOS tetra-ethyl-ortho-silicate) Global oxide 2 mmpoly2_cut 1 correction for mmpoly2 1 Nitride (Si3N4) • V provides a 5th planarized MUMPs-like layout sacox2_cut 2 sacox2 1 Crystalline Silicon layer of poly mmpoly1_cut 1 Max etch hole spacing 38 μm mmpoly1 1 Max dimple spacing 75 μm pin_joint_cut 3 sacox1_cut 2 dimple1_cut 1 2.25 μm mmpoly3 mmpoly0 1 nitride_cut 1, max 4 5.6 μm CMP to
Gold 1.5 - 2 sacox3 dimple2
μm 0. 5 μm sacox3 cut sacox3 cut 1.5 μm mmpoly2 Stringer 0.5 μm sacox2 1 μm mmpoly1 mmpoly1cut
2 μm sacox1 pin joint cut nitride cut sacox1 cut dimple1 ≈ 3 μm sacox1 cut 0.3 μm mmpoly0 0. 5 μm 0.8 μm silicon nitride 0.63 μm silicon dioxide
<100> silicon wafer, n-type, 2 - 20 ohm-cm resistivity, 6” diameter, 675 μm thickness
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 149 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 150
Surface Micromachining: SUMMiT Examples Surface Micromachining: Release
• Wet HF etch removes the P-doped SiO2 or mems.sandia.gov phosphosilicate glass (PSG)
Chemical Wet Bench / Fume Hood Critical Point CO2 Dryer 31 °C and 7.38 MPa EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 151 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 152
38 Surface Micromachining: Surface Micromachining: Release Release 40 Clean Etch Rinse Dry 30 • Release Failure Mechanisms • Insufficient etch times, temperature, PSG phosphorous content 20 • Insufficient number of etch holes • for 2.5 - 5 minute etch times, etch holes should be 30 µm apart for MUMPs type designs 10 • Allowing surface tension forces, of drying rinse fluids, to pull Temperature (°C) Temperature microstructures against the substrate causing permanent adhesion …. this phenomena is sometimes called stiction 0 15 m 5 m 5 m 10 m 7 m 14.5 m 4.5 m 15 s m = minutes 15 s Time s = seconds 2.5 - 5 m
= Acetone (Dimethyl Ketone) CH3COCH3
= 2-Propanol (Isopropyl Alcohol) CH3CHOHCH3 = Deonized Water = 48% Hydrofluoric Acid HF = Carbon Dioxide CO2 gas
= Methanol CH3OH = CO2 liquid
= Methanol:DIW 3:1 = Methanol mixed with liquid CO2 Ristic, Sensor Technology and Devices, 94 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 153 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 154
Silicon On Insulator (SOI) Silicon On Insulator (SOI)
• Si Bulk Micromachining • The creation of microstructures by bulk etching of material from the substrate by (an-)/isotropic wet/dry etching or reactive ion etching. • Surface Micromachining • The creation of microstructures by the selective patterning of thin films and a sacrificial etch. •SOI • Combining bulk etching and a sacrificial etch gives Silicon On Insulator (SOI). • Anodic or Fusion Bonded, commercially produced or made in-house.
Sacrificial Oxide SiGen Si Substrate Thickness is your choice Si Substrate
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 155 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 156
39 Silicon On Insulator (SOI): Overview Example
• A scanning micromirror with angular comb drive actuation -- P. R. Patterson, et al., 2002. • Materials • Microelectronics Fabrication • Bulk Micromachining • Surface Micromachining • Micromolding • Packaging
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 157 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 158
MEMS Fabrication Microforming
• Grow what you need • Surface Microforming Micromachining • Basic process is generally simple Process • High Aspect Ratio Structures • High Aspect Ratio • MEMS Specific Micromachining (HARM) • Typically Metal • Aspect Ratio
Substrate SEM from mems.mcnc.org EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 159 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 160
40 Microforming LIGA In German: Lithographie, Galvanoformung, Abformung • Requires Highly Collimated X-Ray source such as an X-Ray Expose Synchrotron • Resist is Polymethylmethacrylate (PMMA) • Aspect Ratios over 100! • Comparable with Anisotropic Wet Etching Develop Synchrotron Radiation Electron Orbit Target Electroplate • Provides X-Rays • High intensity collimated X-Rays Release • But • Requires expensive facilities (>$ 30 M) EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 161 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 162
LIGA Micromolding: LIGA Masking Lithographe, Galvanoformung, Abformung • Requires special masks Resist: Synchrotron Radiation polymethylmethacrylate > 10 μm thick X-ray Absorber • Cost per mask can exceed $10,000 (PMMA) Mask Membrane
Substrate UW Plating Base (Ti/Ni) SLIGA: when the plating base or other material is Electroplated Metal (Ni) used as a sacrificial layer under the metal. Deposition Resist • Electroplating Metal Mold • Electroless plating • Primary difficulties
• Thickness (over 100 μm) Injection Molding Plastic (plastic) Structure •Stress • Selective CVD Institut für Mikrotechnik Mainz GmbH EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 163 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 164
41 Electroplating Electroplating
Thermometer Pulsed Electroplating ++ Cu • Typical pulse parameters - V + Cu++ • 1 kHz • 10% Duty Cycle - Cu++ - • Provides - - - - - • Better stress control • More uniform Deposition V ++ - Cu + 2e => Cu(s) 5
Au(CN) - + 2e- <=> AuCN + CN- 0 2 - - t AuCN + e <=> Au(s) + CN on t t cyc Sample Electrode EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 165 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 166
Molding Impression Molding
The cost of the X-Ray exposure, and mask are offset by using the metal parts not as an end product, but instead as a mold. Oxygen RIE
Formation of secondary plastic template Plating • Three primary techniques • Reaction Injection Molding Electroplating to form metal parts • Mix polymers just before injection • Thermoplastic Injection Molding • Heat the polymer to a viscous state Release • Impression molding • Printing Process • Primary technique used in German processes EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 167 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 168
42 Sacrificial Processes LIGA Limitations
A sacrificial layer can be added to the process •COST!! SU-8 – Example Polyimide • Developed by IBM Sacrificial Layer •X-Ray source availability •Masks • UV exposer 350-400 nm • Typically only one layer • Aspect ratios greater than 20:1 • Thickness over 200 microns After the PMMA is removed, • Radiation Damage • Primary difficulty the seed layer and the sacrificial layer are etched away Deep UV Processes •Epoxy based resist that is difficult to strip • Poor Man’s LIGA Multilayer Processing • Replace PMMA and X-Rays with Photosensitive Polyimide and Deep By planerizing the surface, a second UV (240 nm) exposure layer can be added. • Aspect Ratios > 10
The process can also be used in • Structures up to 30 μm tall conjunction with surface • Availability micromachining processes. • Standard Lab Environment EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 169 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 170
EFAB Micromolding: Other
• Laser Machining • Heat treatment • Welding • Ablation • Deposition • Etching • Lithography • Photopolymerization • Microelectroforming • Focused-beam milling of plastics, glasses, ceramics, metals
List compiled from M. Madou, Fundamentals of Microfabrication, 1997
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 171 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 172
43 Other Miscellaneous Commercial Micromolding: Other Micromachining
• Micro-Stereo-Lithography (MSL) • Objects are built layer by layer. MetalMUMPs - 10cm wafer fab • An image (UV light) of the layer to be built is generated and projected onto the surface of a photopolymerizable resin. • A selective polymerization of the liquid resin occurs in the 1-3 µm Au (for side contacts) CuTi (plating base) irradiated areas. 20 µm Ni + 0.5 µm Au • A shutter cuts out the light when the layer is solidified. • The polymerized object is then lowered in the photoreactor, 0.35 µm Si3N4 immersing it slightly in fresh resin. (for electrically isolated • When the liquid surface has been stabilized, the irradiation of the structural interconnects) next layer can be started.
0.7 µm polySi (for wiring and structures) 2 µm SiO2 25 µm deep bulk etched trench
500 µm thick n-type (100) Si wafer
Dept. of Microtechnique, Swiss Federal Institute of Technology, Lausanne EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 173 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 174
Other Miscellaneous Commercial SOI MUMPS Micromachining
1. Begin with silicon on insulator wafer, 25 μm top silicon SOIMUMPs layer, 400 micron thick substrate, 2 mm oxide. A back side oxide is also present
2. Lithographically pattern a photoresist on top of the thin silicon layer. Etch down to the oxide using the photoresist as a mask. Strip the resist.
3. Blanket coat the top with a PSG layer. Anneal at 1050oC in argon to dope the silicon. Strip the PSG in a wet etch.
4. Lithographically pattern photoresist on the back side of the wafer. Use DRIE to etch through the wafer, stopping on the oxide. Strip the photoresist
5. Remove the oxide in a buffered oxide etch
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 175 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 176
44 SOI MUMPS SOI MUMPS
6. A shadow mask is created out of a second silicon wafer. Example of a comb resonator design in SOI MUMPS
7. The shadow mask is temporarily bonded to the top silicon layer, and the metal layer is deposited.
8. The shadow mask is removed. Example of a comb resonator design in SOI MUMPS, zoomed in on the support and fingers
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 177 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 178
Bulk Micromachining IC Compatibility
Bonding Wires • Material Damage STW Resonator •SiO 2 Support Arms •Al Isolation Platform 8 mm •Temperature Support Rim • Doping • Pre- or Post- Processing
9 mm
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 179 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 180
45 Overview IC Compatibility
• Separation
• Materials • System in a Package – Ex. IC Sensors • Microelectronics Fabrication Separation Sensor • Bulk Micromachining • Flip Chip • Surface Micromachining • Integration IC • Micromolding • MEMS First – Ex. DMD • Packaging • Integration – Ex. ADXL • IC First – Sandia
Picture from IC Sensors Application notes: Model 3255 Accelerometer
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 181 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 182
Lucent LamdaRouter Packaged Die IC Compatibility
Flip Chip Technology
CMOS Substrate
MEMS Substrate http://www.bell-labs.com/org/physicalsciences/projects/mems/mems3.html
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 183 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 184
46 IC Compatibility – IC First IC Compatibility – IC First
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 185 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 186
MEMS Fabrication IC Compatibility – MEMS First
Picture from: J.H. Smith, et al.,“Characterization of the embedded micromechanical device approach to the picture of ADXL202 monolithic integration of MEMS with CMOS,” SPIE Micromachining and Microfabrication ’96 from www.analog.com EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 187 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 188
47 IC Integration IC Packaging
• MEMS First • Packaging + IC fab is not compromised • Puts devices into an easily manipulated container + Allows high temperature anneals • Provides the system with the proper environmental interaction – Can result in difficult interconnects • Cost of Packaging is non-trivial – Complicates release • often 70%-80% of total unit cost • IC First • IC Packaging + IC Fab is not compromised • MEMS specific Packaging + Most expensive processing done first IC – Limits processing temperatures and thus material choices Adhesive • Integrated Process + Fewest number of steps – Greatest complexity Wirebonding EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 189 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 190
IC Packaging Primary IC Issues
• Electrical Connectivity Dicing & Pick & Wire • Interconnects Sealing Separating Place Bonding •RF? • Reliability •Au/Al DMD Packaging • Thermal Management • Where do we release • Heat Sink/Fan • What about dust particles • Environment • COST!!! • How do we seal • Automation • Must maintain free motion • What about access • Optical or pressure interconnects
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 191 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 192
48 Switch Packaging Approaches (Known Efforts) Wafer Level Packaging
Conventional (Chip-in-box) (<10%) Dice ⇒ release ⇒ package or Dice ⇒ package ⇒ release Ceramic / Metal package Thin-film Encapsulation (<10%) < 10% < 10% Thin-film bubble, cap ⇒ Release through holes ⇒ Seal ⇒ Dice
Wafer Bonding (> 80%) Release ⇒ > 80% Bond cap wafer ⇒ Dice Metal eutectic or Glass frit seal
Approaches Roa, Intel 2000 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 193 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 194
Wafer-Level Cap Silicon Nitride Encapsulated Switches
• Wafer-to-Wafer Bonding is Employed to Cap the Individual Switch Die • Provides Hermetic Environment • Low-Cost Packaging Solution • Optimization is in Process
• RMI has Produced Fully Functional Devices with Promising RF Results • High-Lifetime: >1011 Cycles •Best Case • Optimization of RF Performance is in Process Released switch under nitride cap Nitride cap partially removed showing released switch
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 195 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 196
49 Bulk Micromachining Summary
• Fabrication using bulk material • Silicon • Primary Processes • Masking • Etching • Wafer Bonding Fabrication Review • Large Structures • Less control over Dimensions • One to two regions • Bulk Micromachined Devices • Thermal Isolation • Reduction of Parasitic in Microwave Devices • Seismic Masses • Primarily Custom Processing
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 197 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 198
Surface Micromachining Summary Microforming Summary • Fabrication using thin films • IC fabrication • Fabrication using deposited films and molding • Primary Processes • Sacrificial Layer Processes • Primary Processes • Planar well defined processes •LIGA • Multiple releasable layers • Thick Resist • Two and half dimensional • Surface Micromachined Devices • High Aspect Ratio Micromachining (HARM) • Single layer structures • Typically 1 layer • Cantilevers • Bridges • Medium to good resolution • Micro-Hinges and flip up structures • Primarily Standard IC Processes EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 199 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 200
50 Process Comparison Process Comparison
Surface Bulk Process iMEMS poly MUMPS metal MUMPS SOI MUMPS Microforming Masks 27864 Micromachining Micromachining Processing Steps > 410 >70 > 50 >35 Structural Layers 1221 x,y dim. < 1 μm > 5 μm > 2 μm Structural Layer Nickel, Poly Nitride- Types Polysilicon Polysilicon Poly-Stack Bulk Silicon z dim > 20 μm Layer Thickness 2 - 4 1.5 - 2 20,2 25 < 5 μm > 20 μm Min Feature Size 1282 Mechanical Yes Yes Yes Yes # Layers 2-3 Releasable 1-2 1 Releasable Integrated Cicruits YesNoNoNo Available Die Size N/A 1 cm X 1 cm 1 cm X 1 cm 1 cm X 1 cm IC Compatibility Good Med-Poor Good Cost per die site N/A$ 4,600.00 N/A$ 7,500.00
Material Large Bulk Materials Metals Selection Aspect Ratio < 5 approx. 100 approx. 100
EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 201 EE 480/680, Summer 2006, WSU, L. Starman MicroElectroMechanical Systems (MEMS) 202
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