Behavior Research Methods & Instrumentation 1976, Vol. 8 (2), 123-128 A structured approach to microcomputer system design

KEN McKENZIE Corporation. Santa Clara, California .95053

A simple "building block" philosophy for construction of high-performance microcomputer-based systems utilizing I/O functional definition and a structured implementation of MOS/LSI semiconductor devices. The wide acceptance of the microcomputer as a DEFINITION OF SYSTEM ARCHITECTURE practical tool for on-line computation and dedicated control applications has drastically altered the manner in The heart of any structured philosophy is the disci­ which today's design engineer approaches a new project. pline upon which the system is based. In a microcom­ The traditional circuit by circuit analysis is no longer puter system, this discipline is referred to as the system necessary or desirable. A total systems approach of . Basically, it is a group of interconnections that closely studying each I/O device and its interface in con­ carry the total information transfer from one device in junction with the desired performance level of the over­ the system to another. All system devices, central pro­ all system then, by selectingthe proper MaS/LSI devices cessing unit, memory. and I/O, intercommunicate over and writing the support software, produces an efficient, the system bus. modular design. In the 8080 microcomputer system (see Figure I), The purpose of this paper is to show how a building the system bus is broken down into three major groups: block approach to both hardware and software will Data bus is the bus upon which all data flows in effect system design, introduce the latest MaS/LSI de­ the system. It is bi-directional in nature, allowing both vices, ami familiarize the uninitiated engineer with basic read and write operations to utilize the same bus. microcomputer terminology and jargon. Address bus: When the CPU wishes to read or write to a The structured philosophy presented here is based on specific memory or I/O device, it issues a unique binary the 8080 Microcomputer System (MCS-80), Intel Cor­ value (address) on the address bus. Control bus: The poration, Santa Clara, California.' collection of timing signals that gates data on and off of

HOLD REO

INT k------, ROY 8080A CPU

:r;?~ ~~~"fs::'1 8702A 8302 8'012 8102A-4 - 8107B-4 8704 ROMs 8308 RAMs II 8205 8UFFERS/ I 8'11·2 8210 I DECODER I lL8~1~ (OP2:.I~~~..J 8708 8316A 8102-2 5101 8222

DATA BUS 181 U vel II V D II {t rr:=r CONTROL BUS 161 LCIIU LI I I Il ~

8251 110 82'2 8214 \10 PRIORITY PERIPHERAL COMMUNICATION 8255 8212 INTERFACE INTERFACE

Figure 1. Microcomputer system (courtesy of Intel Corporation, Santa Clara, California).

123 124 McKENZIE

PAc, LSB Table I PA, MCS-80 Component Family* PA2 PA, Part No. Function PA. 8080A CPU MODE0 PAs 8224 Clock Generator (OUTPUTI PAs 12-BIT 8228 System Controller PA., D-A ANALOG OUTPUT CONVERTER r- 8212 Byte I/O pc. (DAel 8251 Communication Interface Pes 8255 Programmable I/O PC, 8253 Programmable Interval Timer 8255 PC, MSB 8257 Programmable DMA Controller 8259 Programmable Interrupt Controller STB DATA PC, OUTPUTEN *MCS-80 uses standard semiconductor memory components. BIT SET/RESET be implemented using a family of bus-compatible, micro­ PC2 SAMPLE EN rPC, STB computer, peripheral components. PB. LSB I/O DEVICE INTERFACE PB, 8-BIT A-D PH, CONVERTER ANALOGINPUT lADe) MODE 0 PB, -- As in any computer-based system, the (INPUT) PB. must be able to communicate with devices or structures I'll,; that exist outside of its normal memory array. Devices PB, such as keyboards, switches, displays, floppy disks, ~ MSB printers, A/D-D/A converters, and other control Figure 2. Digital to analog; analog to digital (courtesy of Intel structures are used to input information into the micro­ Corporation, Santa Clara, California. processor and store or display results of the computa­ the data bus is called the control bus. These signals are tional activity (see Figures 2 and 3). precisely generated so that when the transfer occurs, the The basic operation of the I/O structure of a micro­ data is stable and no conflicts occur with other devices computer system can best be viewed as an array of single on the system bus. byte memory locations that can be read from or written The transfer of information over the system bus must into. Generally, there are special instructions within the abide by an established procedure, which is called basic repertoire to handle such transfers (IN, OUT). The protocol. Bus protocol dictates a sequence of events that CPU issues a unique binary code, corresponding to the any device on the system bus must follow for efficient particular I/O port with which it wishes to communi­ data transfer. The timing disciplines of the bus protocol cate. The data bus is made available to the selected establishes "windows" in which the peripheral device device, and the transfer occurs in accordance with the must respond with valid data or be prepared to accept discipline of the bus protocol. An array of switches, for valid data. There are auxiliary functions of the protocol example, can be monitored by the microprocessor by that can insert compensation factors into these timing simply assigning each switch as a single bit of an input windows, such as "wait states." Consequently, the "port." The CPU can then read the value of the switch protocol discipline is designed to contain a limited array under control of the system software. In turn, the degree of flexibility. microprocessor can output the results of its computation The establishment of a standard system bus architec­ to an array of lights so that it can be read and ture greatly simplifies the design of peripheral, semi­ interpreted by the system user. These simple examples conductor components for microcomputer systems. The are, of course, descriptive of only the most primitive I/O interface to the microprocessor-generated data, address, functions of a microcomputer system. More common and control buses remains identical, and only the I/O applications would be driving motors, scanning key­ individual component functions are subject to additional boards, and monitoring analog sensors. Quite often the circuit engineering. Besides timing (ac characteristics), microcomputer is required to communicate with other the system bus also defines de characteristics such as computer systems that are separated by a great distance. leakage, current drive, voltage levels, and capacitance. By converting parallel system data (bytes) to a serial An often underrated feature, inherent in a properly stream of data, the microcomputer system can use voice­ defined standard system bus, is overall system noise grade telephone lines for this communication. Special immunity. The real measure of cost effectiveness of any semiconductor devices are specifically designed to system is the amount of time that such a system can be handle both transmission and reception of serial operated and provide accurate information. By allowing formatted data; such a device is the Intel 8251 for adequate system tolerance to noise in the design of (Figure 4). the system bus, a high-performance, reliable system can The recent advances in MOS/LSI technology, mainly MICROCOMPUTER SYSTEM DESIGN 125

KE':BOARD PRINTER 00 000 DISPLAY 00 " 000 00 c-l.' WEIGHING 000 --- UNIT 00 ~IH11111 ~IHI 000 00 IinuuCiI I LJ

I 1 I r------,I I OPTIONAl I INPUT INPUT DUTPUT OUTPU'- I INTERFACE "1 I INTERFACE" 1 INTERFACE "2 INTE RFACE"2 I I ~-- TT--..J I BOBO I~ ~ ItI It: CPU I I I '---- BUS

CONTROL UNIT IfI 1: 1

PROGRAM DA'-A MEMORY MEMORY (PROMI (RAMI

Figure 3. Data bus (courtesy of Intel Corporation, Santa Clara, California).

N-channel MOS, has made dedicated peripheral and I/O comes logical to organize the systems and application device controllers an economic reality. The complex software into a straightforward, modular fashion, almost nature of modem peripheral equipment interface and "building block" software. The modular approach to the resultant software overhead has made the use of such software generation also yields inherent diagnostic equipment unattractive to the small system user. By de­ capabilities and greater responsibility. signing a certain amount of "intelligence" into the semi­ conductor components that interface such equipment to the microcomputer system, the amount of software over­ head can be significantly reduced and the number of The real efficiency of the microcomputer is directly chips decreased, often to a single LSI component. proportional to the amount of tasks it can assume with Naturally, all such components would have to be little or no effect on the total system throughput. The designed to the system bus specification for simple inter­ most common method for I/O management is the polled face, but beyond that, each MOS/LSI component be­ approach (Figure 5). Each I/O device in the system is comes a "building block" whose only difference to any periodically tested by the software to ascertain if it other "building block" in the I/O structure is its func­ needs servicing, commonly referred to as "polling" an tional definition. The system software also must undergo I/O device. It is easy to see that a significant portion of a change in philosophy. Each MOS/LSI peripheral com­ ponent can be programmed to support a variety of con­ CPU-DRIVEN MULTIPlEXOR figurations within its major functional definition. The cPU software must initialize such devices and supervise what­ r----- ever maintenance is required for their operation. It be- -);) \ 0 ADDRESS BUS A --" RAM 1/0111 f---- " CON'-ROl BUS

DATA BUS

..J'-.. A --" ROM 1/012) r--- -v v v

• i ! 8251 r---, g- '. .: "I I CR'­ )I I/O IN) Y TERMINAL I I L L ___ ..J Figure 4. Asynchronous serial interface to CRT terminal, DC-9600 baud (courtesy of Intel Corporation, Santa Clara. Figure 5. Polled method (courtesy of Intel Corporation, California). Santa Clara, California). i 26 McKENZIE

is currently being executed and fetch a new routine

CPU INT that will service the requesting device. Once this - servicing is complete, however, the processor would resume exactly where it left off. This method is called L ;:. interrupt (see Figure 6). It is easy to see that system throughput would drastically increase, and hence more A "- RAM " PICU I--- tasks could be assumed by the microcomputer to further V " " I-- enhance its efficiency and cost effectiveness. In an interrupt-driven system, it is common that a number of peripheral devices would be requesting the attention of the processor, some at the exact same time.

ROM 1/0,1, I---- To efficiently manage such requests, the system designer v ~ must assign each requesting device a degree of impor­ tance, or level of priority, as it is more commonly referred to. An auxiliary component, called an interrupt control A J-. 1/0121 - unit, does the actual prioritizing and management of the v " incoming requests. The system designer simply connects each device's request lines to the PICU in the order of importance that he determines. The PICU monitors all ~-----1 , incoming requests, ascertains which has the highest ~ I/O IN) ~ priority, and issues a composite request to the CPU I " V:1_____ JI along with information that can help the CPU identify "\ '7 the requesting device. Such a priority interrupt control unit is the INTEL 8214 (see priority interrupt, Figure Figure 6. Interrupt method (courtesy of Intel Corporation, I). The latest semiconductor components that are Santa Clara, California). dedicated to managing interrupts are complex MaS/LSI devices that actually do a small amount of preprocessing the program would be devoted to managing this over­ of the requests. For example, the 8259 of Intel (Figure head and result in a decrease in system throughput. A 7) is an eight-level controller that is programmed by the more desirable method would be one that would allow system software to select from an array of service algo­ the microprocessor to be executing its main program rithms for more efficient interrupt management. With and only stop to service peripheral devices when it is complete software control of the algorithms by which told to do so by the device itself. In effect, the method the incoming requests are handled, the interrupt can be would provide an external, asynchronous input that changed dynamically as the total system environment informs the processor to complete whatever instruction changes.

\ ADDRESS BUS 1161 \

\ CQNTROLBUS \ tiNT REa i \ DATA BUS (8) \

-- -..,------I------f-- - -

r-- I

6258 8259 6258 f- SLAVE 2 P- SLAVE 1 MASTER P- Si' Si' SP G!ofl,lff" 20 19 18 17 16 15 ,. Gt 21 11 J1111 I WI!!!!!! I I I INTERRUPT REQUESTS

Figure 7. The 8259 eight-level controller (courtesy of Intel Corporation, Santa Clara, California). MICROCOMPUTER SYSTEM DESIGN 127

\ ADDR~SS IlUS (6) \ significant overhead, and the maintenance of multiple loops gets extremely complicated, especially in an A, AO interrupt-driven environment. The Intel 8253 is a single ) CONTROL BUS ---.J chip solution to most system timing problems (Figure 8). [I/OR I/OW In essence, it is a collection of three l o-bit counters that \ DATA BUS 181 1 are totally independent in nature but driven commonly .< ;. as I/O peripheral ports. Instead of setting up timing e loops in software, the programmer configures the 8253 ..( l-1 to match his requirements. The programmer initializes A, Ao CS °0·°, RD WR the 8253 with quantity of the count and desired mode 8253 then, upon command, the 8253 counts out the delay COUNTER COUNTER COUNTER 0 , 2 and interrupts the microprocessor when it has finished I I I r I I lOUT GATE CLK OUT GATE CLK lOUT GATE CLK I its tasks. It is easy to see that the software overhead is I minimal and that multiple delays can easily be main­ tained by assignment of interrupt levels to different 1 11 I I ! 11I counters. Other functions that can be accomplished with Figure 8. The 8253 system interface (courtesy of Intel the 8253 interval timer are nondelay in nature: baud Corporation. Santa Clara. California). rate generator, event counter, binary rate multiplier, and real-time clock. The 8253 represents a significant improvement for BK + 512 o BK solving one of the most common problems in system design and software generation.

SYSTEM MEMORY CONSIDERAnONS RAM ROM Generally, there are two types of memory storage: read only (ROM) and read/write (RAM). The ROMs pro­ vide for nonvolatile storage, so that the main program will not be lost when the system power is shut off. MEMORY MAP RAMs provide temporary storage for intermediate data Figure 9. Memory map (courtesy of Intel Corporation, and semipermanent storage for dynamically alterable Santa Clara, California). software. The interface of either type of storage to the LSIINTERVAt TIMER standard system bus is very similar to that of the I/O devices. It is best to view memory as groups of building One of the most common problems in microcom­ blocks all structured within the disciplines of the puter system design is interfacing to slow. delay­ standard system architecture. A simple memory "map" dependent peripherals devices such as: stepper motors, can be developed that shows the area of address space hammer relays. and other such mechanical devices. The that each type of memory occupies to further enhance system's software allows for such delays by program­ the simple. block approach of system design. (Refer to Figures 9 and 10.) ming timing loops. This type of programming requires ROM it4 I RAM "3 1 "2 1 '" 8111 8111 B316A CS3 '- CS2 I+- RIW 00 1101·4 AD-A7 RtW 00 1101-4 AO·A7 CSI 01-08 AD-A1D ..:: ':> ..:: ';> ..:: MEMW AD-A7 MEMW MEMR AD-A7 MEMR AD-AlD All- MEMV I A12 } ~ ), -< I DATA BUS IBI =0__0 [I~D_-----,n= CONTROL BUS (61 _------'ll II ADDRESS BUS (16) n=

Figure 10. Typical memory interface (courtesy of rntel Corporation. Santa Clara, California), 128 McKENZiE

CONCLUSION Advances in MOS/LSI technology will determine what the future of the microcomputer system will be. As The microcomputer has gained wide acceptance as a more complex peripheral components become available, practical tool for solving complex problems. To expand the microprocessor becomes simply a manager of the I/O the spectrum of applications, a total systems philosophy structure, and the real challenge is the imagination of the that allows for simple implementation, fast construction, system designer and programmer to create efficient solu­ and inherent reliability is a must. A logical structured tions to tomorrow's problems. approach to system design that relies on complete func­ tional definition and component implementation of the NOTE problem yields a cost-effective, reliable solution with 1. 8080 User's Manual, September 1975, Intel absolutely no sacrifice on performance. Corporation, Santa Clara, California 95053.