Micro Processors and Interfacing Devices
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Programmable Interrupt Controller
Programmable Interrupt Controller Dr. Wajiha Shah Outline • Explain how the x86 executes interrupts by using the interrupt vector table and interrupt routines. • List the differences between interrupts and CALL instructions. • Describe the differences between hardware and software interrupts. • Examine the ISR for any interrupt, given its interrupt number. • Describe the function of each pin of the 8259 programmable interrupt controller (PIC) chip. • Explain the purpose of each of the four control words of the 8259 and demonstrate how they are programmed. • Examine the interrupts in x86 PC1s. 8088/86 INTERRUPTS • An interrupt is an external event that informs the CPU that a device needs its service. – In 8088/86 there are a total of 256 interrupts. • INT 00, INT 01, ..., INT FF (sometimes called TYPEs). • When an interrupt is executed the processor: – Saves the flag register (FR), instruction pointer (IP), and code segment register (CS) on the stack,. – Goes to a fixed memory location. • In x86, always four times the value of the interrupt number. 8088/86 INTERRUPTS interrupt service routine (ISR) 1. When an interrupt is invoked it is asked to run a program to perform a certain service. 2. There must be a program associated with every interrupt . 3. This program is commonly referred to as an interrupt service routine (ISR), and also called the interrupt handler. 4. When an interrupt is invoked, the CPU runs the interrupt service routine. 8088/86 INTERRUPTS interrupt service routine (ISR) – For every interrupt there are allocated four bytes of memory in the interrupt vector table. – Two bytes for the IP. – Two for the CS of the ISR. -
16-Bit MS-DOS Programming (MS-DOS & BIOS-Level Programming )
Microprocessors (0630371) Fall 2010/2011 – Lecture Notes # 20 16-Bit MS-DOS Programming (MS-DOS & BIOS-level Programming ) Objectives Real-Address Mode MS-DOS Memory Organization MS-DOS Memory Map Interrupts Mechanism—Introduction Interrupts Mechanism — Steps Types of Interrupts 8086/8088 Pinout Diagrams Redirecting Input-Output INT Instruction Interrupt Vectoring Process Common Interrupts Real-Address Mode Real-address mode (16-bit mode) programs have the following characteristics: o Max 1 megabyte addressable RAM o Single tasking o No memory boundary protection o Offsets are 16 bits IBM PC-DOS: first Real-address OS for IBM-PC Later renamed to MS-DOS, owned by Microsoft MS-DOS Memory Organization Interrupt Vector Table BIOS & DOS data Software BIOS MS-DOS kernel Resident command processor Transient programs Video graphics & text Reserved (device controllers) ROM BIOS MS-DOS Memory Map Address FFFFF R O M BIO S F0000 Reserved C0000 Video Text & Graphics B8000 V R A M Video Graphics A0000 Transient Command Processor Transient Program Area (available for application programs) Resident Command Processor 640K R A M DOS Kernel, Device Drivers Software BIOS BIOS & DOS Data 00400 Interrupt Vector Table 00000 Interrupt Mechanism—Introduction Devices such as the keyboard, the monitor, hard disks etc. can cause such interrupts, when they require service of some kind, such as to get or receive a byte. For example, when you press a key on the keyboard this causes an interrupt. When the Microprocessor is interrupted, it completes the current instruction, and then pushes onto the stack the flags register plus the address of the next instruction (the return address). -
8259 Programmable Interrupt Controller
edge of each clock pulse. When the counter reaches zero, the OUT goes low and the counter is reloaded with the full count and the whole process is repeated. 3) In this way, if the count is odd, the output will be high for (n+1)/2 counts and low for (n-1)/2 count MODE 4 : Software Triggered Strobe In this mode , the OUT is high; It goes low for one clock period at the end of the count. The count must be loaded subsequently outputs MODE 5 : Hardware triggered strobe (Retriggerable). Initially, the out is low, and when the gate pulse is triggered from low to high, The count begins. At the end of count, the OUT goes low for one clock period. 8259 programmable interrupt controller 8259 is Programmable Interrupt Controller (PIC) It is a tool for managing the interrupt requests. 8259 is a very flexible peripheral controller chip: PIC can deal with up to 64 interrupt inputs interrupts can be masked various priority schemes can also programmed. There are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But by connecting 8259 with CPU, we can increase the interrupt handling capability. 8259 combines the multi interrupt input sources into a single interrupt output. Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For example, Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085 microprocessor from 5 to 8 interrupt levels. Features of 8259 PIC microprocessor – 1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor. 2. -
Computers Shouldn't Be Limitations Advertising & Distribution a Handicap Is a Limitation
.. No. 48 July-August 1989 $3.95 T HE MICRO TECHN I CAL J 0 URN A L Tools For The Physically Impaired What's important to people who have handicaps? We asked them. (Their responses may surprise you.) The Adventure Begins page 8 Dallas Vordahl demonstrates what you can do with a computer, a mouthstick, and a very limited amount of head motion. Writing Software For page 16 The Blind Don' t exclude the blind from your next software package. File Transfer Via The page 20 Parallel Port The LIMBO Project page 28 Build a maze-running robot. And More ... Debugging A Processor page 44 Growing Your Own page 66 Software Business Great SOGs page 83 And Much, Much, More 07 a 7447019388 3 U[J!]£?[jj) J/@[J!]£? !fJ©llfU/5Ju O[jj)(]@ (j] /JJ@r:'.JQ£?fj[J!]O /LfI1@@£?(JJ(]@£?J/ (j][jj)@ @[jj)@]O[jj)QQ£?O[jj)@] (]@@ODDD Introducing ... The PC-LabCard Family Only from HSC Electronic Supply Digital 1/0 and Prototype Development IBM PC/XT/AT and it's Counter Card compatible models are moving into Card Industrial/Laboratory applications at • 32 Digital Input Channels • Large breadboard area (3290 holes) - TTL compatible an increasing rate. The reasons for • Independent memory and I/O address - Low loading: 0.2 rnA at O.4V input this include their price/performance decoders built-in • 32 Digital Output Channels ratio and short user learning curve. • Memory and I/O ports are jumper - TTL compatible PC-based data acquisition boards selectable - Driving capacity: Sink 24 rnA, are now taking the place of the • All bus signals are buffered, marked, source 15 rnA and ready for use • Intel 8253 Timer/Counter traditional data loggers or recorders - 3 channels of timer/counter which cost several times more. -
Atmega328p Xplained Mini User Guide
USER GUIDE ATmega328P Xplained Mini User Guide Introduction This user guide describes how to get started with the Atmel® ATmega328P Xplained Mini board. The ATmega328P Xplained Mini evalutation kit is a hardware platform to evaluate the Atmel ATmega328P microcontroller. The evaluation kit comes with a fully integrated debugger that provides seamless integration with Atmel Studio 6.2 (and later version). The kit provides access to the features of the ATmega328P enabling easy integration of the device in a custom design. 42287A-MCU-05/2014 Table of Contents Introduction .................................................................................... 1 1. Getting Started ........................................................................ 3 1.1. Features .............................................................................. 3 1.2. Design Documentation and Related Links .................................. 3 1.3. Board Assembly .................................................................... 3 1.3.1. In Customer Development Assembly ............................. 3 1.3.2. Connecting an Arduino Shield ..................................... 3 1.3.3. Standalone Node ...................................................... 3 1.4. Connecting the Kit ................................................................. 3 1.4.1. Connect the Kit to Atmel Studio ................................... 3 1.4.2. Connect the Target UART to the mEBDG COM Port ......... 3 1.5. Programming and Debugging ................................................. -
Intel 8255 - Wikipedia, the Free Encyclopedia
Intel 8255 - Wikipedia, the free encyclopedia http://en.wikipedia.org/wiki/Intel_8255 Intel 8255 From Wikipedia, the free encyclopedia The Intel 8255 (or i8255 ) Programmable Peripheral Interface ( PPI ) chip is a peripheral chip originally developed for the Intel 8085 microprocessor, [1] and as such is a member of a large array of such chips, known as the MCS-85 Family . This chip was later also used with the Intel 8086 and its descendants. It was later made (cloned) by many Intel D8255 other manufacturers. It is made in DIP 40 and PLCC 44 pins encapsulated versions. [2] Contents 1 Similar chips 2 Uses in computers 3 Functional block of 8255 4 Operational modes of 8255 5 Bit set/reset (BSR) mode 6 Input/Output mode 6.1 Control Word Format 6.2 Mode 0 - simple I/O 6.2.1 Mode 1 – input mode 6.2.2 Mode 0 - output mode 6.3 Mode 1 6.4 Mode 2 Pinout of i8255 7 References 8 External links Similar chips The 8255 is used to give the CPU access to programmable parallel I/O,[3] and is similar to other such chips like the MOS Technology 6522 (Versatile Interface Adapter) and the MOS Technology CIA (Complex Interface Adapter) all developed for the 6502 family. Other such chips are the 2655 Programmable Peripheral Interface from the Signetics 2650 family of microprocessors, the Motorola 6820 PIA (Peripheral Interface Adapter) from the Motorola 6800 family, the Western Design Center WDC 65C21, an enhanced 6520, and many others. However, most often the functionality 8255 offered is now not implemented with the 8255 chip itself any more, but is embedded in a larger VLSI chip as a subfunction. -
Getting Started with STK200 Dragon Introduction This Guide Is Designed to Get You up and Running with Main Software and Hardware
Getting Started with STK200 Dragon Introduction This guide is designed to get you up and running with main software and hardware. As you work through it, there could be lots of details you do not understand, but these are covered in books and other documentation that you can read later. The main software package is AVRStudio, which is Atmel’s Integrated Development Environment or IDE. There is also a plugin C Compiler module called WinAVR that compiles C programs within AVRStudio. The Kanda installer will install these packages and copy documentation to a folder on your hard drive. Default install path is C:\Program Files\STK200 Dragon AVRStudio has its own Atmel-AVR Tools folder in Program Files, and can be run from there or you can run from desktop icon. WinAVR never needs to be run directly, only from AVRStudio. The AVRStudio IDE is designed for writing source code, in C (.c files) or assembler (.asm files). These are then built or compiled into object code (.hex files) for programming into the AVR using ISP or debug files (.elf files) to step through the code. The AVR Dragon hardware is a programmer and In Circuit Emulator (ICE) in one tool. Once source code is built, it can be programmed into the AVR using ISP, which will just run the code or it can be set in Debug mode (using DebugWire or JTAG )that allows you to examine the code operation to find bugs. There are two Debug methods depending on the AVR device you are using • JTAG Mode for AVR devices with 40-pins or more • DebugWire for smaller pin-count devices. -
Power Debugger [USER GUIDE] 2 Atmel-42696D-Power-Debugger User Guide-10/2016 5.2.5
Programmers and Debuggers Power Debugger USER GUIDE Atmel-42696D-Power-Debugger_User Guide-10/2016 Table of Contents 1. The Atmel Power Debugger...................................................................................... 4 1.1. Kit Contents..................................................................................................................................5 2. Getting Started with the Power Debugger................................................................. 6 3. Connecting the Power Debugger...............................................................................8 3.1. Connecting to AVR and SAM Target Devices...............................................................................8 4. Detailed Use Cases.................................................................................................10 4.1. Low-power Application............................................................................................................... 10 4.1.1. Requirements.............................................................................................................. 10 4.1.2. Initial Hardware Setup................................................................................................. 10 4.1.3. Connections.................................................................................................................12 4.1.4. Disabling the debugWIRE Interface.............................................................................13 4.1.5. Disabling On-board Power Supply on the Xplained -
The Programmable Interrupt Controller
The Programmable Interrupt Controller SYSC-3006 Interrupt Controller • Before : The 8086 processor has two hardware interrupt signals • We’ve seen at least 2 interrupt sources. 8086 Timer Keyboard NMI INTR (INT 8) (INT 9) bus • “Decides from which vector table location to load ISR address” SYSC-3006 Interrupt Vectors: Deciding which ISR to run • Auto-vectored interrupts: vector predefined as part of CPU design – For each HW signal, CPU goes to a particular interrupt-type in vector table. – 8086 Example: NMI (auto-vectored -> Interrupt-type 2) • NMI asserted, 8086 executes INT type 2 interrupt behaviour: – save processor state – obtain ISR address from vector 2 (memory address 0:8) – execute type 2 ISR • More than one device shares the NMI signal? (e.g. RAM and power supply) – NMI ISR must check (poll) each device (which one caused the interrupt?) SYSC-3006 Interrupt Vectors: Deciding which ISR to run • Vectored interrupts: vector determined during systems design. – CPU performs “interrupt-acknowledge” cycle -> reads interrupt-type from data bus • Interrupting device can provide interrupt-type • 8086: interrupt controller (IC) External hardware – Vectored interrupts: robust method for multiple devices connected to single interrupt line (no polling!) • Interrupt-type: mapping to unique ISR for each device • Interrupt controller acts as a multiplexer – 8086 Example: INTR is a vectored interrupt SYSC-3006 Interrupt Controller • Interrupt controller acts as a funnel for multiple device interrupts – Allows many devices to share the 8086’s single -
And PC 750 (Type 6887)
Technical Information Manual PC 730 (Type 6877) and PC 750 (Type 6887) Technical Information Manual IBM PC 730 (Type 6877) and PC 750 (Type 6887) Note Before using this information and the product it supports, be sure to read the general information under Appendix B, “Notices and Trademarks” on page 65. First Edition (June 1996) The following paragraph does not apply to the United Kingdom or any country where such provisions are inconsistent with local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS PUBLICATION “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer of express or implied warranties in certain transactions, therefore, this statement may not apply to you. This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time. It is possible that this publication may contain reference to, or information about, IBM products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that IBM intends to announce such IBM products, programming, or services in your country. Requests for technical information about IBM products should be made to your IBM reseller or IBM marketing representative. IBM may have patents or pending patent applications covering subject matter in this document. -
8253/8253·5 Programmable Interval Timer
TABLE OF CONTENTS HOW TO CONFIGURE YOUR SYSTEM SUPPORT 1 IN UNDER 5 MINUTES, WITHOUT READING THE MANUAL • • •• 5 Other options and jumpers ••••• 6 Important note about system memory 6 ABOUT SYSTEM SUPPORT 7 Technical overview • 7 CONFIGURING THE SYSTEM SUPPORT 1 9 Setting I/O address 9 Setting memory address •• 10 Other memory options • • • • • • • • • 11 Disabling the memory • • 11 Global/extended address selection 11 Phantom* response options •••• 12 Battery back-up for CMOS RAM • • 12 Wait states ••••••••••• 12 Using higher speed 9511A or 9512 • 13 Interrupt jumpers and options 13 Using a 9511 or 9512 with interrupts 15 Interval timer options • • • • • • • 15 Configuring the serial channel • • • • 16 Other miscellaneous hardware options 17 Connecting the battery • • • • 18 Mounting the battery holder 18 Replacing the battery • • • • • 18 I/O port map • • • • • • • • 19 PROGRAMMING CONSIDERATIONS FOR THE SYSTEM SUPPORT 1 20 Power-up initialization • • • • 20 Programming the serial channel 20 UART initialization • • • • • • • • • • 25 Sample UART program • • • • • 25 Programming the real time clock • • • • 26 Clock programming sequence • • • • 28 Sample clock program • • • • • • • • • • 29 Programming the interrupt controllers 35 Important note about using DDT to debug interrupts 35 "INTEL 8259A Programmable Interrupt Controller". 36 Initializing the 8259A • • • • • • • • • • • 56 Routine for initializing master/slave 8259As 56 Disabling the 8259As •••••••••••• 57 Programming the interval timer. • • • • • • •••• 58 "INTEL 8253/8253-5 -
15 Pecision System Clock Architecture
Pecision System Clock Architecture 15 Pecision System Clock Architecture “Time iz like money, the less we hav ov it teu spare the further we make it go.” Josh Billing Encyclopedia and Proverbial Philosophy of Wit and Humor, 1874 225 Pecision System Clock Architecture Limitations of the Art Over the almost three decades that NTP has evolved, accuracy expectations have improved from 100 ms to less than 1 ms on fast LANs with multiple segments interconnected by switches and less than a few milliseconds on most campus and corporate networks with multiple subnets interconnected by routers. Today the practical expectations with a GPS receiver, PPS signal and precision kernel support are a few microseconds. In principle the ultimate expectations are limited only by the 232-ps resolution of the NTP timestamp format or about the time light travels three inches. Improving accuracy expectations below the PPS regime is proving intricate and tricky. In this chapter we turn to the most ambitious means available to minimize errors in the face of hardware and software not designed for extraordinary timekeeping. First we examine the hardware and software components for a precision system clock and evolve an optimal design. Next we survey timestamping techniques using both hardware, driver and software methods to minimize errors due to media, device and operating system latencies. Finally, we explore the IEEE 1588 Precision Time Protocol (PTP), how it is used in a high speed LAN, and how it and NTP can sail in the same boat. The parting shots section proposes a hardware assisted design which provides performance equivalent to PTP with only minimal modifications to the Unix operating system kernel.