8259 Programmable Interrupt Controller

edge of each clock pulse. When the counter reaches zero, the OUT goes low and the counter is reloaded with the full count and the whole process is repeated. 3) In this way, if the count is odd, the output will be high for (n+1)/2 counts and low for (n-1)/2 count MODE 4 : Software Triggered Strobe In this mode , the OUT is high; It goes low for one clock period at the end of the count. The count must be loaded subsequently outputs MODE 5 : Hardware triggered strobe (Retriggerable). Initially, the out is low, and when the gate pulse is triggered from low to high, The count begins. At the end of count, the OUT goes low for one clock period. 8259 programmable interrupt controller 8259 is Programmable Interrupt Controller (PIC) It is a tool for managing the interrupt requests. 8259 is a very flexible peripheral controller chip: PIC can deal with up to 64 interrupt inputs interrupts can be masked various priority schemes can also programmed. There are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But by connecting 8259 with CPU, we can increase the interrupt handling capability. 8259 combines the multi interrupt input sources into a single interrupt output. Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For example, Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085 microprocessor from 5 to 8 interrupt levels. Features of 8259 PIC microprocessor – 1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor. 2. It can be programmed either in level triggered or in edge triggered interrupt level. 3. We can masked individual bits of interrupt request register. 4. We can increase interrupt handling capability up to 64 interrupt level by cascading further 8259 PIC. 5. Clock cycle is not required. Table 1. Pin Description Symbol Pin No. Type Name and Function VCC 28 I SUPPLY: + 5V Supply. GND 14 I GROUND CS 1 I CHIP SELECT: A low on this pin enables RD and WR communication between the CPU and the 8259A. INTA functions are independent of CS. WR 2 I WRITE: A low on this pin when CS is low enables The 8259A to accept command words from the CPU. RD 3 I READ: A low on this pin when CS is low enables the 8259A to release status onto the data bus for the CPU. D7–D0 4 –11 I/O BIDIRECTIONAL DATA BUS: Control, status and interrupt-vector information is transferred via this bus. CAS0–CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 8259A bus to control a multiple 8259A structure. These pins are outputs for a master 8259A and Inputs slave 8259A. SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a Dual function pin. When in the Buffered Mode it can used as an output to control buffer transceivers (EN). When not in the buffered mode it is used as an input to designate a master (SP e 1) or slave (SP e 0). INT 17 O INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU, thus it is connected to the CPU’s interrupt pin. IR0–IR7 18 –25 I INTERRUPT REQUESTS: Asynchronous inputs. an interrupt request is executed by raising an IR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high level on an IR input (Level Triggered Mode). INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A interrupt-vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the CPU. A0 27 I A0 ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 8259A to decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically connected to the CPU A0 address line (A1 for 8086, 8088). The internal block diagram of the 8259 includes eight block I. Control Logic II. Read/Write Logic III. Data Bus Buffer IV. Three Registers IRR, ISR, and IMR V. Priority Resolver and VI. Cascade Buffer Read/Write Logic When the address line A0 is at logic 0, the controller is selected to write a command or read a status. Control Logic This block has two pins INT (interrupt) as an output, INTA(Interrupt Acknowledge ) as an input. The INT is connected to the interrupt pin of the µP. Whenever a valid interrupt is asserted, this signal goes high. The INTA is the Interrupt Acknowledge signal from the µP. Interrupt Registers and Priority Resolver The Interrupt Request Register (IRR) has eight input lines (IR0-IR7 ) for interrupts. When these lines go high, the requests are stored in the register The In-Service Register (ISR) stores all the levels that are currently being serviced, and the Interrupt Mask Register (IMR) stores the masking bits of the interrupt lines to be masked The Priority Resolver (PR) examines these three registers and determines whether INT should be sent to the µP Cascade Buffer/Comparator This block is used to expand the number of interrupt levels by cascading two or more 8259s Interrupt Operation To implement interrupts, the Interrupt Enable flip-flop in the µP should be enabled by writing the EI instruction, and the 8259 requires two types of control words; Initialization Command Words (ICWs) and Operational Command Words (OCWs) ICWs: ICWs are used to set up the proper conditions and specify RST vector addresses. OCWs: OCWs are used to perform functions such as masking interrupts, setting up status-read operations, etc. After the initialization, the following sequence of events occurs when one or more interrupt request lines go high. I. The IRR stores the requests II. The priority resolver resloves the priority and sets the INT high when appropriate III. The processor acknowledges the interrupt by sending IV. After the is received, the appropriate priority bit in the ISR is set to indicate which interrupt level is being serviced, and the corresponding bit in the IRR is reset to indicate that the request is accepted. Then, the opcode for the CALL instruction is placed on the data bus V. When the processor decodes the CALL instruction, it places two more signal on the Data bus. VI. When the 8259 receives the second , it places the low order byte of the CALL address on the data bus. At the third , it places the high-order byte on the data bus. CALL address is the vector memory location for the interrupt; this is placed in the control register during the initialization. VII. During the 3rd pulse, the ISR bit is reset VIII. The program sequence is transferred to the memory location specified by the CALL Programming the 8259 The 8259 requires two types of command words, Initialization Command Words (ICWs) and Operational Command Words (OCWs) The 8259 can be initialized with four ICWs; the first two are essential, and the other two are optional based on the modes being used These words must be issued in a given sequence Once initialized, the 8259 can be set up to operate in various modes by using three different OCWs; however, they no longer need be issued in a specific sequence The ICW1 specifies; single or multiple 8259s in the system 4-or 8-bit interval between the interrupt vector location The address bits A7-A5 of the CALL instructions; the rest are supplied by the 8259 .

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