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Introduction to 8259(Interrupt Controller)

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Introduction to 8259(Interrupt Controller) INTRODUCTION TO 8259(INTERRUPT CONTROLLER) The Intel 8259 is a Programmable Interrupt Controllers (PIC) designed and developed to work with the Intel 8085 and Intel 8086 microprocessors. The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single interrupt output to interrupt a microprocessor. The Programmable Interrupt Controller (PIC) functions as an overall manager in an Interrupt-Driven system environment. Most of the microprocessors have limited number of interrupt lines to accept interrupt (For e.g. Intel 8085 has 5 interrupt input pins). Therefore it is not possible for the microprocessor to handle interrupts by several I/O devices. When the number of I/O devices is more than the number of Interrupt lines of the microprocessor, such controllers are required. 8259 is used when several I/O devices need to transfer data using interrupt and they are to be connected to the same interrupt line of the microprocessor. It accepts requests from the peripheral devices, resolve their priority to entertain the peripheral with highest priority and issues an interrupt to the CPU based on this determination. FEATURES OF 8259 It is a LSI chip enclosed with 28 pins DIP (Dual in line package). It uses NMOS technology and requires a single +5V DC power supply. It can accept 8 interrupt requests (IRQ) simultaneously. All these 8 interrupts are vectored priority interrupts. It has internal priority resolver to determine the interrupts priority. It can be cascaded in master-slave configuration to get 64 levels of interrupts. The 8259 is designed to minimize the software and real time overhead in handling multi-level priority interrupts. No clock Signal required. It can be operated on fixed priority mode and rotating priority mode. A Special register called Interrupt Mask Register (IMR) can individually mask the interrupt requests. Modes and masks can be changed dynamically. In 8085 mode, it provides 3 byte CALL instruction. In 8086 mode, it provides 8 bit vector number. It can be used in Polled and Vectored mode. Starting address of ISR or vector number is programmable. INTERNAL ARCHITECTURE OF 8259 The internal block diagram of 8259 PIC is as shown in Fig.8.4. It consists of eight functional blocks: (1) Data bus buffer (2) Control logic (3) Interrupt Request Register (IRR) (4) In-Service Register (5) Interrupt Mask register (6) Priority resolver (7) Read/Write logic (8) Cascade buffer. Fig.8.4 8259 Block Diagram The functional blocks of 8259 are discussed in detail below: Interrupt Request Register (IRR) Eight interrupt lines IR0-IR7 are connected to the interrupt request register (IRR). The IRR stores all the interrupt levels (set or reset) which are requesting service through any one of the 8 IRQ lines (IRQ0-IRQ7). It keeps the information about the interrupt inputs that have requested for interrupt services. Every bit in IRR corresponds to one of the lines IRQ0-IRQ7. The device requesting for the service via one of the eight pins IR0-IR7 setting it to a high level. The 8259 then set the corresponding bit in IRR. In-Service Register (ISR) It is used to store all the interrupt levels that are currently being serviced. The priority resolver determines the priority of the bit set in the IRR. The bits corresponding to the interrupt of the highest priority is selected. The information about the interrupt input of the selected interrupt is stored in ISR. On the receipt of INTA signal from the CPU, the highest priority ISR bit is set and the corresponding IRR bit is reset. Interrupt Mask Register (IMR) It is used to store the mask bits of the interrupt lines that are required to be masked. It contains a specific bit for each interrupt line. It is used to mask or unmask individual interrupt input. The priority resolver directs the IMR to operate on IRR. An interrupt input can be masked by setting the corresponding bit to 1 in IMR. An interrupt which is masked by software (by programming IMR) is not recognized and serviced even if the corresponding bit is set in the IRR. Priority Resolver This logic block determines the priorities of the interrupts when more than one I/O device request for the interrupt. On the receipt of INTA signal from the CPU, the priority resolver select the interrupt line of highest priority, set the corresponding bit in ISR. By default the priority resolver work in fixed priority mode. In this mode the IRQ0 has the highest priority while the IRQ7 has lowest. Read/Write Control Logic All the commands from the CPU are accepted through this block; it also allows the status of the 8259 to be transferred onto the data bus. Data Bus Buffer This 8-bit Bidirectional buffer is used to interface the 8259 to the System data Bus. All the control words and status information between 8259 and microprocessor are transferred through this buffer. Interrupt Control Logic This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt acknowledge (INTA) signal from CPU that causes the 8259 to release vector address on to the data bus. The Cascade Buffer/Comparator This function block stores and compares the IDs of all 8259's used in the master/slave cascaded system. When 8259 is used as a master, the associated cascaded I/O pins (CAS0-CAS2) act as an output pins, and these pins are input pins when 8259 is used as slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS0±2 lines to select one of the slaves. The selected slave sends its preprogrammed subroutine address onto the data bus during the next one or two consecutive INTA pulses..
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