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Interruptverarbeitung in Betriebssystemen Interruptverarbeitung in Betriebssystemen Sommersemester 2015 Prof. Dr. Peter Mandl Prof. Dr. Peter Mandl Seite 1 Gesamtüberblick 1. Einführung in Computersysteme 2. Entwicklung von Betriebssystemen 3. Architekturansätze 4. Interruptverarbeitung in Betriebssystemen 5. Prozesse und Threads 6. CPU-Scheduling 7. Synchronisation und Kommunikation Interruptklassen 8. Speicherverwaltung 9. Geräte- und Dateiverwaltung Asynchrone Interrupts Synchrone Interrupts (nicht vorhersehbar und auch (vorhersehbar und auch 10. Betriebssystemvirtualisierung nicht reproduzierbar) reproduzierbar) Exceptions Systemcalls (Software-Interrupts) Unterbrechung vor der Ausführung, Faults z. B. Page Fault = Seitenfehler Unterbrechung vor der Ausführung, Traps z. B. Division durch 0 Prof. Dr. Peter Mandl Seite 2 Zielsetzung . Konzepte und Abläufe der Interruptverarbeitung in Betriebssystemen kennenlernen und verstehen . Unterscheidung der verschiedenen Interrupt- Klassen vornehmen können . Ablauf eines asynchronen Interrupts erläutern können . Ablauf eines (synchronen) Systemcalls erläutern können Prof. Dr. Peter Mandl Seite 3 Überblick 1. Begriffe und Klassifizierung 2. Zusammenspiel der Komponenten 3. Systemdienste und Systemcalls Prof. Dr. Peter Mandl Seite 4 Polling Polling => Busy Waiting (aktives Warten) Gerät 1 while() { Ready-Bit for (alle Geräte) { if (Gerät[i].Ready-Bit == 1 ) { CPU Gerät 2 doAction(); Ready-Bit } … } } Gerät n Ready-Bit = 1 bedeutet, Gerät ist bereit, es sind Ready-Bit z.B. Daten abzuholen Prof. Dr. Peter Mandl Seite 5 Interrupt Interrupt = Unterbrechung = Trap Abgrenzung zu Polling - Kein aktives Abfragen von Ereignisquellen Gründe für Interrupts: - Betriebssystembedingungen - Asynchrone Ereignisse Verursacher: Hardware oder Software Abschaltung (Maskierung) von Interrupts ist möglich, sollte aber für sehr kurze Zeit sein Manchmal unbedingt erforderlich (siehe später Interrupt Service Routinen) Prof. Dr. Peter Mandl Seite 6 Synchron und asynchron Synchrone Interrupts: Von der CPU ausgelöste Ausnahmen (für das laufende Programm gedacht) - Division durch 0 - Speicherzugriffsverletzung Asynchrone Interrupts: Treten unabhängig davon auf, was das System gerade ausführt - Netzwerkadapter meldet ankommende Nachricht - Plattenspeicher meldet Zustellung eines Blocks Prof. Dr. Peter Mandl Seite 7 Interrupt-Klassifizierung Interruptklassen Asynchrone Interrupts Synchrone Interrupts (nicht vorhersehbar und auch (vorhersehbar und auch nicht reproduzierbar) reproduzierbar) Systemcalls Exceptions (auch als Traps oder Software- Interrupts bezeichnet) Faults Unterbrechung vor der Ausführung, z.B. Page Fault = Seitenfehler Unterbrechung nach der Ausführung, Traps z.B. Division durch 0 Prof. Dr. Peter Mandl Seite 8 Überblick 1. Begriffe und Klassifizierung 2. Zusammenspiel der Komponenten 3. Systemdienste und Systemcalls Prof. Dr. Peter Mandl Seite 9 Interrupt-Bearbeitung: Zusammenspiel Interrupts führen dazu, dass Code außerhalb des normalen Programmflusses ausgeführt wird Steuerung wird an eine definierte Position im Kernel übergeben Interrupt-Service- Routine (ISR) 1: Gerät ist fertig Interrupt Festplatte 2: Interrupt Controller Clock CPU 3: CPU-Handling Tastatur Drucker Bus Prof. Dr. Peter Mandl Seite 10 Interrupt-Bearbeitung: Befehlszyklus Prüfung, ob Interrupt anliegt, ist Teil des Befehlszyklus Prüfung am Ende eines Maschinenbefehls Fetch (Befehl aus Speicher holen) Execute (Befehl ausführen) Prüfung, ob Interrupt vorliegt Bei Multiprozessoren bzw. Mehrkernprozessoren: nein IRQ ja Dispatching eines Prozessors/Kerns Programmzähler notwendig, um anstehenden Interrupt auf Startadresse der ISR setzen zu bearbeiten Prof. Dr. Peter Mandl Seite 11 Interrupt-Vektor-Tabelle und Adressierung Interrupt Request (IRQ) wird vom Gerät gesendet und identifiziert das Gerät Abbildung IRQ Int-Nr durch Hardware in einem Interrupt Controller Int-Nr ist der Index für die Interrupt-Vektor-Tabelle (IVT) Die IVT wird über die CPU adressiert IVT-Aufbau durch Prozessor vorgegeben: Bei Intel 256 IVT-Einträge für Exceptions, Systemcalls (Traps) und Geräteinterrupts IVT IRQInt-Nr 0 Interruptvektor 1 Interruptvektor SVR 0 2 3 SVR 1 … Prof. Dr. Peter Mandl Seite 12 Interrupt-Service-Routine (ISR) Interrupt Anwendungsprogramm 1: Interrupt Usermodus Controller 2: Ack Verteiler (Interrupt-Bearbeitung) 3: 4: Interrupt-Vektor- 5: - E/A-Geräte benachrichtigen die Tabelle CPU, wenn sie einen Dienst Kernelmodus 01 ISR1 02 benötigen 03 ISR2 ISR3 - Dadurch kann die CPU maximal n ausgenutzt werden, da sie parallel zur Ein-/Ausgabe etwas anderes ISRn machen kann Adressraum ISR = Interrupt Service Routine Prof. Dr. Peter Mandl Seite 13 Interrupt-Bearbeitung: Ablauf Beliebiges ISR Programm Normale Programmbearbeitung Zeitpunkt des Interrupt Laufender Maschinenbefehl wird noch zu Ende geführt. Registersatz wird auf den Stack gerettet. Adressierung über Interrupt- Vektortabelle Niedriger priorisierte Inter- rupts werden deaktiviert. ... Alten Zustand wieder- Rückkehr Normale Programmbearbeitung herstellen (Register,...). fortsetzen Prof. Dr. Peter Mandl Seite 14 Beispiel: Intel 8259A-Controller Intel 8259A PIC = Programmable Controller = Multiplexer für Hardware-Interrupts - Ein integrierter Schaltkreis zur Verwaltung mehrerer Hardware- Interrupts - Aufgabe: Überwacht Interrupt-Leitungen (IRQ), speichert sie und gibt sie an die CPUs weiter - 8 Interrupt-Eingänge: Eingang 0 hat höchste Priorität - Seit IBM PC XT eingesetzt - Oft wurden zwei PICs in einem PC genutzt Neuere Versionen - APIC = Advanced PIC mit 256 Interrupt-Eingängen wird bei x86- Architekturen eingesetzt - SAPIC = Streamlined Advanced Programmable Interrupt Controller wird bei IA64-Architekturen eingesetzt Prof. Dr. Peter Mandl Seite 15 Gerät - Interrupt-Controller - CPU - Betriebssystem Übertragung der Interrupt-Request-Nummer, Mapping IRQ Int-Nr. IRQ 0 Gerät 1 D0-D7 Interrupt- Handling IRQ 1 Betriebs- Gerät 2 CPU 8259A system ... INT IRQ 7 Gerät 8 INTA Prof. Dr. Peter Mandl Seite 16 Beispiel: Intel 8259A-Controller Innenleben Intel 8259A, vereinfacht 8259A Interrupt- IRQ0-7 D0-D7 In-Service- Daten- Request- Register (ISR) bus- Register(IRR) Puffer CPU Interrupt-Masken- Register (IMR) INTR Steuerlogik INTA Prof. Dr. Peter Mandl Seite 17 Beispiel: Intel 8259A-Controller kaskadiert CPU INTA (Bearbeitung durch CPU bestätigt) IRQ 0 0 timer output 1 keyboard CPU 08 real time clock 09 s/w - int a0h IRQ 2 D0 – D7 10 reserved Intel 8259 Intel 8259 11 reserved (Adressierung des Interrupts) Master Slave 12 PS/2 mouse 13 coprocessor CPU INTR 14 hard disk IMR 15 reserved 03 serial 2 04 serial 1 05 parallel 2 INTA = Interrrupt Acknowledge INTR = Interruptmeldung an CPU 06 floppy IMR = Interrupt Mask Register 07 parallel 1 IRQ = Interrupt Request PIC = Programmable Interrupt Controller APIC = Advanced PIC Prof. Dr. Peter Mandl Seite 18 Interrupt-Dispatching bei Mehrkernprozessoren Dispatching-Algorithmus im Interrupt-Dispatcher wählt einen Kern aus, der den Interrupt bearbeiten soll Kommunikationssystem Local APIC Kern 1 Local APIC Kern 2 Interrupt Interrupt Dispatcher Interrupts (z.B. I/O-APIC Controller … im Chipsatz) Local APIC Kern n Mehrkernprozessor Prof. Dr. Peter Mandl Seite 19 Fallbeispiel: Windows, Interrupt-Bearbeitung (1) Interrupt-Service-Routinen Asynchrone Interrupts Ausnahme- Ausnahme- Hardware-Interrupt InHtearrnudplet-rService- Handler E/A-Geräte, Taktgeber Routine Synchrone Interrupts Ausnahme- Ausnahme- Systemcall Handler SyHsatenmdldeirenste Ausnahme- Ausnahme- Exceptions (Traps, Abort) Ausnahmen HAaunsdnlearhme- verteiler Handler Busfehler, Stromausfall, Handler Division durch 0,... Seitenfehler- Page Faults Handler Prof. Dr. Peter Mandl Seite 20 Fallbeispiel: Windows, Interrupt-Bearbeitung (2) Windows hat eine eigene Interrupt-Verwaltung Über sog. Interrupt Request Levels (IRQL) ordnet der Kernel den Interrupts eigene Prioritäten zu Nur Interrupts mit höherem IRQL können Interruptbearbeitung auf niedrigerem IRQL unterbrechen Über eine Interrupt Dispatch Tabelle (IDT) wird festgehalten, welche ISR für welchen Interrupt zuständig ist Prof. Dr. Peter Mandl Seite 21 Fallbeispiel: Windows, Interrupt-Bearbeitung (3) Interrupt Request Levels (IRQLs) in der IA32- Architektur IRQL Bezeichnung Beschreibung 31 High-Level Maschinen-Check und katastrophale Fehler 30 Power-Level Strom/Spannungsproblem 29 IPI-Level Interprocessor Interrupt 28 Clock-Level Clock-Interrupt 27 Sync-Level Prozessorübergreifende Synchronisation 3-26 Device-Levels Abbildung auf IRQs der Geräte je nach verbautem Interrupt-Controller 2 Dispatch/DPC-Level Dispatching und Ausführung von Deferred Procedure Calls 1 APC-Level Ausführung von Asynchronous Procedure Calls nach Ein-/Ausgabe-Requests 0 Passive-Level Normale Threadausführung Prof. Dr. Peter Mandl Seite 22 Fallbeispiel: Windows, Interrupt-Bearbeitung (4) Interrupt Request Levels (IRQLs) in der x64- und der IA64-Architektur IRQL Bezeichnung Beschreibung 15 High-Level Maschinen-Check und katastrophale Fehler 14 Power-Level Strom/Spannungsproblem und Interprozessor-Interrupt 13 Clock-Level Clock-Interrupt 12 Synch-Level Prozessorübergreifende Synchronisation 3-11 Device-Levels Abbildung auf IRQs der Geräte je nach verbautem Interrupt-Controller 2 Dispatch/DPC-Level Dispatching und Ausführung von Deferred Procedure Calls 1 APC-Level Ausführung von Asynchronous Procedure Calls 0 Passive-Level Normale Threadausführung Prof. Dr. Peter Mandl Seite 23 Fallbeispiel: Windows, Interrupt-Bearbeitung (5) Interrupt Controller Interrupt-Verteiler-Code Interrupt-Service-
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