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Programmable Interrupt Controller Programmable Interrupt Controller Dr. Wajiha Shah Outline • Explain how the x86 executes interrupts by using the interrupt vector table and interrupt routines. • List the differences between interrupts and CALL instructions. • Describe the differences between hardware and software interrupts. • Examine the ISR for any interrupt, given its interrupt number. • Describe the function of each pin of the 8259 programmable interrupt controller (PIC) chip. • Explain the purpose of each of the four control words of the 8259 and demonstrate how they are programmed. • Examine the interrupts in x86 PC1s. 8088/86 INTERRUPTS • An interrupt is an external event that informs the CPU that a device needs its service. – In 8088/86 there are a total of 256 interrupts. • INT 00, INT 01, ..., INT FF (sometimes called TYPEs). • When an interrupt is executed the processor: – Saves the flag register (FR), instruction pointer (IP), and code segment register (CS) on the stack,. – Goes to a fixed memory location. • In x86, always four times the value of the interrupt number. 8088/86 INTERRUPTS interrupt service routine (ISR) 1. When an interrupt is invoked it is asked to run a program to perform a certain service. 2. There must be a program associated with every interrupt . 3. This program is commonly referred to as an interrupt service routine (ISR), and also called the interrupt handler. 4. When an interrupt is invoked, the CPU runs the interrupt service routine. 8088/86 INTERRUPTS interrupt service routine (ISR) – For every interrupt there are allocated four bytes of memory in the interrupt vector table. – Two bytes for the IP. – Two for the CS of the ISR. • These locations provide the addresses of the interrupt service routine for which the interrupt was invoked. – The lowest 1024 bytes of memory space are set aside for the interrupt vector table. 8088/86 INTERRUPTS differences between INT and CALL • What is the difference between… – INT instruction - which saves the CS:IP of the following instruction and jumps indirectly to the subroutine associated with the interrupt. – A CALL FAR instruction, which also saves CS:IP and jumps to the desired subroutine (procedure)? 8088/86 INTERRUPTS categories of interrupts • Three x86 pins are associated with hardware interrupts... – INTR (interrupt request) – NMI (nonmaskable interrupt) – INTA (interrupt acknowledge) • INTR is a CPU input signal, which can be masked (ignored) & unmasked through use CLI and STI. • NMI, also an input signal into the CPU, cannot be masked and unmasked using CLI & STI. – For this reason, it is called a nonmaskable interrupt. 8088/86 INTERRUPTS hardware interrupts • INTR and NMI are activated externally by putting 5V on the x86 microprocessor NMI & INTR pins. – On activation of either interrupt, x86: • Finishes the instruction it is executing. • Pushes FR & CS:IP of the next instruction onto the stack. • Jumps to a fixed location in the interrupt vector table and fetches the CS:IP for the interrupt service routine (ISR) associated with that interrupt. • At the end of the ISR, IRET causes the CPU to get (pop) back its original FR and CS:IP from the stack. – Forcing the CPU to continue at the instruction where it left off when the interrupt came in. INTERRUPT CONTROLLER • x86 has only pins INTR & INTA for interrupts. Figure 14-3 8259A Programmable Interrupt Controller 8259 INTERRUPT CONTROLLER The Intel 8259 programmable interrupt controller (PIC) makes expansion of the number of hardware interrupts much easier. Partial Block Diagram of the 8259A 8259 INTERRUPT CONTROLLER pins • CAS0, CAS1, and CAS2 - can be used to set up several 8259 chips to expand the number of hardware interrupts to 64. – By cascading 8259 chips in a master/slave configuration. • To use 8259 in slave mode, the chip must be programmed and CAS0 to CAS2 are ignored. • SP/EN, slave programming/enable - in buffered mode, an output signal from 8259 to activate the transceiver (EN). – In nonbuffered mode, an input signal into the 8259. • SP = 1 for the master and SP = 0 for the slave. 8259 INTERRUPT CONTROLLER pins • INT - an output connected to INTR of the x86. • INTA - input to the 8259 from INTA of the x86. • IR0 to IR7, interrupt request - hardware interrupts. – When a HIGH is put on any interrupt from IR0 to IR7, 8088/86 will jump to a vector location. – For each IR there exists a physical memory location in the interrupt vector table. • The x86 has 256 hardware or software interrupts. (INT 00–INT FF) 8259 INTERRUPT CONTROLLER control words and ports • Four control words associated with the 8259: – ICW1 (initialization command word); ICW2; ICW3; ICW4. – There is only one address line A0 to communicate with the chip. Figure 14-3 8259A Programmable Interrupt Controller 14.4: USE OF THE 8259 CHIP IN x86 PCs sources of NMI • The NMI, nonmaskable interrupt, is a CPU pin, and cannot be masked (disabled) by software. • There are three sources of activation of the NMI: – 1. NPIRQ. (numerical processor interrupt request) – 2. Read/write PCK. (parity check) – 3. IOCHK. (input/output channel check) • The PC recognizes which of interrupt requests has been activated by checking input port C of the 8255. .
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