by Stephen A. Edwards Retrocomputing on an FPGA Reconstructing an 80’s-Era Home Computer with Programmable Logic The author reconstructs a computer of his childhood, an Apple II+. As a Christmas present to myself in MOS Technology (it sold for $25 when 2007, I implemented an 1980s-era Apple an Intel 8080 sold for $179). The 6502 II+ in VHDL to run on an Altera DE2 had an eight-bit data bus and a 64K FPGA board. The point, aside from address space. In the Apple II+, the 6502 entertainment, was to illustrate the power ran at slightly above 1 MHz. Aside from (or rather, low power) of modern FPGAs. the ROMs and DRAMs, the rest of the Put another way, what made Steve Jobs circuitry consisted of discrete LS TTL his first million could be a class project chips (Photo 2). for the embedded systems class I teach at While the first Apple IIs shipped with Columbia University. 4K of DRAM, this quickly grew to a More seriously, this project standard of 48K. DRAMs, at this time, demonstrates how legacy digital were cutting-edge technology. While they electronics can be preserved and required periodic refresh and three power integrated with modern systems. While I supplies, their six-times higher density didn’t have an Apple II+ playing an made them worthwhile. important role in a system, many Along with with an integrated embedded systems last far longer than keyboard, a rudimentary (one-bit) sound their technology. The space shuttle port, and a game port that could sense immediately comes to mind; PDP-8s can buttons and potentiometers (e.g., in a be found running some signs for San joystick), the main feature of an Francisco’s BART system. Apple II+ was its integrated video display. It generated composite What is an Apple II+? (baseband) NTSC video that was usually The Apple II+ (Photo 1) was one of the sent through an RF modulator to appear first really successful personal computers. on TV channel 3 or 4. Designed by Steve Wozniak (“Woz”) and The Apple II+ had three video modes: introduced in 1977 [1, 2, 4], it really took × a 40 24 uppercase-only Photo 2: The Apple II+ Motherboard. Ex- off in 1978 when the 140K Disk II × black-and-white text display, a 40 48 pansion slots and analog video circuity 5.25-inch floppy drive was introduced, 16-color low-resolution display, and a dominate the top; the 6502 is above the followed by VisiCalc, the first × 140 280 6-color high-resolution six large ROM chips. The white rectan- spreadsheet. display. The Apple II+ can almost be gle encloses 48K of DRAM. The charac- Fairly simple even by the standards of thought of as a video controller that ter ROM is at the bottom; the rest is TTL. the day, the Apple II was built around the happens to have a microprocessor inexpensive 8-bit 6502 processor from connected to it. Woz started with a 14.31818 MHz master clock—exactly four times the 3.579545 MHz colorburst frequency used in NTSC video—and derived everything from it. The CPU and video alternate accesses to memory at 2 MHz. Another Woz trick: the video addresses are such that refreshing the video also suffices to refresh the DRAMs, so no additional refresh cycles are needed. Figure 1 shows the block diagram of my reconstruction. The 6502 processor on the left generates addresses and output Photo 1: An Apple II+ data. The address is fed to the ROMs, an Figure 1: Block Diagram Figure 2: Woz’s clock generator circuit. A 14.31818 MHz crystal drives a 4-bit shift register and a quad flip-flop to generate DRAM timing signals and the processor clocks, which in turn feed a bank of horizontal and vertical video counters. address range decoder, the peripheral patent [5], which describes it and his trick ’153 driving it, which selects between slots, and to a mux that selects between of using digital signals to generate color PRE PHI 0 and a combination of Q3 and processor and video system addresses for NTSC video. PHI0 depending on the state of AX. the main memory. Woz derived the CPU clock from the The third sequential process models The original Apple II+ used a tri-state 14M clock by dividing by roughly the four 4-bit binary counters. In the data bus, but FPGA cores do not support fourteen. “Roughly” because every original circuit, these were clocked by the such complex electrical structures sixty-fifth CPU cycle (one per horizontal output of a NAND gate. Such a practice (although they do provide tri-state I/O scan line) is stretched by two 14M clock is dangerous because the output of the pins), so my reconstruction breaks the periods to preserve the phase of the 3.58 gate might glitch and cause unpredictable data bus into multiple segments. Most MHz colorburst frequency. Thus, there behavior, so instead I chose to clock these notably, I added a large mux (right side of are 65 * 14 + 2 = 912 pixel periods per counters at 14 MHz and instead carefully Figure 1) that selects the source of data line, or exactly 228 cycles of the control when they count. fed to the 6502 core, such as main 3.58 MHz colorburst per line. Figure 3 shows a timing diagram for memory or the ROMS. While it would be possible to write a the clock generator illustrating how it The Clock Generator model for each TTL part in VHDL and behaves at the end of a line. The assemble them according to the COLOR DELAY N signal causes the Figure 2 shows the Apple’s clock schematic, I prefer to try to write the shift register to delay RAS N et al. two generator circuit. A crystal oscillator VHDL according to Woz’s intentions for extra 14M cycles, which also causes drives the clocks on a ’195 quad shift the original circuit. This is especially true PHI0 to be stretched. HCOUNT changes register and a ’175 quad flip-flop. These for combinational “glue” logic, which on the rising edge of LDPS N, just as in generate clocks for the the DRAM (RAS’ was often implemented in nonintuitive the original circuit. and CAS’) along with the “1 MHz” ways to save parts. The values taken on by the horizontal processor clocks PHI0 and PHI1. A gated Listing 1 shows my VHDL code for the counter are a little unusual: the counter is version of PHI0 feeds a bank of ’161s: clock generator. It assumes the 14 MHz allowed to wrap around from 7F to 00, four-bit binary counters configured to act clock is provided externally and consists but is then set to 40 to start the line. as horizontal and vertical counters of three main sequential processes. The These 65 PHI0 periods turn into about (H0–H5, VA–VC, and V0–V5) from first models the ’195 shift register, which 15.70 kHz, close to the NTSC horizontal which the video addresses are generated. either shifts or loads dependings on its frequency of 15.734 kHz. This clever circuit does a lot with few own Q3 output. The second process parts. It is at the center of Woz’s models the ’175 quad flip-flop and the 60 us 61 us 62 us 63 us 64 us 65 us Time CLK_14M RAS_N AX cas_n Q3 CLK_7M COLOR_REF PRE_PHI0 PHI0 LDPS_N HPE_N HCOUNT[6:0] 7E 7F 00 40 41 VCOUNT[8:0] 0FA 0FB COLOR_DELAY_N Figure 3: Behavior of the clock generator at the end of a line -- To generate the once-a-line hiccup: D1 pin 6 The CPU and Memory COLOR_DELAY_N <= not (not COLOR_REF and (not AX and not CAS_N) and PHI0 and not H(6)); Like Woz, I didn’t create a 6502 -- The DRAM signal generator processor from scratch. Instead, I used a C2_74S195: process (CLK_14M) 6502 core written by Peter Wendrich for begin if rising_edge(CLK_14M) then his FPGA-based Commodore 64. The if Q3 = ’1’ then -- shift main challenge here was making sure it (Q3, CAS_N, AX, RAS_N) <= unsigned’(CAS_N, AX, RAS_N, ’0’); was clocked properly given the odd way else --load the Apple II+ generates its occasionally (Q3, CAS_N, AX, RAS_N) <= unsigned’(RAS_N, AX, COLOR_DELAY_N, AX); stretched processor clock. end if; Semiconductor memory has changed a end if; lot since 1977. The Apple II+ end process; used 24 4116 16-kilobit DRAM chips -- The main clock signal generator B1_74S175 : process (CLK_14M) with 150 ns access times to provide 48 begin kilobytes of memory. Today, it is difficult if rising_edge(CLK_14M) then COLOR_REF <= CLK_7M xor COLOR_REF; to find memory chips this small. CLK_7M <= not CLK_7M; While it would have been nice to place PHI0 <= PRE_PHI0; if AX = ’1’ then all of the Apple’s memory on the FPGA I PRE_PHI0 <= not (Q3 xor PHI0); -- B1 pin 10 was using, it (an Altera Cyclone II 2C35) end if; end if; has about 59K of on-chip RAM, which is end process; just a little too small to fit 48K of RAM LDPS_N <= not (PHI0 and not AX and not CAS_N); plus 12K of ROMs. I chose instead to use LD194 <= not (PHI0 and not AX and not CAS_N and not CLK_7M); off-chip SRAM (the DE2 has 512K) for -- Four four-bit presettable binary counters the 48K of main memory and store the -- Seven-bit horizontal counter counts 0, 40, 41, ..., 7F (65 states) ROMs on-chip. Storing the ROMs in -- Nine-bit vertical counter counts $FA .