A New Simulated Inductor with Reduced Series Resistor Using a Single VCII±

Article A New Simulated Inductor with Reduced Series Resistor Using a Single VCII±

Erkan Yuce 1, Leila Safari 2, Shahram Minaei 3, Giuseppe Ferri 2 , Gianluca Barile 2 and Vincenzo Stornelli 2,*

1 Department of Electrical and Electronics Engineering, Pamukkale University, Denizli 20160, Turkey; [email protected] 2 Department of Industrial and Information Engineering, University of L’Aquila, 67100 L’Aquila, Italy; [email protected] (L.S.); [email protected] (G.F.); [email protected] (G.B.) 3 Department of Electrical and Electronics Engineering, Dogus University, Istanbul 34775, Turkey; [email protected] * Correspondence: [email protected]

Abstract: This paper presents a new realization of a grounded simulated inductor using a single dual output second-generation voltage conveyor (VCII±) as an active building block, two resistors and one grounded capacitor. The main characteristic of the proposed circuit is that the value of the series resistor can be significantly reduced. Thus, it has the property of improved low-frequency performance. Another feature is the use of a grounded capacitor that makes the proposed circuit attractive for integrated circuit (IC) realization. A simple CMOS implementation of the required VCII± is used. However, a single passive component-matching condition is required for the proposed structure. As an application example, a standard fifth-order high-pass ladder filter is also given. SPICE simulations using 0.18 µm CMOS technology parameters and a supply voltage of ±0.9 V as well as experimental verifications, are carried out to support the theory.

Citation: Yuce, E.; Safari, L.; Minaei, Keywords: simulated inductor; low-series resistor; VCII; voltage conveyor; high-gain VCII; current- S.; Ferri, G.; Barile, G.; Stornelli, V. A New Simulated Inductor with mode; ladder filter; band-pass filter Reduced Series Resistor Using a Single VCII±. Electronics 2021, 10, 1693. https://doi.org/10.3390/ electronics10141693 1. Introduction Inductors are analog passive components that play an essential role in many ana- Academic Editor: Christos Volos log and mixed-signal circuits. Due to the large occupation of area and the low-quality factor of spiral inductors, designers prefer to substitute them with simulated inductors Received: 10 June 2021 (SIs) [1–49]. SIs are constructed using a few active elements, resistors and one capacitor, Accepted: 12 July 2021 and exhibit characteristics of inductance within a specified frequency range. They find Published: 15 July 2021 wide applications in the design of active filters, oscillators, phase shifters, etc. SIs using various kind of active devices offer some advantages such as the capability for integra- Publisher’s Note: MDPI stays neutral tion, low area, high quality factor, operation in a wide frequency range, etc. However, with regard to jurisdictional claims in grounded SIs [1–49] have the following problems. Some of the grounded SIs [1,2] use oper- published maps and institutional affil- ational amplifiers (OAs); therefore, they suffer from slew-rate limitations. Other grounded iations. SIs [1–10,12–14,19,21,31,33,34,39,48,49] employ more than one active building block (ABB). The grounded SI configurations described in [1,2,6,11,12,15–20,24–28,35,37,39,43–47] in- clude a floating capacitor that is not suitable for integrated circuit (IC) fabrication. The grounded SI proposals in [17,22,24–30,36,38,42,45,46] contain complex internal structures. Copyright: © 2021 by the authors. Other grounded topologies [40–46] are made up of non-standard active devices. Finally, Licensee MDPI, Basel, Switzerland. the grounded SI architectures reported in [9,23,30–35,37] have a capacitor connected to a This article is an open access article low-impedance terminal or consist of an operational transconductance amplifier (OTA); distributed under the terms and accordingly, their high-frequency performances are limited [50,51]. conditions of the Creative Commons A literature survey revealed that, in recent years, the current-mode (CM) approach Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ has been widely used in the SI design [1–17,20–22,24–29,36,38–49]. The main reason is 4.0/). the potential of the CM signal processing with its low-voltage nature and high-frequency

Electronics 2021, 10, 1693. https://doi.org/10.3390/electronics10141693 https://www.mdpi.com/journal/electronics Electronics 2021, 10, 1693 2 of 15

operation, etc. [52,53]. Recently, a new CM active building block called second-generation voltage conveyor (VCII) [54–56] has been used in the implementation of high-performance grounded immittance-function simulators [48,57]. This new block is the dual circuit of the more famous second-generation current conveyor (CCII). The difference between CCII and VCII is that, unlike VCII, CCII lacks a low-impedance voltage output port. This feature enables VCII-based circuits to benefit from advantages of processing signals in the current domain while producing output signals in voltage form. Therefore, VCII is suitable for all applications requiring output signal in the form of voltage. The results reported in [54–56] reveal that VCII-based circuits outperform conventional circuits in many aspects. For instance, achieved simulated impedances in [48,57] are robust against process mismatches and temperature variations while their power consumption is reduced, when compared to the other reported work. The latter feature comes from the very simple internal structure of the used ABB, i.e., VCII. The maximum operation frequency range and parasitic series impedance of the VCII-based grounded SI reported in [48] are 2.5 MHz and 191 Ω, respectively. It also employs two ABBs. Here, we aim to design a VCII-based grounded SI with improved performance that uses only one ABB. The proposed circuit is based on one dual-output VCII (VCII±) as ABB, two resistors and one grounded capacitor. The most important feature of the new implementation is that the value of series impedance is considerably reduced by adjusting resistor values. Hence, it has the property of improved low-frequency performance. It employs only a grounded capacitor that results in easy integration in the IC process. In addition, the frequency range is extended to 10 MHz. Additionally, complete circuit analysis and SPICE simulation results are reported. As an application example, a fifth- order high-pass (HP) ladder filter is presented. Nevertheless, there is a simple matching condition which can be easily satisfied. Fortunately, this matching condition is also useful in setting the value of parasitic series resistance to the desired value. The promising results through the SPICE simulation program and experimental verifications show that VCIIs are highly suitable in the SI applications. Compared to the grounded SI based on the negative- impedance converters (NICs) of [49] which employ two active elements, two resistors and one grounded capacitor, the realized inductor value is four times lower than the one extracted from the proposed circuit for the same values of the capacitor and resistors. The organization of this paper is as follows. In Section2, VCII ± and the proposed SI are introduced and analyzed. The non-ideal analysis is performed in Section3. Simulation results are reported in Section4. Experimental verifications are presented in Section5. Finally, Section6 concludes the paper.

2. The Proposed Circuit Figure1 shows the symbolic presentation and internal structure of the VCII ± without a Z− port. It has a low-impedance current input Y terminal, two high-impedance current output X+ and X− terminals and one low impedance voltage output terminal, Z+. It simply consists of a current buffer (CB) and a voltage buffer (VB). The input current is transferred from the Y terminal to the X+ terminal in the same direction and the X− terminal in the opposite direction. The voltage at the X+ terminal is transferred to the Z+ terminal. The VCII± demonstrated in Figure1 is described as:     IX+ 0 0 β   VX+  IX−   0 0 −η    =   VX−  (1)  VY   0 0 0  IY VZ+ α 0 0 Electronics 2021, 10, x FOR PEER REVIEW 3 of 16

Electronics 2021, 10, x FOR PEER REVIEW 3 of 16 Electronics 2021, 10, 1693 3 of 15

(a) (b) Figure 1. VCII± without Z− port: (a) symbolic presentation (b) internal structure.

The proposed VCII±-based SI is shown in Figure 2. Simple analysis shows that, in the case of ideal VCII (negligible contribution of parasitic impedances), the input impedance of the proposed SI is evaluated by

𝑍(𝑠) =𝑠𝐶𝑅𝑅 +𝑅 −𝑅 (2)

In above equation, if R2 = R1 = R is chosen, the following input impedance is obtained:

𝑍(𝑠) =𝑠𝐶𝑅 (3) One observes from Equation (3) that a positive lossless grounded SI is obtained. If non-ideal(a) gains are considered, Equation (2) turns(b) to: Figure 1. VCII±Figure without 1. VCII Z−± port:without (a)Z symbolic− port: (a) symbolicpresentation presentation (b) internal (b) internal structure. structure. 𝑠𝐶𝑅𝑅 +𝑅 + (1−𝜂)𝑅 𝑍 (𝑠) = (4) In Equation (1), β and η, being current gains, are ideally𝛼𝛽 equal to one and two, The proposed respectively.VCII±-based Additionally, SI is shownα, beingin Figure voltage 2. gain,Simple is ideally analysis equal shows to unity. that, in the case of ideal VCII (negligibleTheFrom proposed Equationcontribution VCII± (4),-based of quality parasitic SI is shown factor impedances), in Figure(Q) for2. Simple equivalent the analysis input inductance impedance shows that, in is the found as of the proposed SI caseis evaluated of ideal VCII by (negligible contribution of parasitic impedances), the input impedance 𝜔𝐶𝑅𝑅 of the proposed SI is evaluated by 𝑄= (5) 𝑍(𝑠) =𝑠𝐶𝑅𝑅 +𝑅 −𝑅 𝑅 + (1−𝜂)𝑅 (2) Zin(s) = sCR1R2 + R1 − R2 (2) In above equation, if R2 = R1 = R is chosen, the following input impedance is obtained:

R1 𝑍(𝑠) =𝑠𝐶𝑅 (3) One observes from Equation (3) that a positive lossless grounded SI is obtained. If non-ideal gains are considered, Equation (2) turns to:

𝑠𝐶𝑅𝑅 +𝑅 + (1−𝜂)𝑅 𝑍(𝑠) Y= (4) X-𝛼𝛽 From Equation (4), quality factor (Q) for equivalent inductance is found as VCII± 𝜔𝐶𝑅𝑅 𝑄= (5) 𝑅 + (1−𝜂)𝑅 Iin Z+ Vin X+ R2 R1 C

Zin Y X- FigureFigure 2. 2.Proposed Proposed VCII VCII±-based±-based simulated simulated inductor. inductor. VCII±

Iin Z+ Vin X+ R2

Z in Figure 2. Proposed VCII±-based simulated inductor.

Electronics 2021, 10, x FOR PEER REVIEW 4 of 16

From Equation (5) it can be realized that for the ideal case, where R1 = R2 and η = 2, the Q value of the inductance is infinity.

3. Parasitic Impedance Effects Figures 3 and 4 show the VCII± with its parasitic impedances and the equivalent Electronics 2021, 10, 1693 model of the proposed SI, respectively. Thus, the VCII± denoted4 ofin 15 Figure 3 is described as

R = R = R 1 In above equation, if 2 1 is⎡ chosen,𝑠𝐶 + the following input0 impedance10 is obtained:⎤ 𝐼 𝑅 𝑉 Z⎢ (s) = sCR2 ⎥ (3) 𝐼 in⎢ 1 ⎥ 𝑉 = 0𝑠𝐶+ (6) One observes from Equation𝑉 (3) that⎢ a positive lossless grounded SI is−2 obtained. 0 ⎥ If𝐼 𝑅 non-ideal gains are considered,𝑉 Equation⎢ (2) turns to: ⎥ 𝐼 ⎢ 0 0 𝑅 0 ⎥ sCR⎣ R + R + (1 − η)R 0𝑅⎦ Z (s) = 1 2 11 2 0 (4) in αβ By a simple analysis, including only parasitic impedances of the VCII±, Equation (2) convertsFrom Equation to: (4), quality factor (Q) for equivalent inductance is found as

ωCR1R2 Q = 1 (5) + ( − ) 𝑍R1 (𝑠)1 =𝑅η R2 // //(𝑠𝐿 +𝑟) (7) 𝑠𝐶 From Equation (5) it can be realized that for the ideal case, where R1 = R2 and η = 2, theHere,Q value Leq, of req the, R inductanceeq and Ceq is are, inﬁnity. respectively, calculated as 3. Parasitic Impedance Effects 𝐿 =(𝐶+𝐶)(𝑅 +𝑅)(𝑅 +𝑅) (8) Figures3 and4 show the VCII ± with its parasitic impedances and the equivalent model of the proposed SI, respectively.(𝑅 Thus,+𝑅 the) VCII+(𝑅±denoted+𝑅) in Figure3 is described as 𝑟 = +𝑅 +𝑅 −𝑅 −𝑅 (9)  1 𝑅    sCx+ + 0 1 0   IX+ RX+ VX+ 1  IX−   0 sCx− + −2 0  VX−   RX− 𝑅 =𝑅    =    (6) (10)  VY   0 0 RY 0  IY  V + I + Z 1 0 𝐶0 =𝐶RZ+ Z (11)

Ideal VCII±

IY RX- C VY Y X- RY X- VX- IX-

IZ+

Z+ VZ+ RZ+ IX+

VX+ X+

CX+ RX+

FigureFigure 3. VCII3. VCII±± and itsand parasitic its parasitic impedances. impedances.

ElectronicsElectronics 20212021,, 1010,, x 1693 FOR PEER REVIEW 55 of of 16 15

Iin Vin

req Zin Ceq Req

Leq

FigureFigure 4. 4. EquivalentEquivalent model model of of the the proposed proposed simulated simulated inductor. inductor.

ItBy is aseen simple from analysis, Equations including (7) and only (8) that parasitic the proposed impedances SI has of therestrictions VCII±, Equationat high fre- (2) quenciesconverts due to: to parasitic elements RX+ and CX+ and at low frequencies due to req. Fortu- 1 nately, req can be set to zeroZ by( choosings) = R // R2 as follows://sL + r (7) in eq sC eq eq (𝑅 +𝑅 )𝑅 +eq(𝑅 +𝑅 −𝑅 )𝑅 𝑅 = Here, Leq, req, Req and Ceq are, respectively, calculated as (12) 𝑅 −(𝑅 +𝑅)

If RX− is too high (RX-L >eq ∞=), the(C + EquationCX−)(R 1(12)+ R isY )(reducedR2 + R toZ+ R) 2 = R1 + RY − RZ+, which (8)is easily satisfied in practice. (R1 + RY) + (R2 + RZ+) req = + R1 + RY − R2 − RZ+ (9) 4. Simulation Results RX−

The performance of the proposed circuitReq = ofRX Figure+ 2 is tested through SPICE simula-(10) tions using 0.18 μm CMOS technology parameters and a supply voltage of ±0.9 V. The C = C (11) resulted performance parameters for theeq VCII±,X+ derived from one in Figure 5 [58], are reportedIt is in seen Table from 1 in Equations which VB (7)= 0.23 and V (8)is chosen. that the The proposed proposed SI hassolution restrictions for the atimple- high mentationfrequencies of duean equivalent to parasitic inductor elements is notRX+ relatedand C toX+ aand specific at low VCII. frequencies The size of due M13 to, M req.9– MFortunately,10 determines req the can value be set of to rY zero. The by size choosing of M3, M R218 asdetermines follows: impedance at X+ port; the size of M8–M24 determines the impedance at X− port; and finally the size of M11–M12, M14 (R + R )R + + (R + R − R +)R − determines the impedanceR = at Z1+ port.Y AspectZ ratios1 ofY the PMOSZ X transistors, M1–M7 and(12) 2 − ( + ) M9–M12, are chosen as 40.5 μm/0.54 μmR andX− MR8, 1M13R andY M14 are selected as 81 μm/0.54 μm. Furthermore, those of NMOS transistors, M15–M23, are chosen as 13.5 μm/0.54 μm and If RX− is too high (RX− > ∞), the Equation (12) is reduced to R2 = R1 + RY − RZ+, that of M24 is selected as 27 μm/0.54 μm. Total power-dissipation of the proposed SI is which is easily satisfied in practice. nearly found as 1.92 mW. To achieve an inductance value of about 200 μH, all the values of4. passive Simulation components Results are chosen as R1 = 2 kΩ, R2 ≅ 2.16 kΩ and C = 50 pF. Frequency responsesThe performanceof the proposed of theSI and proposed an ideal circuit inductor of Figure are shown2 is tested in Figure through 6. From SPICE the sim- ulationulations results, using the 0.18 operationµm CMOS frequency technology rang parameterse of the proposed and a supplySI is 1 kHz–10 voltage MHz. of ±0.9 The V. valueThe resulted of series performance impedance is parameters also obtained for theas a VCII negligible±, derived value from of 237 one m inΩ Figure. To test5[ the58], time-domain performance of the proposed inductor simulator, a sinusoidal input current are reported in Table1 in which VB = 0.23 V is chosen. The proposed solution for the withimplementation peak amplitude of an of equivalent25 μA and frequency inductor is of not 1 MHz related is used. to a specific VCII. The size of M13, M9–M10 determines the value of rY. The size of M3, M18 determines impedance at X+ port; the size of M8–M24 determines the impedance at X− port; and finally the size of M11–M12, M14 determines the impedance at Z+ port. Aspect ratios of the PMOS transistors, M1–M7 and M9–M12, are chosen as 40.5 µm/0.54 µm and M8, M13 and M14 are selected as 81 µm/0.54 µm. Furthermore, those of NMOS transistors, M15–M23, are chosen as 13.5 µm/0.54 µm and that of M24 is selected as 27 µm/0.54 µm. Total power-dissipation of the proposed SI is nearly found as 1.92 mW. To achieve an inductance value of about ∼ 200 µH, all the values of passive components are chosen as R1 = 2 kΩ, R2 = 2.16 kΩ and C = 50 pF. Frequency responses of the proposed SI and an ideal inductor are shown in Figure6. From the simulation results, the operation frequency range of the proposed SI

Electronics 2021, 10, 1693 6 of 15 Electronics 2021, 10, x FOR PEER REVIEW 6 of 16

is 1 kHz–10 MHz. The value of series impedance is also obtained as a negligible valueVDD Electronics 2021, 10, x FOR PEER REVIEW 6 of 16 of 237V mΩ. To test the time-domain performance of the proposed inductorM M simulator,M a B M 6 7 8 sinusoidal inputM1 current withM2 peakM amplitude3 ofM 254 µA and frequency5 of 1 MHz is used.

VDD

M9 M10 Y M11 M12 Z+ X- VB M6 M7 M8 M M2 M3 M4 M5 1 M13 X+ M14

M15 M16 M17 M18 M19 M20 M21 M22 M23 M24

V M9 M10 Y M11 M12 Z+ X- SS

M13 X+ M14 Figure 5. Internal structure of the used VCII± without Z− terminal.

M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 Table 1. Some performance parameters of the VCII± of Figure 5. VSS Parameter Value Parameter Value Figure 5. Internal structure of the used VCII± without Z− terminal. Figure 5. InternalRY structure of the used19 VCIIΩ ± without Z− terminal.β 1.004

Table 1. Some performanceTable 1. Some parametersRX+performance of the parameters VCII±41 ofkΩ ofFigure the VCII 5. ± of Figureη5 . 2.021

Parameter Value Parameter Value Parameter RX− Value 20 kΩParameter α Value 0.973 RY 19 Ω β 1.004 RRZ+ 4119 k ΩΩ η 2.021 RY X+ 19 Ω β 1.004 RX− 20 kΩ α 0.973 CX+ 143 fF RZ+ 19 Ω RX+ 41 kΩ η 2.021 CX+ 143 fF CX− 111 fF CX− 111 fF RX− 20 kΩ α 0.973

RZ+ 19 Ω

CX+ 143 fF

CX− 111 fF

FigureFigure 6.6.Frequency Frequency responsesresponses ofof thethe proposedproposed simulated simulated inductor inductor and and ideal ideal inductor. inductor.

FigureFigure7 7shows shows the the produced produced output output signals signals along along with with applied applied input input signal. signal. Addi- Addi- tionally, the value of total harmonic distortion (THD) is 1.8%. The value of the phase shift tionally, the value of total harmonic distortion (THD) is 1.8%. ◦The value of the phase shift betweenbetween inputinput currentcurrent andand output output voltage voltage is is approximately approximately 90 90°.. ThereThere isis anan offsetoffset voltage voltage − atat thethe simulation simulation output output voltage voltag whosee whose value value is approximatelyis approximately12 − mV.12 mV. Figure Figure8 shows 8 shows the THDthe THD variations variations for various for various amplitudes amplitudes of the of peak-input the peak-input currents currents at a frequency at a frequency of 1 MHz. of 1 Favorably,MHz. Favorably, the maximum the maximum value of value THD of remains THD remains below 3.7%. below To 3.7%. test the To frequency-domaintest the frequency- applicability of the proposed SI, it is used in a standard fifth-order HP ladder filter shown Figure 6. Frequencydomain responses applicability of the proposed of the proposedsimulated SI, inductor it is used and in ideala standard inductor. fifth-order HP ladder filter in Figure9 with Leq1 = Leq2 = 200 µH, RS = RL = 5 kΩ and C1 = C2 = C3 = 50 pF. Frequency- shown in Figure 9 with Leq1 = Leq2 = 200 μH, RS = RL = 5 kΩ and C1 = C2 = C3 = 50 pF. Fre- domain analysis for the filer is given in Figure 10. A time-domain analysis for the filter quency-domain analysis for the filer is given in Figure 10. A time-domain analysis for the Figure 7 showsexample the produced is depicted output in Figure signal 11, ins whichalong awith sinusoidal applied input input voltage signal. with Addi- a 250 mV peak filter example is depicted in Figure 11, in which a sinusoidal input voltage with a 250 mV tionally, the valueand of total a frequency harmonic of 2.5 distortion MHz is applied. (THD) is Figure 1.8%. 12 The demonstrates value of the the phase THD shift variations for peak and a frequency of 2.5 MHz is applied. Figure 12 demonstrates the THD variations between input current and output voltage is approximately 90°. There is an offset voltage at the simulation output voltage whose value is approximately −12 mV. Figure 8 shows the THD variations for various amplitudes of the peak-input currents at a frequency of 1 MHz. Favorably, the maximum value of THD remains below 3.7%. To test the frequency- domain applicability of the proposed SI, it is used in a standard fifth-order HP ladder filter shown in Figure 9 with Leq1 = Leq2 = 200 μH, RS = RL = 5 kΩ and C1 = C2 = C3 = 50 pF. Fre- quency-domain analysis for the filer is given in Figure 10. A time-domain analysis for the filter example is depicted in Figure 11, in which a sinusoidal input voltage with a 250 mV peak and a frequency of 2.5 MHz is applied. Figure 12 demonstrates the THD variations

Electronics 2021, 10, x FOR PEER REVIEW 7 of 16 Electronics 2021, 10, x FOR PEER REVIEW 7 of 16

for various amplitudes of peak-input voltages at 2.5 MHz. Monte Carlo (MC) simulations ElectronicsElectronics 20212021, 10, ,x10 FOR, 1693 PEERfor REVIEW various amplitudes of peak-input voltages at 2.5 MHz. Monte Carlo (MC) simulations7 of 167 of 15 are accomplished in 100 runs where all the passive elements of the filter, as shown in Fig- are accomplished in 100 runs where all the passive elements of the filter, as shown in Fig- ure 13, are changed by 1%. Furthermore, threshold voltages of all the MOS transistors in ure 13, are changed by 1%. Furthermore, threshold voltages of all the MOS transistors in for Figurevarious 5amplitudes are varied of by peak-input 1% and the voltages result at for 2.5 th MHz.e filter Monte example Carlo is (MC) given simulations in Figure 14. Power Figure 5 variousare varied amplitudes by 1% and of peak-input the result voltages for the atfilter 2.5 MHz.example Monte is given Carlo in (MC) Figure simulations 14. Power are are suppliesaccomplished are varied in 100 runsand wherethe result all the for pass theive filter elements example of the is filter,depicted as shown in Figure in Fig- 15. suppliesaccomplished are varied and in 100 the runs result where for allthe the filter passive example elements is depicted of the filter, in asFigure shown 15. in Figure 13, ure 13, are changed by 1%. Furthermore, threshold voltages of all the MOS transistors in are changed by 1%. Furthermore, threshold voltages of all the MOS transistors in Figure5 Figure 5 are varied by 1% and the result for the filter example is given in Figure 14. Power are varied by 1% and the result for the filter example is given in Figure 14. Power supplies suppliesare varied are varied and theand result the result for the for filter the filter example example is depicted is depicted in Figure in Figure 15. 15.

Figure 7. Time-domain responses of the proposed simulated inductor. Figure 7. Time-domain responses of the proposed simulated inductor. FigureFigure 7. Time-domain 7. Time-domain responses responses of the of proposed the proposed simulated simulated inductor. inductor.

FigureFigureFigure 8. THD 8. THD values values values of output of of output output voltages voltages voltages of the of theproposed of proposed the proposed simulated simulated simulated inductor inductor for in for differentductor different for peak peakdifferent val- values peak val- Figure 8. THD values of output voltages of the proposed simulated inductor for different peak values uesofof the the of input inputthe input currents. currents. currents. ues of the input currents.

Figure 9. Standard fifth-order high-pass ladder filter realization [49]. Figure 9. Standard fifth-order high-pass ladder filter realization [49]. Figure 9. FigureStandard 9. Standard fifth-order ﬁfth-order high-pass high-pass ladder ladder filter ﬁlterrealization realization [49]. [49 ].

ElectronicsElectronicsElectronics 2021 2021 ,2021 10, 10, x,, x10FOR FOR, 1693x FORPEER PEER PEER REVIEW REVIEW REVIEW 8 8of of 16 816 of 16 15

FigureFigureFigureFigure 10. 10. Frequency Frequency10. 10. FrequencyFrequency responses responses responses responses of of the the of fifth-orde the fifth-orde fifth-orde ﬁfth-orderr rhigh-pass high-passr high-pass ladder ladder ladder filter filter filter ﬁlter example. example. example.

FigureFigureFigureFigure 11. 11. Time-domain Time-domain11. 11. Time-domainTime-domain analysis analysis analysis for for the forthe HP the HP ladder HP ladder ladder filter filter filter ﬁlterexample. example. example.

Figure 12. THD variations of the HP ladder ﬁlter for various amplitudes of the peak-input voltages FigureFigureFigure 12. 12. THD THD12. THD variations variations variations of of the the of HP theHP ladder HPladder ladder filter filter filter for for various forvarious various amplitudes amplitudes amplitudes of of the the of peak-input thepeak-input peak-input voltages voltages voltages at 2.5 MHz. atat 2.5 2.5at MHz. MHz.2.5 MHz.

ElectronicsElectronicsElectronicsElectronics 2021 2021 2021, 202110, ,,10 x10, ,FOR10 ,x x ,FOR 1693FOR PEER PEER PEER REVIEW REVIEW REVIEW 9 of9 916of of9 16 of 16 15

FigureFigureFigureFigure 13. 13. 13.Monte 13.Monte MonteMonte Carlo Carlo Carlo Carlo simulations simulations simulations simulations of ofthe of the of theHP the HP HPladder HP ladder ladder ladder filter filter filter ﬁlterwith with with withchanges changes changes changes of ofall of ofall theall allthe thepassive the passive passive passive elements. elements. elements. elements.

FigureFigureFigureFigure 14. 14. 14.Monte 14. Monte MonteMonte Carlo Carlo Carlo Carlo simulations simulations simulations simulations of ofthe of the of theHP the HP HPladder HP ladder ladder ladder filter filter filter ﬁlterwith with with withchanges changes changes changes of ofthreshold of ofthreshold threshold threshold voltages voltages voltages voltages of ofall of ofall all all thethe theMOSthe MOS MOS MOStransistors. transistors. transistors. transistors.

FigureFigureFigureFigure 15. 15. 15.Frequency 15. Frequency FrequencyFrequency responses responses responses responses of ofthe of ofthe theHP the HP HPladder HP ladder ladder ladder filter filter filter ﬁlterfor for fordifferent for different different different power power power power supplies. supplies. supplies. supplies.

Electronics 2021, 10, 1693 10 of 15

A comparison among the proposed grounded SI with other reported similar works, such as CFOA [4–7], CCII [8–11] and VCII-based ones [47,48], is drawn in Table2, which considers important parameters such as technology, power dissipation, supply voltage, frequency range and the number of grounded and ﬂoating passive components, etc. The work reported in [4] suffers from a high supply voltage of ±5V. Although the frequency range of the circuit reported in [7] is limited to 1 kHz, it consumes larger power consumption compared to the proposed circuit because it employs two CFOA as active building blocks. In fact, compared to VCII, which consists of one CB and one VB, the internal structure of each CFOA is formed by one CB and two VBs. Therefore, even in equal conditions, the circuit reported in [7] consumes larger power if compared to the proposed one. The circuit reported in [10], which employs three CCII as active building blocks, is applicable at frequencies larger than 100 kHz while the proposed circuit low-frequency range is 1 kHz. This is attributed to the reduced parasitic series resistance as well as its simplicity, which employs only one active building block; therefore, the number of parasitic elements, which are the frequency-performance limiting factor, is reduced. Although, compared to the previously reported VCII-based SI circuit of [48], the power consumption of the proposed circuit is increased approximately 3 times, but the frequency range is extended from 2.5 MHz to 10 MHz. The work reported in [48] also shows a lossy inductor. In addition, the series resistance is decreased from 191 Ω to 0.23 Ω. Moreover, by setting the values of R1 and R2, the value of a parasitic series resistor can be set as required in the speciﬁc application.

Table 2. A comparison among the proposed circuit and some other previously reported similar works.

# of Passive Elements Power Improved Low Reference # ABB (Type) Frequency Range Technology Dissipation VDD-VSS Frequency # of R # of C (mW) Performance G (F) G (F) [4] 3 (CFOA) 2 (1) 1 (0) 1 µHz–1 MHz AD844 NA ±5 Yes [5] 2 (CFOA) 1 (1) 1 (0) NA AD844 NA NA No [6] * 1 (CFOA) 1 (1) 0 (1) Low AD844 NA ±15 No [7] 2 (CFOA) 2 (1) 1 (0) 1 kHz–100 MHz 0.13 µm 3.05 ±0.75 Yes [8] 2 (CCII) 2 (0) 1 (0) NA NA NA NA No [9] 2 (CCII) 2 (0) 1 (0) NA AD844 NA ±12 No [10] 3 (CCII) 2 (1) 1 (0) 100 kHz–100 MHz 0.35 µm NA ±1.5 Yes [11] 1 (CCII) 2 (2) 0 (1) NA NA NA NA No [47]* MOS transistors 2 (0) 0 (1) <1 kHz NA NA NA No [48] 2 (VCII) 0 (2) 1 (0) 50 kHz–2.5 MHz 0.18 µm 0.65 ±0.9V No Proposed 1 VCII± 0 (2) 1 (0) 1 kHz–10 MHz 0.18 µm 1.92 ±0.9V Yes G: grounded, F: ﬂoating, NA: not available, *: lossy.

5. Experimental Verifications Implementation of the VCII± by utilizing AD844s [59] is demonstrated in Figure 16 where supply voltages of AD844s are chosen as ±12 V. Additionally, passive elements Ra = Rb = 2.2 kΩ; Rc = 1.1 kΩ for realizing VCII; R1 = R2 = 2.2 kΩ; and C = 2.2 nF for ∼ realizing L, are selected to obtain Leq = 10.65 mH. Figure 17 shows a picture of the fabricated board, highlighting its main features. The experimental setup used to evaluate the equivalent inductance is depicted in Figure 18 where R’ = 1 kΩ is chosen. Thus, a time-domain analysis of the measured grounded SI is given in Figure 19, where a sinusoidal input voltage signal (Vin) with 0.5 V peak at 25 kHz is applied to the input and output ◦ voltage taken from Vout. The measured phase shift between them is approximately 86 . A second-order voltage-mode band-pass (BP) filter application is analyzed as well: in Figure 20 the schematic that is used for this experiment is reported. Transfer function of the BP filter in Figure 20 is evaluated as:

1 s C R H(s) = f (13) s2 + s 1 + 1 Cf R LCf Electronics 2021, 10, x FOR PEER REVIEW 11 of 16

5. Experimental Verifications Implementation of the VCII± by utilizing AD844s [59] is demonstrated in Figure 16 where supply voltages of AD844s are chosen as ±12 V. Additionally, passive elements Ra = Rb = 2.2 kΩ; Rc = 1.1 kΩ for realizing VCII; R1 = R2 = 2.2 kΩ; and C = 2.2 nF for realizing L, are selected to obtain Leq ≅ 10.65 mH. Figure 17 shows a picture of the fabricated board, highlighting its main features. The experimental setup used to evaluate the equivalent inductance is depicted in Figure 18 where R’ = 1 kΩ is chosen. Thus, a time-domain analysis of the measured grounded SI is given in Figure 19, where a sinusoidal input voltage signal (Vin) with 0.5 V peak at 25 kHz is applied to the input and output voltage taken from Vout. The measured phase shift between them is approximately 86°. A second-order voltage-mode band-pass (BP) filter application is analyzed as well: in Figure 20 the schematic that is used for this experiment is reported. Transfer function of the BP filter in Fig- ure 20 is evaluated as: 1 𝑠 𝐶 𝑅 𝐻(𝑠) = 1 1 (13) 𝑠 +𝑠 + 𝐶𝑅 𝐿𝐶 The measured transfer function is reported in Figure 21 and compared to the simulated and the ideal ones. For this analysis the following values are chosen: R ≅ 1 kΩ, R1 ≅ 1.9 kΩ (given in order to improve low-frequency performance); R2 = 2.2 kΩ and C = 2.2 nF, yielding L ≅ 9.2 mH. Additionally, Cf = 30 nF is chosen to obtain f0 ≅ 9.58 kHz. In Figure 21, there is good agreement between ideal, simulated and measurement results above 1kHz. Any discrepancy between these results occurs at frequencies below 1 KHz which is not in Electronics 2021, 10, 1693 the operation frequency range of the proposed circuit and is due to the combined11 non of 15 idealities from AD844s. A time-domain analysis for the BP filter is given in Figure 22 in which a sinusoidal input voltage with 1 V peak-to-peak at f = f0 is applied.

+ AD844 Y - (2) W Z AD844 Rc X- (1) W - Z + +

Ra AD844 (3) W Z+ Z Rb X+ - Electronics 2021, 10, x FOR PEER REVIEW 12 of 16 Electronics 2021 , 10, x FOR PEER REVIEW 12 of 16

± FigureFigure 16. 16. ImplementationImplementation of of the the VC VCIIII± byby utilizing utilizing AD844s. AD844s.

(a) (b) (a) (b) Figure 17. A photograph of the fabricated board (a) and its description (b). FigureFigure 17. A 17. photographA photograph of the of fabricated the fabricated board board (a) and (a) its and description its description (b). (b).

Current Generator Vout Current Generator Vout Vin + Vin + AD844 W AD844 W Proposed Z Proposed Z grounded - grounded - Iin simulated Iin simulated inductor R/ inductor R/

Figure 18. Experimental setup for realizing the grounded simulated inductor. FigureFigure 18. 18. ExperimentalExperimental setup setup for for realizing realizing the grounded simulated inductor.

Figure 19. Measured time-domain analysis of the grounded simulated inductor. Figure 19. Measured time-domain analysis of the grounded simulated inductor.

Electronics 2021, 10, x FOR PEER REVIEW 12 of 16

(a) (b)

Figure 17. A photograph of the fabricated board (a) and its description (b).

Current Generator Vout Vin +

AD844 W Proposed Z - grounded Iin simulated inductor R/

Electronics 2021, 10, 1693 12 of 15

Figure 18. Experimental setup for realizing the grounded simulated inductor.

Electronics 2021, 10, x FOR PEER REVIEW 13 of 16

FigureFigure 19.19. MeasuredMeasured time-domaintime-domain analysisanalysis ofof thethe groundedgrounded simulatedsimulated inductor.inductor.

Electronics 2021, 10, x FOR PEER REVIEW 13 of 16

FigureFigure 20. 20.A A second-order second-order voltage-mode voltage-mode band-pass band-pass ﬁlter filter application. application.

The measured transfer function is reported in Figure 21 and compared to the simulated ∼ ∼ and the ideal ones. For this analysis the following values are chosen: R = 1 kΩ, R1 = 1.9 kΩ (given in order to improve low-frequency performance); R2 = 2.2 kΩ and C = 2.2 nF, yielding ∼ ∼ L = 9.2 mH. Additionally, Cf = 30 nF is chosen to obtain f 0 = 9.58 kHz. In Figure 21, there is good agreement between ideal, simulated and measurement results above 1kHz. Any discrepancy between these results occurs at frequencies below 1 KHz which is not in the operation frequency range of the proposed circuit and is due to the combined non idealities from AD844s. A time-domain analysis for the BP ﬁlter is given in Figure 22 in which a sinusoidalFigure 20. A input second-order voltage withvoltage-mode 1 V peak-to-peak band-pass atfilterf = application.f 0 is applied.

Figure 21. Experimental, simulation and ideal gain responses versus frequency.

FigureFigure 21. 21.Experimental, Experimental, simulationsimulation and and ideal ideal gain gain responses responses versus versus frequency. frequency.

Figure 22. A time-domain analysis for the band-pass filter.

As it is shown in Figures 6–8 and 10–15 (SPICE simulations) as well as Figures 19, 21 and 22 (experimental verifications), the achieved time- and frequency-domain performances using the proposed SI are very close to ideal ones.

6. Conclusions A new implementation for the SI based on a single VCII± is proposed. It is composed of one VCII± ABB, two resistors and one grounded capacitor that is attractive for IC fabrication. The prominent feature of the presented work is its low series impedance. As a Figureresult, 22. it Ahas time-domain the property analysis of improved for the band-pass low-frequency filter. performances. However, it is restricted with a single resistive matching condition. To test the functionality of the pro- posedAs circuit, it is shown it is usedin Figures in the 6–8 realization and 10–15 of (SPIa standardCE simulations) fifth-order as HPwell ladder as Figures filter 19,and 21 a andsecond-order 22 (experimental BP filter. verifications),Simulation and the experime achievedntal time- results and approach frequency-domain to ideal ones perfor- but an mancesunimportant using differencethe proposed arises SI arefrom very non-idealities close to ideal of ones.the VCII±.

6. Conclusions A new implementation for the SI based on a single VCII± is proposed. It is composed of one VCII± ABB, two resistors and one grounded capacitor that is attractive for IC fabrication. The prominent feature of the presented work is its low series impedance. As a result, it has the property of improved low-frequency performances. However, it is restricted with a single resistive matching condition. To test the functionality of the proposed circuit, it is used in the realization of a standard fifth-order HP ladder filter and a second-order BP filter. Simulation and experimental results approach to ideal ones but an unimportant difference arises from non-idealities of the VCII±.

Electronics 2021, 10, x FOR PEER REVIEW 13 of 16

Figure 20. A second-order voltage-mode band-pass filter application.

Electronics 2021, 10, 1693 13 of 15

Figure 21. Experimental, simulation and ideal gain responses versus frequency.

FigureFigure 22.22. AA time-domaintime-domain analysisanalysis forfor thethe band-passband-pass ﬁlter.filter.

AsAs it is is shown shown in in Figures Figures 6–86– 8and and 10–15 Figures (SPI CE10– simulations)15 (SPICE simulations) as well as Figures as well 19, as 21 Figuresand 22 19(experimental, 21 and 22 (experimental verifications), veriﬁcations), the achieved the time- achieved and time- frequency-domain and frequency-domain perfor- performancesmances using usingthe proposed the proposed SI are SIvery are close very closeto ideal to idealones. ones.

6.6. ConclusionsConclusions AA newnew implementationimplementation for for the the SI SI based based on on a a single single VCII VCII±± isis proposed.proposed. ItIt isis composedcomposed ofof one VCII± VCII± ABB,ABB, two two resistors resistors and and one one groun groundedded capacitor capacitor that that is attractive is attractive for IC for fab- IC fabrication.rication. The The prominent prominent feature feature of the of presente the presentedd work work is its is low its series low series impedance. impedance. As a Asresult, a result, it has it the has property the property of improved of improved low-frequency low-frequency performances. performances. However, However, it is re- it isstricted restricted with with a single a single resistive resistive matching matching cond condition.ition. To test To the test functionality the functionality of the of pro- the proposedposed circuit, circuit, it is it isused used in inthe the realization realization of of a astandard standard fifth-order fifth-order HP ladder filterfilter andand aa second-order BP filter. Simulation and experimental results approach to ideal ones but an second-order BP filter. Simulation and experimental results approach to ideal ones but an unimportant difference arises from non-idealities of the VCII±. unimportant difference arises from non-idealities of the VCII±.

Author Contributions: Conceptualization, S.M. and E.Y.; methodology, E.Y. and L.S.; software, E.Y. and L.S.; validation, G.B. and E.Y.; formal analysis, E.Y., L.S. and S.M.; investigation, L.S.; resources, L.S. and G.F.; data curation, G.B. and E.Y.; writing—original draft preparation, E.Y.; writing—review and editing, G.F., S.M. and V.S.; visualization, G.B. and E.Y.; supervision, G.F., V.S. and S.M.; project administration, G.F., V.S. and S.M.; funding acquisition, G.F. and V.S. All authors have read and agreed to the published version of the manuscript. Funding: This research received no external funding. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References 1. Antoniou, A. Gyrators using operational amplifiers. Electron. Lett. 1967, 3, 350–352. [CrossRef] 2. Maundy, B.; Gift, S.J.G. Active Grounded Inductor Circuit. Int. J. Electron. 2011, 98, 555–567. [CrossRef] 3. Hamad, A.R.; Ibrahim, M.A. Grounded Generalized Impedance Converter Based on Differential Voltage Current Conveyor (DVCC) and Its Applications. ZANCO J. Pure Appl. Sci. 2017, 29, 118–127. Available online: https://zancojournals.su.edu.krd/ index.php/JPAS/article/view/1121 (accessed on 8 June 2021). 4. Yüce, E.; Minaei, S. On the Realization of Simulated Inductors with Reduced Parasitic Impedance Effects. Circuits Syst. Signal Process. 2009.[CrossRef] 5. Fabre, A. Gyrator Implementation from Commercially Available Transimpedance Operational Amplifiers. Electron. Lett. 1992, 28, 263–264. [CrossRef] 6. Yuce, E. Novel Lossless and Lossy Grounded Inductor Simulators Consisting of a Canonical Number of Components. Analog. Integr. Circuits Signal Process. 2009, 59, 77–82. Available online: https://link.springer.com/article/10.1007/s10470-008-9235-0 (accessed on 1 May 2021). 7. Yuce, E.; Minaei, S. Commercially Available Active Device Based Grounded Inductor Simulator and Universal Filter with Im- proved Low Frequency Performances. J. Circuits Syst. Comput. 2017, 26, 1750052. Available online: https://www.worldscientific. com/doi/abs/10.1142/S0218126617500529 (accessed on 1 May 2021). Electronics 2021, 10, 1693 14 of 15

8. Sedra, A.; Smith, K. A Second-Generation Current Conveyor and Its Applications. IEEE Trans. Circuit Theory 1970, 17, 132–134. [CrossRef] 9. Çiçeko˘glu, O. New Current Conveyor Based Active-Gyrator Implementation. Microelectron. J. 1998, 29, 525–528. [CrossRef] 10. Yuce, E. Grounded Inductor Simulators with Improved Low-Frequency Performances. IEEE Trans. Instrum. Meas. 2008, 57, 1079–1084. [CrossRef] 11. Soliman, A.M. New Active-Gyrator Circuit Using a Single Current Conveyer. Proc. IEEE 1978, 66, 1580–1581. [CrossRef] 12. Alpaslan, H.; Yuce, E. New Grounded Inductor Simulator Using Unity Gain Cells. Indian J. Pure Appl. Phys. 2013, 51, 651–656. 13. Yuce, E.; Alpaslan, H. New CMOS Based Current Follower and Its Applications to Inductor Simulator and Band-Pass Filter. Indian J. Pure Appl. Phys. 2016, 54, 511–516. 14. Alzaher, H. Current Follower Based Reconfigurable Integrator/Differentiator Circuits with Passive and Active Components’ Reuse. Microelectron. J. 2015, 46, 135–142. [CrossRef] 15. Arslan, E. High Performance Wideband CMOS CCI and Its Application in Inductance Simulator Design. Adv. Electr. Comp. Eng. 2012, 12, 21–26. [CrossRef] 16. Emre Arslan; Ugur Cam; Oguzhan Cicekoglu Novel Lossless Grounded Inductance Simulators Employing Only a Single First Generation Current Conveyor. Frequenz 2003, 57, 204–206. [CrossRef] 17. Kumar, P.; Senani, R. New Grounded Simulated Inductance Circuit Using a Single PFTFN. Analog Integr. Circuits Signal Process. 2010, 62, 105–112. [CrossRef] 18. Pandey, R.; Pandey, N.; Paul, S.K.; Singh, A.; Sriram, B.; Trivedi, K. Novel Grounded Inductance Simulator Using Single OTRA. Int. J. Circuit Theory Appl. 2014, 42, 1069–1079. Available online: https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.1905 (accessed on 8 June 2021). 19. Pandey, R.; Pandey, N.; Paul, S.K.; Singh, A.; Sriram, B.; Trivedi, K. New Topologies of Lossless Grounded Inductor Using OTRA. J. Electr. Comput. Eng. 2011. Available online: https://www.hindawi.com/journals/jece/2011/175130/ (accessed on 8 June 2021). 20. Gülsoy, M.; Cicekoglu, O. Lossless and Lossy Synthetic Inductors Employing Single Current Differencing Buffered Amplifier. IEICE Trans. Commun. 2005.[CrossRef] 21. Toker, A.; Acar, S. CDBA-Based Fully Integrated Gyrator Circuit Suitable for Electronically Tunable Inductance Simulation. AEU Int. J. Electron. Commun. 2000, 54, 293–296. 22. Kaçar, F. New Lossless Inductance Simulators Realization Using a Minimum Active and Passive Components. Microelectron. J. 2010, 41, 109–113. [CrossRef] 23. Kaçar, F.; Ye¸sil,A.; Minaei, S.; Kuntman, H. Positive/Negative Lossy/Lossless Grounded Inductance Simulators Employing Single VDCC and Only Two Passive Elements. AEU Int. J. Electron. Commun. 2014, 68, 73–78. [CrossRef] 24. Metin, B. Supplementary Inductance Simulator Topologies Employing Single DXCCII; Brno University of Technology: Brno, Czech Republic, 2011. 25. Kaçar, F.; Ye¸sil,A. Novel Grounded Parallel Inductance Simulators Realization Using a Minimum Number of Active and Passive Components. Microelectron. J. 2010, 41, 632–638. [CrossRef] 26. Ye¸sil,A.; Kaçar, F. New DXCCII-Based Grounded Series Inductance Simulator Topologies; Istanbul University: Istanbul,˙ Turkey, 2014. 27. Myderrizi, I.; Minaei, S.; Yuce, E. DXCCII-Based Grounded Inductance Simulators and Filter Applications. Microelectron. J. 2011, 42, 1074–1081. [CrossRef] 28. Metin, B.; Herencsar, N.; Koton, J.; Horng, J.-W. DCCII-Based Novel Lossless Grounded Inductance Simulators with No Element Matching Constrains. Radioengineering 2014, 23, 532–539. 29. Metin, B. Canonical Inductor Simulators with Grounded Capacitors Using DCCII. Int. J. Electron. 2012, 99, 1027–1035. Available online: https://www.tandfonline.com/doi/abs/10.1080/00207217.2011.639274 (accessed on 8 June 2021). 30. Herencsar, N.; Lahiri, A.; Koton, J.; Vrba, K.; Metin, B. Realization of Resistorless Lossless Positive and Negative Grounded Inductor Simulators Using Single ZC-CCCITA; Radioengineering, Czech Technical University: Praha, Czech Republic, 2012. 31. Bhaskar, D.R.; Prasad, D.; Singh, A.K. New Grounded and Floating Simulated Inductance Circuits Using Current Differencing Transconductance Amplifiers; Radioengineering, Czech Technical University: Praha, Czech Republic, 2010. 32. Srivastava, M.; Prasad, D.; Bhaskar, D. New Electronically Tunable Grounded Inductor Simulator Employing Single VDTA and One Grounded Capacitor. J. Eng. Sci. Technol. 2017, 12, 113–126. 33. Herencsar, N.; Koton, J.; Vrbra, K. CFTA-Based Active-C Grounded Positive Inductance Simulator and Its Application. Elektrore- vue 2010, 1, 24–27. Available online: http://elektrorevue.cz/en/articles/analogue-technics/0/cfta-based-active-c-grounded- positive-inductance-simulator-and-its-application-1/ (accessed on 8 June 2021). 34. Psychalinos, C.; Spanidou, A. Current Amplifier Based Grounded and Floating Inductance Simulators. AEU Int. J. Electron. Commun. 2006, 60, 168–171. [CrossRef] 35. Ye¸sil,A.; Kaçar, F.; Gürkan, K. Lossless Grounded Inductance Simulator Employing Single VDBA and Its Experimental Band-Pass Filter Application. AEU Int. J. Electron. Commun. 2014, 68, 143–150. [CrossRef] 36. Singh, A.; Kumar, P.; Senani, R. Electronically Tunable Grounded/Oating Inductance Simulators Using Z-Copy CFCCC. Turk. J. Electr. Eng. Comput. Sci. 2018, 26, 1041–1055. [CrossRef] 37. Siripongdee, S.; Jaikla, W. Electronically Controllable Grounded Inductance Simulators Using Single Commercially Available IC: LT1228. AEU—Int. J. Electron. Commun. 2017, 76, 1–10. [CrossRef] Electronics 2021, 10, 1693 15 of 15

38. Agrawal, D.; Maheshwari, S. Electronically Tunable Grounded Immittance Simulators Using an EX-CCCII. Int. J. Electron. 2020, 107, 1625–1648. Available online: https://www.tandfonline.com/doi/abs/10.1080/00207217.2020.1729421 (accessed on 8 June 2021). 39. Yesil, A.; Yuce, E.; Minaei, S. Inverting Voltage Buffer Based Lossless Grounded Inductor Simulators. AEU Int. J. Electron. Commun. 2018, 83, 131–137. [CrossRef] 40. Abaci, A.; Yuce, E. Modiﬁed DVCC Based Quadrature Oscillator and Lossless Grounded Inductor Simulator Using Grounded Capacitor(s). AEU Int. J. Electron. Commun. 2017, 76, 86–96. [CrossRef] 41. Koton, J.; Yuce, E.; Ibrahim, M.A.; Herencsar, N.; Minaei, S. Lossy/Lossless Floating/Grounded Inductance Simulation Using One DDCC; Radioengineering, Czech Technical University: Praha, Czech Republic, 2012. 42. Yuce, E.; Minaei, S. A Modiﬁed CFOA and Its Applications to Simulated Inductors, Capacitance Multipliers, and Analog Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 2008, 55, 266–275. [CrossRef] 43. Alpaslan, H.; Yuce, E. Inverting CFOA Based Lossless and Lossy Grounded Inductor Simulators. Circuits Syst. Signal Process. 2015, 34, 3081–3100. Available online: https://link.springer.com/article/10.1007/s00034-015-0004-x (accessed on 8 June 2021). 44. Yuce, E.; Minaei, S.; Cicekoglu, O. A Novel Grounded Inductor Realization Using a Minimum Number of Active and Passive Components. ETRI J 2005, 27, 427–432. [CrossRef] 45. Yuce, E.; Minaei, S.; Cicekoglu, O. Limitations of the Simulated Inductors Based on a Single Current Conveyor. IEEE Trans. Circuits Syst. I: Regul. Pap. 2006, 53, 2860–2867. [CrossRef] 46. Yuce, E. Inductor Implementation Using a Canonical Number of Active and Passive Elements. Int. J. Electron. 2007, 94, 317–326. Available online: https://www.tandfonline.com/doi/abs/10.1080/00207210701257343 (accessed on 8 June 2021). 47. Filanovsky, I.M. Current Conveyor, Voltage Conveyor, Gyrator. In Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257), Dayton, OH, USA, 14–17 August 2001; Volume 1, pp. 314–317. 48. Safari, L.; Yuce, E.; Minaei, S.; Ferri, G.; Stornelli, V. A Second-generation Voltage Conveyor (VCII)–Based Simulated Grounded Inductor. Int. J. Circuit Theory Appl. 2020, 48, 1180–1193. Available online: https://onlinelibrary.wiley.com/doi/abs/10.1002/cta. 2770 (accessed on 8 June 2021). 49. Yuce, E.; Alpaslan, H.; Minaei, S.; Ayten, U.E. A new simulated grounded inductor based on two NICs, two resistors and a grounded capacitor. Circuits Syst. Signal Process. 2021.[CrossRef] 50. Yuce, E.; Minaei, S. Universal Current-Mode Filters and Parasitic Impedance Effects on the Filter Performances. Int. J. Circuit Theory Appl. 2008, 36, 161–171. [CrossRef] 51. Fabre, A.; Saaid, O.; Wiest, F.; Boucheron, C. High Frequency Applications Based on a New Current Controlled Conveyor. IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. 1996, 43, 82–91. [CrossRef] 52. Ferri, G.; Guerrini, N.C. Low-Voltage Low-Power CMOS Current Conveyors; Springer: Berlin/Heidelberg, Germany, 2003; ISBN 978-1-4020-7486-8. 53. Toumazou, C.; Lidgey, F.J.; Haigh, D. Analogue IC Design: The Current-Mode Approach; IET: Stevenage, UK, 1993; ISBN 978-0-86341-297-4. 54. Filanovsky, I.M.; Stromsmoe, K.A. Current-Voltage Conveyor. Electron. Lett. 1981, 17, 129–130. [CrossRef] 55. Yesil, A.; Minaei, S. New Simple Transistor Realizations of Second-Generation Voltage Conveyor. Int. J. Circuit Theory Appl. 2020, 48, 2023–2038. [CrossRef] 56. Safari, L.; Barile, G.; Stornelli, V.; Ferri, G. An Overview on the Second Generation Voltage Conveyor: Features, Design and Applications. IEEE Trans. Circuits Syst. II Express Briefs 2019, 66, 547–551. [CrossRef] 57. Stornelli, V.; Safari, L.; Barile, G.; Ferri, G. A New Extremely Low Power Temperature Insensitive Electronically Tunable VCII-Based Grounded Capacitance Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 2021, 68, 72–76. [CrossRef] 58. Surakampontorn, W.; Riewruja, V.; Kumwachara, K.; Dejhan, K. Accurate CMOS-Based Current Conveyors. IEEE Trans. Instrum. Meas. 1991, 40, 699–702. [CrossRef] 59. AD844 60 MHz Monolithic Op amp. Available online: https://www.analog.com/media/en/technical-documentation/data- sheets/AD844.pdf (accessed on 1 May 2021).