Inductance Model of a Backside Integrated Power Inductor in 2.5D/3D Integration

applied sciences

Article Inductance Model of a Backside Integrated Power Inductor in 2.5D/3D Integration

Kefang Qian and Libo Qian * Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China; [email protected] * Correspondence: [email protected]

Received: 27 September 2020; Accepted: 20 November 2020; Published: 22 November 2020

Featured Application: A fully integrated power inductor using a silicon interposer is proposed, which is appropriate for miniaturized power management applications.

Abstract: Inductor integration is of vital importance for miniaturization of power supply on chips. In this paper, a backside integrated power inductor is presented. The inductor is placed at the backside of a silicon interposer and connected to the front side metal layers by through-silicon vias (TSVs) for area saving and simple fabrication. An inductance model is proposed to eﬀectively capture the total inductance of the power inductor by an analytical method. The results obtained from the analytical model and ﬁnite element method exhibit good agreement with various design parameters and the error between the proposed model and measurement remains less than 7.91%, which indicates that the proposed model can predict the inductance suitably.

Keywords: fully integrated inductor; inductance model; through-silicon vias (TSVs); mutual inductance; 3D integration

1. Introduction An inductor is a fundamental component for electronic devices, which is used for energy storage and filtering, but it dominates in size and loss. To achieve its miniaturization and aid lowering the cost of the power supply on chip, monolithic integration of power inductors is essential [1–4]. Lots of design methodologies and fabrication technologies have been proposed for potential monolithic integration. The increase in switching frequencies of power circuits up to megahertz can significantly reduce the inductor’s size [5,6]. A tiny 0.47 µH inductor has been used in a commercial 8 MHz PWM synchronous Buck regulator [5]. A 250 MHz buck regulator has been implemented with a 12 nH wire-bond power inductor in [6]. However, such a high frequency will cause high power switching and result in poor efficiency (e.g., 71% [6]). Furthermore, the power inductor with low inductance easily introduces a high ripple current. Various magnetic core materials have been adopted to enhance the inductance density for monolithic integration of power inductors [7–9]. A 3D in-silicon magnetic core toroidal inductor is presented in [7], in which the magnetic powder-based core is embedded into an air-core inductor using a casting method. A 3D solenoid inductor that is embedded in the substrate and integrated an iron core is reported in [8]. However, the introduction of magnetic material not only causes a core saturation issue but also increases the design and fabrication complexity. In this paper, a fully integrated air-core power inductor is proposed, which is developed for a high-density silicon-interposer based on 2.5D and 3D integrated circuits, and a compact analytical model has been derived to capture the total inductance of the proposed inductor, where the screw pitch and cross-sectional sharp are considered. Comparted to traditional circular coil method [10,11] and the model developed for coils with a circular section-area [12], the proposed model can offer a better

Appl. Sci. 2020, 10, 8275; doi:10.3390/app10228275 www.mdpi.com/journal/applsci Appl. Sci. 2020, 10, x FOR PEER REVIEW 2 of 8 Appl. Sci. 2020, 10, 8275 2 of 9 and the model developed for coils with a circular section-area [12], the proposed model can offer a accuracybetter accuracy and is more and suitableis more forsuitable the inductance for the induct predictionance prediction of power of inductance power inductance fabricated fabricated with 2D planarwith 2D technology. planar technology.

2.2. Inductance Inductance Model Model Description Description FigureFigure1a 1a shows shows the the cross-section cross-section schematic schematic of a silicon-interposer-basedof a silicon-interposer-based 3D IC package,3D IC package, in which in thewhich interposer the interposer acts as bridges acts as between bridges thebetween active th chipse active and printedchips and circuit printed board circuit package board [13 package,14]. In addition[13,14]. toIn theaddition interconnection, to the interconnection, the interposer the provides interposer the functionalitiesprovides the functionalities with passive componentswith passive integration.components Variousintegration. integrated Various passive integrated devices, passive such devices, as TSV such inductors, as TSV TSVinductors, capacitors TSV capacitors and TSV ﬁlters,and TSV have filters, been have presented been presented [15–17]. However,[15–17]. Howeve these studiesr, these focusstudies on focus the utilization on the utilization of tiny TSVs.of tiny TheTSVs. TSV-based The TSV-based solenoid inductorsolenoid hasinductor a low inductancehas a low inductance and is not suitable and is fornot powersuitable device for power applications. device Inapplications. this design, In a fullythis design, integrated a fully power integrated inductor power is proposed, inductor is as proposed, shown in as Figure shown1. Thein Figure proposed 1. The inductorproposed is inductor designed is to designed be placed to at be the placed backside at the of backside the interposer of the for interposer eﬃciently for utilizing efficiently the utilizing silicon areathe andsilicon can area be connectedand can be to connected the front sideto the power front circuits side power through circuits TSVs. through A thin TSVs. oxide A dielectric thin oxide is inserteddielectric between is inserted the inductorbetween andthe inductor silicon substrate and silicon to obtain substrate a high-quality to obtain a factor.high-quality factor.

(a) (b)

FigureFigure 1. 1.Schematic Schematic of of ( a(a)) the the 3D 3D IC IC package package and and ( b(b)) the the 3D 3D view view of of the the proposed proposed backside backside integrated integrated powerpower inductor. inductor.

FigureFigure2 shows2 shows the the major major fabrication fabrication steps steps of of the th proposede proposed power power inductors. inductors. Firstly, Firstly, the the via via structurestructure is is formed formed at theat the front front side side of the of interposerthe interp byoser deep by reactivedeep reactive ion etching ion etching (Figure 2(Figurea). The 2a). etched The viaetched is then via processed is then processed with an oxide with dielectric,an oxide adielectr Ta barrieric, a andTa barrier a Cu seed and layer, a Cu followed seed layer, by thefollowed acid Cu by electroplatingthe acid Cu electroplating (Figure2b). The (Figure Cu damascene 2b). The Cu technique damascene [ 18] technique is adopted [18] to fabricate is adopted the to redistribution fabricate the layersredistribution (RDLs) and layers the (RDLs) vias connecting and the vias the TSVsconnecting to the RDLsthe TSVs (Figure to the2c). RDLs The (Figure topside 2c). of the The interposer topside of waferthe interposer is temporarily wafer is bonded temporarily to a carrier bonded by to adhesive a carrier andby adhesive a back grindingand a back is grinding carriedout is carried to a few out micronsto a few to microns the TSVs to (Figurethe TSVs2d). (Figure The proposed 2d). The inductorproposed is inductor implemented is implemented by the RDLs by at the the RDLs backside at the withbackside the Cu with damascene the Cu damascene method and method the vias and connecting the vias theconnecting TSVs and the the TSVs inductor and the are inductor completed are (Figurecompleted2e). Finally,(Figure one2e). de-bondsFinally, one the de-bonds carrier wafer the carrier and assembles wafer and theassembles TSV module the TSV on module the package on the substratepackage (Figuresubstrate2f). (Figure 2f). WithWith thethe helphelp of of the the finite-element finite-element method method simulation simulation withwith HFSS HFSS software, software, thethe electricalelectrical 2 performanceperformance ofof thethe proposed backside backside integrated integrated inductor inductor with with a size a size of 1 of mm 1 mm2 is investigated.is investigated. Table Table1 provides1 provides a performance a performance comparison comparison for the for proposed the proposed backside backside integrated integrated inductor inductor with with other other state- state-of-the-artof-the-art works. works. Where Where L, QL,, Qf ,andf and RRDCDC areare the the inductor inductor inductance, qualifyqualify factor,factor,switching switching frequencyfrequency and and dc dc resistance, resistance, respectively; respectively;η is theη is inductor the inductor efficiency, efficiency, whichis which estimated is estimated by the inductor by the parametersinductor parameters and the equation and the in [19equation,20] for powerin [19,20] effi ciency.for power Since efficiency. the oxide dielectricSince the provides oxide dielectric a good isolationprovides between a good theisolation inductor between and the the silicon inductor substrate, and the it issilicon observed substrate, that theit is proposed observed inductor that the achievesproposed a higherinductor qualify achieves factor, a higher leading qualify to a peakfactor, inductor leading etoffi aciency peak inductor of 87.3% efficiency for a typical of 87.3% voltage for conversiona typical voltage ratio ofconversion 1.8 V:0.9 ratio V and of 1.8 load V:0.9 current V and of load 100 current mA. On of 100 the mA. contrary, On the substrate contrary, loss substrate and eddyloss currentand eddy loss current significantly loss significantly decrease the decrease quality and the e ffiqualityciency and of the efficiency silicon-core of the inductors silicon-core and magnetic-coreinductors and inductors. magnetic-core Furthermore, inductors. in comparison Furthermore, to the in toroidalcomparison inductor, to the the toroidal proposed inductor, embedded the inductorproposed is embedded more compatible inductor with is themore standard compatible CMOS with process. the standard CMOS process.

Appl. Sci. 2020, 10, 8275 3 of 9 Appl. Sci. 2020, 10, x FOR PEER REVIEW 3 of 8

FigureFigure 2. 2. SchematicSchematic of ofthe the major major fabrication fabrication steps steps:(:(a) viaa) via formation, formation, (b) (viab) filling, via ﬁlling, (c) RDLs (c) RDLs and vias and formation,vias formation, (d) Temporary (d) Temporary bonding bonding and backside and backside grinding, grinding, (e) inductor (e) inductor formation, formation, (f) TSV module (f) TSV assemble.module assemble.

Table 1. 1. ComparisonComparison of ofthe theproposed proposed backside backside integrat integrateded inductor inductor with the with prior the integrated prior integrated power inductors.power inductors.

L RDCRDC η InductorInductor Technology Technology L (nH) Q@fQ@f H (%) (nH) (m(mΩΩ)) (%) ThisThis work work Backside Backside integrated integrated air core air core 208 208 15@32 15@32 MHz MHz 1200 1200 87.3 87.3 SiliconSilicon embedded embedded [19][19] 2011 2011 15.815.8 [email protected]@16 MHz MHz 291 291 53.2 53.2 siliconsilicon core core In-SiIn-Si 3D toroid 3D toroid [21][21] 2018 2018 43.6743.67 9@209@20 MHz MHz 12501250 77.6 77.6 siliconsilicon core core In-SiIn-Si 3D toroid 3D toroid [8] 2019[8] 2019 229.5229.5 [email protected]@5 MHz MHz 20002000 55.2 55.2 magneticmagnetic core core In-SiIn-Si 3D toroid 3D toroid [7] 2019[7] 2019 112112 [email protected]@12.5 MHz MHz 265265 90.7 90.7 magneticmagnetic core core

BasedBased onon thethe above above structure, structure, the resistance–inductance–capacitancethe resistance–inductance–capacitanc (RLC)e (RLC) model ofmodel the backside of the backsideintegrated integrated inductor caninductor be established. can be established. Considering Considering that the inductance that the inductance is one of the is critical one of parametersthe critical parametersfor inductors for in inductors power management in power management applications, applications, this work focuses this work on thefocuses modeling on the and modeling analysis and of analysisthe inductance of the inductance of the proposed of the inductor.proposed Forinductor. the basis For analysis,the basis itanalysis, is assumed it is assumed that the trackthat the width track is widthw, the trackis w, spacingthe track is spacings and the is track s and thickness the track is tthickness. The linked is t flux. The of linked the inductor flux of determined the inductor its determinedinductance. its For inductance. a one-turn inductor,For a one-turn the overall inductor, inductance the overall of the inductance inductor is equalof the toinductor its self-inductance. is equal to itsFor self-inductance. multi-turn inductors, For multi-turn there is mutualinductors, coupling there is between mutual eachcoupling turn, between and then each the turn, magnetic and then field thestrength magnetic through field the strength inductor through and the the linked inductor flux an significantlyd the linked increases flux significantly with the number increases of with turns, the as numbershown in of Figure turns,3 .as Therefore, shown in theFigure overall 3. Therefore, inductance the of overall the inductor inductance is the sumof the of inductor the self-inductance is the sum ofand the increased self-inductance mutual inductanceand increased between mutual each induct turnance [22]. between For the proposedeach turn Archimedean[22]. For the spiralproposed coil Archimedeanwith a rectangular spiral cross coil section with a area rectangular and n concentric cross section turns, thearea total and inductance n concentricLT canturns, be writtenthe total as T S M inductancethe sum over L thecan self-inductance be written as theLS sumand over the mutual the self-inductance inductance L ML ofand all the turns, mutual inductance L of all turns, Xn Xn = + = +nn LT ==+LS LM LS Mij (1) LLLLT SM+ Si=1 j=1 M ij (1) ij==11

where Mij represent the mutual inductance between the ith turn coil and jth turn coil. The overall where Mij represent the mutual inductance between the ith turn coil and jth turn coil. The overall self- self-inductance LS can be further approximated as a function of coil geometry [23], inductance LS can be further approximated as a function of coil geometry [23], ! ! μµleng 2leng w + t LS = llenglog2 eng + 0.5 + wt+ (2) L =×2π × logw + t ++ 0.5 3leng S π + (2) 23wt leng Appl. Sci. 2020, 10, 8275 4 of 9

Appl. Sci. 2020, 10, x FOR PEER REVIEW 4 of 8 7 where leng is the total length of the n-turn coil, and µ = 4π 10 H/m is the permittivity of × − wherethe surrounding leng is the medium.total length For of an the Archimedean n-turn coil, spiral and coilμ = with4π × an 10 inner−7 H/m radius is theR0 permittivityand screw pitch of thep (p surrounding= w + s), leng medium.can be calculated For an Archimedean by spiral coil with an inner radius R0 and screw pitch p (p = w + s), leng can be calculated by 2 ns π !2 Z × p p 2 2π×n θ22 leng = R0pp+θ + dθ (3) lR= ++2π 2π dθ (3) eng 0  0 ππ 0 22

(a) (b)

FigureFigure 3. 3. MagneticMagnetic field ﬁeld strength strength in in (a (a) )a a one-turn one-turn coil coil and and (b (b) )a a two-turn two-turn coil. coil.

TheThe mutual inductanceinductanceM Mij canij can be calculatedbe calculated using using the classical the classical magnetic magnetic vector potential vector potential approach approachas [22,24– as26 ][22,24–26] → → µ0 dli ×dlj Mij =μ dl×ij dl (4) M = 0 4π R (4) ij 4π  R For an Archimedean spiral coil, the tangent vector of point P (Ricosθ1, Risinθ1, 0) on the ith coil

andFor point anQ Archimedean(Rjcosθ2, Rjsin spiralθ2, 0) coil, on thethe jtangentth coil can vector be derived of point as P (Ricosθ1, Risinθ1, 0) on the ith coil and point Q (Rjcosθ2, Rjsinθ2, 0) on the jth coil can be derived as  → → →  dli= dxi i + dy i j   +  dlii= dxip dy i j  = (cos θ θ sin θ )→i + (sin θ + θ cos θ )→j dθ   2π 1 − 1 1 1 1 1 1  p  (5)   → =−++→θθ→ θ θθ θ θ  dl = dx i +(cosdy j11 sin 1 )ijd (sin 11 cos 1 ) 1   j πj j  2p   = (cos θ  θ sin θ )→i + (sin θ + θ cos θ )→j dθ (5)  2π + 2 2 2 2 2 2 2 dljj= dx i dy j j−  and then p   =(cossin)(sincos)θθ2−++" θijd θθ# θ θ → → p22(1+θ1 2θ2) cos(θ2 22θ1) 2 2  dl2i π dlj = − − dθ1dθ2 (6) × 4π2 (θ θ ) sin(θ θ ) 2 − 1 2 − 1 and then The distance between two points P and Q can be expressed as 2 ()()θθ θ− θ r p 1+12 cos 2 1 - × 2 θθ2 dlij dl= 2  d12 d (6) R = Rj cos4πθ2 ()()Rθθi cos−−θ1 + θθRj sin θ2 Ri sin θ1 (7) −21sin 21−

TheSubstituting distance between Equation two (5)–Equation points P and (7) intoQ can Equation be expressed (4), M asij can be obtained as

2 22 µ0RRp =+(1+()()θ1cosθ2)θθcos - R(θ cos2 θ1) (θ R2 sinθ θθ1) -sin R sin(θ2 θ1 ) (7) M = ji21− − ji− 2− 1dθ dθ (8) ij 3 q 1 2 16π 2 2 Ri + Rj 2RiRj cos(θ2 θ1) Substituting Equation (5)–Equation (7) into Equation− (4), M−ij can be obtained as μ 2 ()()()()θθ θθ−− θθ θθ − p 1+12 cos 21 - 21 sin 21 M = 0 ddθθ ij 16π 3  22 ()θθ 12 (8) RRij+-2cos- RR ij 21 Appl. Sci. 2020, 10, x FOR PEER REVIEW 5 of 8

Substituting Equations (3) and (8) into Equation (1), the total inductance of the proposed Archimedean coil can be calculated.

3. Validation and Discussion Appl. Sci. 2020, 10, 8275 5 of 9 In this section, the inductances obtained from the proposed model, the traditional circular coil method (CCM), quasi-static electromagnetic simulation with Q3D, are compared [26]. Q3D is a fast- quasi-staticSubstituting electromagnetic Equations (3)field and simulator (8) into and Equation is good (1), at the RLCG total parameter inductance extraction. of the proposed For the Archimedeanproposed power coil inductor can be calculated. with the inductance of ~1 μH, its switching frequency would not exceed 3.100 Validation MHz. Therefore, and Discussion Q3D can provide an accurate inductance extraction for the proposed power inductor. In the simulation environment, the two terminals of the inductor are defined as a source and Insink, this respectively, section, the and inductances the AC RL obtained solver are from adopted the proposed for inductance model, extraction. the traditional In the circularcircular coilcoil methodmethod (CCM),[10,11], each quasi-static loop is electromagneticapproximated as simulationa circle and with the radius Q3D, are of the compared ith turn[ 26is ].treated Q3D as is aR0 fast-quasi-static + (i−1)p. The base electromagnetic parameters are ﬁeldw = 40 simulator μm, t = 20 and μm, is s good = 20 μ atm, RLCG R0 = 20 parameter μm and n extraction.= 26. As shown For thein Figure proposed 4, the power inductances inductor with thethe inductanceproposed mo ofdel ~1 µ agreeH, its well switching with the frequency results wouldof 3D notsimulators exceed 100over MHz. various Therefore, design parameters: Q3D can provide the error an with accurate respect inductance to the EM extraction results is forless thethan proposed 9.5%, while power the inductor.error of the In thetraditional simulation circular environment, coil method the is two 40.2%. terminals The comparison of the inductor indicates are deﬁned that the as proposed a source andmodel sink, can respectively, be used for andinductance the AC RLextraction solver are of adoptedthe fully forintegrated inductance power extraction. inductor. In the circular coil methodFurthermore, [10,11], each the loop results is approximated in Figure 4a,b asdemonstrate a circle and that the L radiusT increases of the withith turnthe track is treated width as wR and0 + (i 1)p. The base parameters are w = 40 µm, t = 20 µm, s = 20 µm, R = 20 µm and n = 26. As shown in track− spacing s, due to the increased partial self-inductance and0 mutual inductance according to FigureEquations4, the (2) inductances and (8). Since with the the variation proposed in partia modell self-inductance agree well with and the resultsmutual of inductance 3D simulators with overtrack variousthickness design t is little, parameters: it can be theseen error in Figure with respect 4c that tothe the impact EM results of the isparameter less than 9.5%,on LT whilecan be the negligible. error of theMoreover, traditional the circularresults in coil Figure method 4d isshow 40.2%. the The overall comparison inductance indicates would that increase the proposed with the model inner canradius be usedof the for inductor. inductance extraction of the fully integrated power inductor.

(a) (b)

FigureFigure 4.4. ImpactImpact of of (a (a) )track track width, width, (b ()b track) track spacing, spacing, (c) ( ctrack) track thickness thickness and and (d) (innerd) inner radius radius on the on thetotal total inductance. inductance.

Furthermore, the results in Figure4a,b demonstrate that LT increases with the track width w and track spacing s, due to the increased partial self-inductance and mutual inductance according to Equations (2) and (8). Since the variation in partial self-inductance and mutual inductance with track thickness t is little, it can be seen in Figure4c that the impact of the parameter on LT can be negligible. Appl. Sci. 2020, 10, 8275 6 of 9

Moreover, the results in Figure4d show the overall inductance would increase with the inner radius of the inductor. Appl. Sci.Table 20202 ,investigates 10, x FOR PEER the REVIEW computational e ﬃciency of the model by comparing the simulation6 time of 8 of the proposed analytical model and 3D EM simulator using the parameters listed. The simulation Table 2 investigates the computational efficiency of the model by comparing the simulation time was performed on an Intel i5 core with a processor speed of 3.0 GHz and 8 GB of RAM. It was found of the proposed analytical model and 3D EM simulator using the parameters listed. The simulation that lots of computational time can be saved using the proposed model. was performed on an Intel i5 core with a processor speed of 3.0 GHz and 8 GB of RAM. It was found that lots of computational timeTable can 2. beComparison saved using of computational the proposed e ﬃmodel.ciency.

StructureTable 2. Comparison This of Modelcomputational 3Defficiency. EM Simulator

r1 = Structure50 µm, n = 10 This 0.03 Model s 3D EM 69.7Simulator s rr11 = 5050 µμm,m, nn= = 1510 0.03 0.07 s 69.7 76.0 s s

r1r1= = 10050 μµm,m, n = 15 0.07 0.08 s 76.0 73.0 s s 1 rr1 =100100 µμm,m,n n= =26 15 0.08 0.29 s 73.0 86.6 s s r1 = 100 μm, n = 26 0.29 s 86.6 s r1 = 100 µm, n = 37 0.41 s 117.0 s r1 = 100 μm, n = 37 0.41 s 117.0 s

To verify the the accuracy accuracy of of the the analytical analytical expr expressions,essions, the the proposed proposed model model was was applied applied to the to thefabricated fabricated power power inductors. inductors. Taking Taking into into account account th thee additional additional process process steps steps for for the the 3D 3D integration and the weak impact of the interposer materials on the inductor’s performance, the proposed power inductor was fabricatedfabricated withwith 2-layer2-layer PrintPrint CircuitCircuit BoardBoard (PCB)(PCB) technology.technology. In the emulated 3D integration environment shown in Figure 55a,a, thethe inductorinductor isis realizedrealized onon thethe backsidebackside planarplanar track.track. The viasvias inin the the PCB PCB technology technology imitate imitate the the TSVs TSVs to connect to connect the inductor the inductor to the frontsideto the frontside power circuits.power Tablecircuits.3 compares Table 3 compares the inductances the inductances obtained from obtained this model, from this the model, circular the coil circular method coil (CCM) method [ 10, 11(CCM)] and electrical[10,11] and measurement electrical measurement with a Hioko with IM3570 a Hioko Impedance IM3570 Analyzer.Impedance By Analyzer. connecting By the connecting two terminals the two of theterminals inductor of tothe the inductor two probes to the of the two impedance probes of analyzer, the impedance capable ofanalyzer, measurement capable frequencies of measurement of 4 Hz tofrequencies 5 MHz, the of inductance4 Hz to 5 MHz, at 1 MHz the caninductance be captured. at 1 MHz It is observed can be captured. that the proposedIt is observed model that shows the aproposed higher accuracy model shows in comparison a higher accuracy to CCM. in The comparison maximum to error CCM. and The average maximum error error of the and proposed average modelerror of are the 7.91% proposed and 3.72%,model respectively,are 7.91% and which 3.72%, indicates respectively, the feasibility which indicates of the proposedthe feasibility model of the for inductanceproposed model prediction. for inductance prediction.

(a) (b)

Figure 5. (a) Schematic view of the fabricated power inductor and (b) its experimental setup.setup.

Table 3. Comparison of the inductance results.

Size This Model CCM Measurement Error Inductance Error Inductance Inductance (nH) (%) (nH) (%) (nH) r1 = 3 mm, n = 4 196.7 −2.64 182.2 −9.81 202 r1 = 3 mm, n = 6 452.6 1.72 425.2 −4.40 445 r1 = 3 mm, n = 8 814.6 1.96 796.4 −0.33 799 r1 = 3 mm, n = 16 3725 6.29 4023.6 14.82 3504.4 r1 = 6 mm, n = 4 419.1 −1.84 404.5 −5.27 427 r1 = 6 mm, n = 6 931.1 2.56 888.2 −2.18 908 r1 = 6 mm, n = 8 1635.3 4.62 1574.6 0.74 1563 r1 = 6 mm, n = 16 6500 7.91 6749.2 12.05 6023.6 Appl. Sci. 2020, 10, 8275 7 of 9

Table 3. Comparison of the inductance results.

Size This Model CCM Measurement Inductance Error Inductance Error Inductance (nH) (%) (nH) (%) (nH) r = 3 mm, n = 4 196.7 2.64 182.2 9.81 202 1 − − r = 3 mm, n = 6 452.6 1.72 425.2 4.40 445 1 − r = 3 mm, n = 8 814.6 1.96 796.4 0.33 799 1 − r1 = 3 mm, n = 16 3725 6.29 4023.6 14.82 3504.4 r = 6 mm, n = 4 419.1 1.84 404.5 5.27 427 1 − − r = 6 mm, n = 6 931.1 2.56 888.2 2.18 908 1 − r1 = 6 mm, n = 8 1635.3 4.62 1574.6 0.74 1563

r1 = 6 mm, n = 16 6500 7.91 6749.2 12.05 6023.6 r = 10 mm, n = 4 725.1 5.96 742.9 3.64 771 1 − − r = 10 mm, n = 6 1608.6 0.21 1594.6 1.08 1612 1 − − r1 = 10 mm, n = 10 4320.8 4.06 4256.9 2.53 4152

r1 = 10 mm, n = 20 16200 5.49 17,269 12.45 15,357

4. Conclusions In this paper, a power inductor integration technology for 2.5D/3D integrated power management applications is presented and experimentally demonstrated. The inductor can be integrated at the backside of the silicon interposer and interconnects with the frontside power circuits with TSVs. A compact and accurate inductance model is developed to capture the overall inductance of the proposed inductor. A comparison with 3D EM results shows that the proposed analytical model has a good prediction capability and a high computational eﬃciency. Furthermore, the model results show that the increase in track width, track spacing and inner radius of the inductor would increase the overall inductance, while the variation in the inductance with track thickness is less. Finally, the inductance from the proposed model and the measurements were compared, and an error of less than 7.91% was obtained.

Author Contributions: Conceptualization, K.Q.; methodology, K.Q.; validation, K.Q and L.Q.; formal analysis, K.Q and L.Q.; investigation, K.Q.; resources, K.Q.; data curation, K.Q.; writing—original draft preparation, K.Q.; writing—review and editing, K.Q and L.Q.; supervision, L.Q.; project administration, L.Q.; funding acquisition, L.Q. All authors have read and agreed to the published version of the manuscript. Funding: This work was supported by the National Natural Science Foundation of China under Grants 61771268, U1709218 and the K.C. Wong Magna Fund in Ningbo University. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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