applied sciences Article Inductance Model of a Backside Integrated Power Inductor in 2.5D/3D Integration Kefang Qian and Libo Qian * Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China; [email protected] * Correspondence: [email protected] Received: 27 September 2020; Accepted: 20 November 2020; Published: 22 November 2020 Featured Application: A fully integrated power inductor using a silicon interposer is proposed, which is appropriate for miniaturized power management applications. Abstract: Inductor integration is of vital importance for miniaturization of power supply on chips. In this paper, a backside integrated power inductor is presented. The inductor is placed at the backside of a silicon interposer and connected to the front side metal layers by through-silicon vias (TSVs) for area saving and simple fabrication. An inductance model is proposed to effectively capture the total inductance of the power inductor by an analytical method. The results obtained from the analytical model and finite element method exhibit good agreement with various design parameters and the error between the proposed model and measurement remains less than 7.91%, which indicates that the proposed model can predict the inductance suitably. Keywords: fully integrated inductor; inductance model; through-silicon vias (TSVs); mutual inductance; 3D integration 1. Introduction An inductor is a fundamental component for electronic devices, which is used for energy storage and filtering, but it dominates in size and loss. To achieve its miniaturization and aid lowering the cost of the power supply on chip, monolithic integration of power inductors is essential [1–4]. Lots of design methodologies and fabrication technologies have been proposed for potential monolithic integration. The increase in switching frequencies of power circuits up to megahertz can significantly reduce the inductor’s size [5,6]. A tiny 0.47 µH inductor has been used in a commercial 8 MHz PWM synchronous Buck regulator [5]. A 250 MHz buck regulator has been implemented with a 12 nH wire-bond power inductor in [6]. However, such a high frequency will cause high power switching and result in poor efficiency (e.g., 71% [6]). Furthermore, the power inductor with low inductance easily introduces a high ripple current. Various magnetic core materials have been adopted to enhance the inductance density for monolithic integration of power inductors [7–9]. A 3D in-silicon magnetic core toroidal inductor is presented in [7], in which the magnetic powder-based core is embedded into an air-core inductor using a casting method. A 3D solenoid inductor that is embedded in the substrate and integrated an iron core is reported in [8]. However, the introduction of magnetic material not only causes a core saturation issue but also increases the design and fabrication complexity. In this paper, a fully integrated air-core power inductor is proposed, which is developed for a high-density silicon-interposer based on 2.5D and 3D integrated circuits, and a compact analytical model has been derived to capture the total inductance of the proposed inductor, where the screw pitch and cross-sectional sharp are considered. Comparted to traditional circular coil method [10,11] and the model developed for coils with a circular section-area [12], the proposed model can offer a better Appl. Sci. 2020, 10, 8275; doi:10.3390/app10228275 www.mdpi.com/journal/applsci Appl. Sci. 2020, 10, x FOR PEER REVIEW 2 of 8 Appl. Sci. 2020, 10, 8275 2 of 9 and the model developed for coils with a circular section-area [12], the proposed model can offer a accuracybetter accuracy and is more and suitableis more forsuitable the inductance for the induct predictionance prediction of power of inductance power inductance fabricated fabricated with 2D planarwith 2D technology. planar technology. 2.2. Inductance Inductance Model Model Description Description FigureFigure1a 1a shows shows the the cross-section cross-section schematic schematic of a silicon-interposer-basedof a silicon-interposer-based 3D IC package,3D IC package, in which in thewhich interposer the interposer acts as bridges acts as between bridges thebetween active th chipse active and printedchips and circuit printed board circuit package board [13 package,14]. In addition[13,14]. toIn theaddition interconnection, to the interconnection, the interposer the provides interposer the functionalitiesprovides the functionalities with passive componentswith passive integration.components Variousintegration. integrated Various passive integrated devices, passive such devices, as TSV such inductors, as TSV TSVinductors, capacitors TSV capacitors and TSV filters,and TSV have filters, been have presented been presented [15–17]. However,[15–17]. Howeve these studiesr, these focusstudies on focus the utilization on the utilization of tiny TSVs.of tiny TheTSVs. TSV-based The TSV-based solenoid inductorsolenoid hasinductor a low inductancehas a low inductance and is not suitable and is fornot powersuitable device for power applications. device Inapplications. this design, In a fullythis design, integrated a fully power integrated inductor power is proposed, inductor is as proposed, shown in as Figure shown1. Thein Figure proposed 1. The inductorproposed is inductor designed is to designed be placed to at be the placed backside at the of backside the interposer of the for interposer efficiently for utilizing efficiently the utilizing silicon areathe andsilicon can area be connectedand can be to connected the front sideto the power front circuits side power through circuits TSVs. through A thin TSVs. oxide A dielectric thin oxide is inserteddielectric between is inserted the inductorbetween andthe inductor silicon substrate and silicon to obtain substrate a high-quality to obtain a factor.high-quality factor. (a) (b) FigureFigure 1. 1.Schematic Schematic of of ( a(a)) the the 3D 3D IC IC package package and and ( b(b)) the the 3D 3D view view of of the the proposed proposed backside backside integrated integrated powerpower inductor. inductor. FigureFigure2 shows2 shows the the major major fabrication fabrication steps steps of of the th proposede proposed power power inductors. inductors. Firstly, Firstly, the the via via structurestructure is is formed formed at theat the front front side side of the of interposerthe interp byoser deep by reactivedeep reactive ion etching ion etching (Figure 2(Figurea). The 2a). etched The viaetched is then via processed is then processed with an oxide with dielectric,an oxide adielectr Ta barrieric, a andTa barrier a Cu seed and layer, a Cu followed seed layer, by thefollowed acid Cu by electroplatingthe acid Cu electroplating (Figure2b). The (Figure Cu damascene 2b). The Cu technique damascene [ 18] technique is adopted [18] to fabricate is adopted the to redistribution fabricate the layersredistribution (RDLs) and layers the (RDLs) vias connecting and the vias the TSVsconnecting to the RDLsthe TSVs (Figure to the2c). RDLs The (Figure topside 2c). of the The interposer topside of waferthe interposer is temporarily wafer is bonded temporarily to a carrier bonded by to adhesive a carrier andby adhesive a back grindingand a back is grinding carriedout is carried to a few out micronsto a few to microns the TSVs to (Figurethe TSVs2d). (Figure The proposed 2d). The inductorproposed is inductor implemented is implemented by the RDLs by at the the RDLs backside at the withbackside the Cu with damascene the Cu damascene method and method the vias and connecting the vias theconnecting TSVs and the the TSVs inductor and the are inductor completed are (Figurecompleted2e). Finally,(Figure one2e). de-bondsFinally, one the de-bonds carrier wafer the carrier and assembles wafer and theassembles TSV module the TSV on module the package on the substratepackage (Figuresubstrate2f). (Figure 2f). WithWith thethe helphelp of of the the finite-element finite-element method method simulation simulation withwith HFSS HFSS software, software, thethe electricalelectrical 2 performanceperformance ofof thethe proposed backside backside integrated integrated inductor inductor with with a size a size of 1 of mm 1 mm2 is investigated.is investigated. Table Table1 provides1 provides a performance a performance comparison comparison for the for proposed the proposed backside backside integrated integrated inductor inductor with with other other state- state-of-the-artof-the-art works. works. Where Where L, QL,, Qf ,andf and RRDCDC areare the the inductor inductor inductance, qualifyqualify factor,factor,switching switching frequencyfrequency and and dc dc resistance, resistance, respectively; respectively;η is theη is inductor the inductor efficiency, efficiency, whichis which estimated is estimated by the inductor by the parametersinductor parameters and the equation and the in [19equation,20] for powerin [19,20] effi ciency.for power Since efficiency. the oxide dielectricSince the provides oxide dielectric a good isolationprovides between a good theisolation inductor between and the the silicon inductor substrate, and the it issilicon observed substrate, that theit is proposed observed inductor that the achievesproposed a higherinductor qualify achieves factor, a higher leading qualify to a peakfactor, inductor leading etoffi aciency peak inductor of 87.3% efficiency for a typical of 87.3% voltage for conversiona typical voltage ratio ofconversion 1.8 V:0.9 ratio V and of 1.8 load V:0.9 current V and of load 100 current mA. On of 100 the