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Energy-Harvesting Systems for Green Computing

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Energy-Harvesting Systems for Green Computing JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 10, NO. 4, DECEMBER 2012 291 Energy-Harvesting Systems for Green Computing Terrence Mak (Invited paper) Abstract⎯Energy harvesting technologies provide a interfaces and specific communication channels. Although promising alternative to battery-powered systems and the self-powered system can be produced by plugging create an opportunity to achieve sustainable computing together individual components, the overall system for the exploitation of ambient energy sources. However, sustainability, in terms of energy utilization and energy harvesting devices and power generators computational efficiency, is relatively low. Sustainability is encompass a number of non-classical system behaviors crucial, especially, at the era of continuing progress and or characteristics, such as delivering nondeterministic massive integration in silicon technologies. Applications, power density, and these would create hindrance for such as health monitoring systems, distributed sensors, effectively utilizing the harvested energy. Previously, we portable communication, and entertainment systems, have investigated new design methods and tools that are demand high reliability and sustainability from power used to enable power adaptive computing and, dissipation. Sustainable computing with good power particularly, catering non-deterministic voltage, which efficiency must be addressed from various abstraction can efficiently utilize ambient energy sources. Also, we layers that include system design, processor architecture, developed a co-optimization approach to maximize the power adaptors, and energy harvesting power sources. computational efficiency from the harvested ambient Traditional battery-powered systems work under energy. This paper will provide a review of these limited energy supply. For applications requiring long methods. Emerging technologies, such as 3D-IC, which working duration, much effort has been devoted to energy would also enable new paradigm of green and efficient or low-power system design. With advances in high-performance computing, will be also discussed. energy harvesting technologies, it is possible to implement a self-powered system that harvests ambient energy from Index Terms⎯Energy harvesting, green computing, the environment. Particularly, harvesters provide a three-dimensional-integrated circuit (3D-IC) design. spectrum of power delivery that subjects to various environmental conditions and systematic volumes, 1. Introduction including solar, electromagnetic, mechanical piezoelectric vibration, and so on. This enables a new opportunity to Recent advancements in microelectromechanical electronic architecture design and methodology innovation (MEMS) technology present and apply novel design and for the exploitation of ambient energy source. This paper manufacturing processes that enable the integration of reviews two design methods to handle variable voltage self-powered devices, whose energy is harvested from the sources from energy harvesting devices and to optimize the environment, in micro-packages and integrated circuits. ambient energy utilization for computing. Also, emerging Much study has been carried out to improve the energy technologies, such as three-dimensional-integrated circuit [1]−[4] harvesting efficiency . Such energy harvesting systems (3D-IC), and its implication on green computing will be provide a promising alternative to battery-powered systems discussed. The area of energy harvesting electronic is and create opportunities for architecture and design calling for new techniques and paradigm of design for innovation for the exploitation of an ambient energy source. utilizing ambient energy effectively. Previous work on energy harvester systems focuses on individual components design. Many research groups have designed and prototyped at subsystem-level with unique 2. Voltage Sensor for Variable Voltage Dynamic adaptation is crucial to energy harvesting circuits because the harvester power efficiency can be Manuscript received September 7, 2012; revised October 22, 2012. This work was supported by the National Natural Science Foundation of China maximized by varying the computational loads according to under Grant No. 61176025 and No. 61006027. the scavenged energy at run-time. To achieve this goal, a T. Mak is with the Department of Computer Science and Engineering, sensor circuit is needed to measure the supplied power from The Chinese University of Hong Kong, Hongkong, China. He is also the harvester in order to schedule activities in the affiliated with Guangzhou Institute of Advanced Technology, Chinese computational circuitry. A challenge is that this sensor Academy of Sciences, Guangzhou 511458, China (e-mail: stmak@cse. cuhk.edu.hk). needs also to be powered by the same harvester, where the Digital Object Identifier: 10.3969/j.issn.1674-862X.2012.04.002 power supply is either unreliable or unstable in terms of its 292 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 10, NO. 4, DECEMBER 2012 V voltage levels. Another problem is that stable and known dd Load voltage or current references, a prerequisite of most Energy Stop the conversion Vdd traditional voltage measurement devices, generally do not and latch the outputs [5] Harvesting t +t exist in such an operating environment . Previously, we generator charging conversion S propose an approach to voltage sensing, which we call 3 E Sampling circuit energy-proportionality. It is based on the use of a sampling EN capacitor, which converts power supply voltage to an Digital Vdd amount of energy in the form of a charge stored on this DC/DC Vin Charge-to-digital code converter S C converter capacitor, plus a charge-to-digital converter that provides 1 sample S2 reliable conversion of the stored energy to a binary code on Vdd [6] the output . In this method, electric charge in the sampling t conversion capacitor is converted to the binary code in a single step. Voltage sensor An asynchronous counter is designed to act as both an Energy availability Vdd oscillator and a counter, thereby combining the two main tcharging Controller functionalities in one circuit: converting charge to Task schedule frequency and integrating frequency to codes. It is crucial that every signal transition in the asynchronous counter Fig. 1. System consists of a voltage sensor that samples charge contributes to the formation of the output code from the from the main energy supply and stores it in a small capacitor. sensor, and each such transition consumes a certain quantum of energy taken from the sampling capacitor. Thus, C=15p,T=5us 150150 C=15 pF, T=5 μs the switching activity and output of the counter virtually CC=15p,T=2us=15 pF, T=2 μs becomes proportional to the input energy “invested” into CC=15p,T=500ns=15 pF, T=500 ns this computation. This constitutes what we call energy- proportional computing. Output count Output count count Output Fig. 1 shows a general architecture of the proposed 0 0 voltage sensor circuit in a system depending on harvested 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Initial voltage V (V) energy. A sensing round starts with the charging of the dd (a) sampling capacitor (Csample) from the Vdd being sensed. The result amount of charge on this capacitor is uniformly 140 CC=12p,T=5us=12 pF, T=5 μs 140 related to the Vdd. This capacitor’s voltage will be used as CC=12p,T=2us=12 pF, T=2 μs input to the asynchronous counter circuit.The capacitor is CC=12p,T=500ns=12 pF, T=500 ns then discharged for some time by using the energy in its Output count Output charge to perform some quantifiable work. The amount of Output count 00 work completed reflects the sampled charge (and the V dd 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 value at the time of sampling). In this design an Initial voltage Vdd (V) asynchronous counter counts the pulses generated by itself (b) to record its amount of work. The sampling circuit in Fig. 1 CC=10p,T=5us=10 pF, T=5 μs works in two states. In the first or charging state S is on 100 1 100 CC=10p,T=2us=10 pF, T =2 μs and S2 is off. Csample is charged to Vdd−Vs1, where Vs1 is the CC=10p,T=500ns=10 pF, T =500 ns voltage drop across S1. This state should be long enough to fully charge the sampling capacitor (tcharging). In the second Output count Output count count Output or conversion state (tconversion) S1 is off and S2 is on. In this 00 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 state V , which is V −V −V , where V is the voltage 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 in dd s1 s2 s2 Initial Voltage (Vdd) Initial voltage Vdd (V) drop across S2, is applied to the load counter. In this design (c) S3 is used to bypass the sampling circuit at the end of the conversion time. At this time, the counter stops counting Fig. 2. Output count versus input voltage for three different values and latches the output. Not shown in the figure, the end of of capacitor and three different time lengths of sampling and conversion T=5 μs, 2 μs, and 500 ns, respectively: (a) C=15 pF, (b) conversion should also discharge Csample readying it for the next sensing round. C=12 pF, and (c) C=10 pF. Fig. 2 depicts the value of the output count for three different sampling capacitor values with three different The design of a voltage sensor for energy harvesting output time choices (T=tcharging+tconversion) over a range of circuits based on a charge-to-digital converter is presented. voltages (Vdd=[0, 1V]). This figure shows two slightly Simple design of the proposed voltage sensor frees it up different slopes on each individual curve. The reason is that from the requirement for a stable reference voltage or dramatic decrease in on to off currents (Ion/Ioff) in current.
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