Techniques to Measure, Model, and Manage Power

CHAPTER TWO Techniques to Measure, Model, and Manage Power Bhavishya Goel, Sally A. McKee, and Magnus Själander Computer Science and Engineering, Chalmers University of Technology, 412 96 Gothenburg, Sweden Contents 1. Introduction 8 2. Problem Statement 10 3. Empirical Power Measurement 12 3.1 Measurement Techniques 13 3.1.1 At the Wall Outlet 13 3.1.2 At the ATX Power Rails 14 3.1.3 At the Processor Voltage Regulator 17 3.2 Experimental Results 19 3.3 Further Reading 22 4. Power Estimation 23 4.1 Power Modeling Techniques 24 4.1.1 Performance Monitoring Counters 24 4.1.2 PMC Access 25 4.1.3 Counter Selection 26 4.1.4 Model Formation 32 4.2 Secondary Aspects of Power Modeling 34 4.2.1 Temperature Effects 34 4.2.2 Effects of Dynamic Voltage and Frequency Scaling 37 4.2.3 Effects of Simultaneous Multithreading 38 4.3 Validation 39 5. Power-Aware Resource Management 42 5.1 Sample Policies 44 5.2 Experimental Setup 45 5.3 Results 46 5.4. Further Reading 48 6. Discussion 49 References 50 Advances in Computers, Volume 87 © 2012 Elsevier Inc. ISSN 0065-2458, http://dx.doi.org/10.1016/B978-0-12-396528-8.00002-X All rights reserved. 7 8 Bhavishya Goel et al. Abstract Society’s increasing dependence on information technology has resulted in the deployment of vast compute resources. The energy costs of operating these resources coupled with environmental concerns have made energy-aware computing one of the primary challenges for the IT sector. Making energy-efficient computing a rule rather than an exception requires that researchers and system designers use the right set of techniques and tools. These involve measuring, analyzing, and controlling the energy expenditure of computers at varying degrees of granularity. In this chapter, we present techniques to measure power consumption of computer systems at various levels and to compare their effectiveness. We discuss methodologies to estimate processor power consumption using performance-counter-based power modeling and show how the power models can be used for power-aware scheduling. Armed with such techniques and methodologies, we as a research and development community can better address challenges in power-aware management. 1. INTRODUCTION Green Computing has become much more than a buzz phrase. The greening of the Information and Communication Technology (ICT) sector has grown into a significant movement among manufacturers and service providers. Even end users are rising to the challenge of creating a green society and sustainable environment in which our development and use of information technology can still flourish. Environmental legisla- tion and rising operational and waste disposal costs obviously lend force to this movement, but so do public perceptions and corporate images. For instance, environmental concerns have a growing impact on the ICT industry’s products and services, and they increasingly influence the choices that ICT organizations make (environmental criteria are now among the top buying criteria for ICT-related goods and services). Most ICT providers now prioritize choices that reduce long-term, negative environmental impact instead of just reducing operational costs. Over a computing system’s lifetime, the array of costs includes design, verification, manufacturing, deployment, operation, maintenance, retirement, disposal, and recycling. All of these include an ICT component, themselves. Green ICT thus spans: • environmental risk mitigation; • green metrics, assessment tools, and methodologies; • energy-efficient computing and power management; • data center design and location; • environmentally responsible disposal and recycling; and • legislative compliance. Techniques to Measure, Model, and Manage Power 9 Murugesan notes that each personal computer in use in 2008 was responsible for generating about a ton of carbon dioxide per year [33]. In 2007–2008, multiple independent studies calculated the global ICT footprint to be 2% [50] of the total emissions from all human activity. While the growing ICT sector’s global emissions will continue to rise (by a pro- jected 6% per annum through the year 2020 [50]), increases in products and services and advances in technology will potentially bring about greater reductions in other sectors. The implications of Green Computing thus reach far beyond the ICT sector itself. One factor in this growing carbon footprint is the steadily increasing amount of total electrical energy expended by ICT. As computer system architects, the obvious first step that system designers can take toward addressing the larger problem of total emissions footprint is to reduce operational power consumption. Although power efficiency is but one aspect of this multifaceted environmental problem, the design of more power-efficient systems will help inform solutions that impact other aspects. The most robust solutions are likely to come from hardware/ software codesign to create hardware that provides more real-time power consumption information to software that can leverage that information to save power throughout the system. Until such combined solutions exist, though, we still need to reduce power consumption of existing platforms. This chapter discusses an approach to achieving this reduction for current systems. Power-aware resource management requires introspection into the dynamic behavior of the system. In Section 2, we first discuss some of the challenges to obtaining this information. Our solution is to use performance monitoring counters (PMCs). Such counters are nearly ubiquitous in current platforms, and they provide the best available introspection into computational and system activity. We use PMC values to build per-core power consumption models that can then be used to generate power estimates to drive resource management decisions. For such models to be useful, we must verify their accuracy, which requires a means to measure dynamic power consumption. In Section 3, we thus describe a set of power-measurement techniques and discuss their pros and cons with respect to their use in better resource management. In Section 4, we set the context by surveying previous power modeling work before explaining our methodology in detail. In Section 5, we present a case study of power management techniques that leverage this methodology. 10 Bhavishya Goel et al. 2. PROBLEM STATEMENT Power consumption has joined performance as a first-class metric for dictating system design and performance specifications [32]. Efficient use of available system resources requires balancing power consumption and performance requirements. To make power-aware decisions, system resource managers require real-time information about power consumption and temperature, preferably at the granularity of individual resources. In a chip multiprocessor (CMP), power consumption for different cores may vary widely, depending on the properties of the code they execute. Armed with information about power usage, task schedulers, hypervisors, and operating systems can make better decisions for how to execute a given workload efficiently. Unfortunately, most available hardware lacks the on-die infrastructure for sensing current consumption, largely due to the hardware costs and the intrusive nature of the sensing techniques. Even when such sensing capabilities exist, the information they provide is rarely made available to software. For example, the Intel® Core™ i7 [14] processor employs power monitoring hardware on-chip to enable its Turbo Boost technology. But this interface is only available to and used only by the hardware for selectively and temporarily increasing chip performance. External power meters can be used to measure total system power. Digital multimeters can be used to further isolate CPU power from system power, but their use requires access to the power rails coming out of the power sup- ply unit (PSU). Intel’s Node Manager [19] can be used in combination with certain Intel® Xeon® processors to measure power and to control power dissipation. This technique can report both system-wide as well as processor and memory system power consumption. However, the above techniques lack functionality to provide power consumption at the granularity of devices, such as cores, integer units, floating-point units, or caches. Intel’s Sandy Bridge microarchitecture can measure power at the core level [38]. Their power-measurement techniques are based on the same methodology as pre- sented in this chapter. They use microarchitectural events that are multiplied with energy weights and then summed together to form the power of a core or of the complete CPU. This technique does not provide insights into power dissipation, as it is proprietary, and only the end result can be read from software. Furthermore, it is limited to a specific processor model. System simulators [10] are used at design time to obtain detailed and decomposable information about component power consumption. Most of the architectural power models used in such simulators are prone to error [22], Techniques to Measure, Model, and Manage Power 11 and thus obtaining accurate power models for off-the-shelf commercial processors can be difficult, even impossible. Furthermore, simulators suffer very long running times. Finally, these tools must be used offline, and they provide little useful information for online power estimation of arbitrary applications. A viable alternative is to create power models that can be computed in real time and whose results can be made available to the appropriate software

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