Welcome to CSE467! Highlights
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Welcome to CSE467! Highlights: Course Staff: Bruce Hemingway and Charles Giefer We'll be reading hand-outs and papers from various sources. Course web:http://www.cs.washington.edu/467/ The course work will be built around an embedded-core processor in an FPGA. My office: CSE 464 Allen Center, 206 543-6274 Tools are Active-HDL from Aldec, Synplify, and Xilinx ISE. Today: Course overview Languages are verilog and C. What is computer engineering? Applications in the FPGA will include some audio. What we will cover in this class What is “design”, and how do we do it? You may do this week’s lab at your own time. Basis for FPGAs The project- audio string model CSE467 1 CSE467 2 What is computer engineering? What we will cover in CSE467 CE is not PC design Basic digital design (much of it review) It includes PC design Combinational logic Truth tables & logic gates CE is not necessarily digital design Logic minimization Analog computers Special functions (muxes, decoders, ROMs, etc.) Real-world (analog) interfaces Sequential logic CE is about designing information-processing systems Flip-flops and registers Computers Clocking Networks and networking HW Synchronization and timing State machines Automation/controllers (smart appliances, etc.) Counters Medical/test equipment (CT scanners, etc.) State minimization and encoding Much, much more Moore vs Mealy CSE467 3 CSE467 4 What we will cover (con’t) CSE467 is about design Advanced topics Design is an art Field-programmable gate arrays (FPGAs) You learn by doing Multilevel logic High-speed design Takes years of practice HDLs and synthesis This class is a starting point Verilog Synthesizing to an FPGA Engineering is learning how to solve problems Re-usable code modules-- IP Independent of any specific technology Lab equipment Independent of any specific tools Oscilloscopes Logic analyzers Imagination is more important than knowledge – Einstein An audio design project CSE467 5 CSE467 6 1 Example: Design an encryptor One round (iteration) of DES DES This block represents one of the 16 Input is clear-text (or plain-text) iteration steps Output is cipher-text Same algorithm encrypts and Standard DES operates on 64-bit decrypts blocks (eight 8-bit bytes) Details IP is initial permutation The key is 56 bits L is left-half of message K1 – K16 are 16 permutations R is right half of message on the master key 16 iterations on the message Use lookup tables for the K are keys f is a function (next slide) permutations and substitutions –1 IP is an inverse permutation CSE467 7 CSE467 8 DES in hardware Hardware DES Standard DES algorithm Options are Turns a 64-bit message block into a 64-bit cipher Discrete logic (fixed-function ICs) block PLDs & discrete logic Electronic Code Book (ECB) mode Microprocessor / microcontroller / DSP Each 64-bit block is encrypted independently FPGA Imagine you have to design a fast encryptor Semicustom ASIC For a continuous data stream Custom IC e.g. satellite communications or wireless LAN or ... How do you choose? How would you implement DES? CSE467 9 CSE467 10 DES with discrete logic? PLDs? DES using a µP How? How? Large PCB Use COTS development system Discrete FSM Or a custom PCB with µP, memory, firmware, glue logic Leverage PLDs Advantages Advantages Easy to change algorithm or fix design errors (rewrite None firmware) Disadvantages Low design cost High parts cost Disadvantages Many ICs High parts cost Complex PCB Slow throughput High design cost Serial execution Slow throughput Hard to change algorithm CSE467 or fix design errors 11 CSE467 12 2 FPGA primer DES using an FPGA CLB Architecture Idealized FPGA How? PCB with one or several FPGAs Include glue logic in FPGAs Advantages Easy to change algorithm or fix design errors (resynthesize logic) Moderate throughput Pipelined logic; 25 – 75 MHz clock Disadvantages Moderate parts cost Okay for small production runs Moderate design cost CSE467 13 CSE467 14 DES using an ASIC DES as a custom IC How? How? A single ASIC--Include glue logic A single custom IC Advantages Include glue logic in IC Fast throughput Pipelined logic Advantages 50 – 300 MHz clock Ultra-fast throughput Low parts cost for volume production Pipelined, tuned logic Moderate design cost 200 – 1000 MHz clock Debug using FPGAs Low cost for volume production LSI Logic G10 ASIC design flow Synthesize to an ASIC Disadvantages Disadvantages Difficult to change algorithm or fix design errors Redesign chip Difficult to change algorithm or fix design errors Long, slow, expensive design process Redesign chip CSE467 15 CSE467 16 FPGA Basics A Simple Programmable Function Field PROGRAMMABLE Gate Array Adapted from: The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) CSE467 17 CSE467 18 3 Unprogrammed Fusible Links Programmed Fusible Links CSE467 19 CSE467 20 Unprogrammed antifuse links Programmed antifuse links CSE467 21 CSE467 22 A Transistor-based mask- Growing an anti-fuse programmed ROM cell CSE467 23 CSE467 24 4 A Transistor-and-fusible- link-based PROM cell Standard MOS versus EPROM transistors CSE467 25 CSE467 26 An EPROM transistor-based memory cell Intel 1702A EPROM die, circa 1971- 256x8 CSE467 27 CSE467 28 An SRAM-based programmable cell CSE467 29 CSE467 30 5 Summary of Programming Technologies What you will do Implement physical model of a vibrating string in a Xilinx FPGA Xilinx development board PC design environment-- Active-HDL, Synplify Verilog and Xilinx ISP toolset Microblaze soft processor-- example of IP You won’t learn end-to-end design Starting with problem statement Ending with product You will experience design You will implement an algorithm in hardware You will create your own design implementation CSE467 31 CSE467 32 6.