USOO6157976A United States Patent (19) 11 Patent Number: 6,157,976 Tien et al. (45) Date of Patent: Dec. 5, 2000

54 PCI-PCI BRIDGE AND PCI- AUDIO OTHER PUBLICATIONS ACCELERATOR INTEGRATED CIRCUIT PCI System Architecture, Tom Shanley/Don Anderson, 75 Inventors: Paul Tien, Fremont; Cheng-Yeuan 1995, pp. 381-382. Tsay, Pleasanton; Rsong-Hsiang Shiao, Fremont, all of Calif. Primary Examiner Ayaz R. Sheikh Assistant Examiner Rupal D. Dharia 73 Assignee: ESS Technology, Fremont, Calif. Attorney, Agent, or Firm-Gray Cary Ware & Freidenrich 57 ABSTRACT 21 Appl. No.: 09/074,657 A semiconductor device with an embedded PCI 2.1 com 22 Filed: May 6, 1998 pliant bridge provides expanded functionality as System 51511 Int. Cl...... GO6F13FOO700; GO6F 13/38/ level implementationsp of a PCI-to-PCI bridge,9. and enhances 52 U.S. Cl...... 710/129, 710/127, 710/64; the level of integration possible. The embedded PCI-to-PCI 345/435; 84/604; 84/621; 84/622; 84/647 bridge allows the creation of multi-function, multimedia 58) Field of Search 345/435: 710/127 add-on cards Supporting multiple devices. Multi-function, 710129,6484/602,604 621 622 647. multimedia Subsystems that provide audio, graphics, MPEG, s w is s s 454. 70425s etc., are mapped into a bridged-to PCI-bus that keeps Such s traffic off the main PCI-bus. The advantage for the system or 56) References Cited add-in card Vendor is that the various multimedia chips that are combined can come from different Sources, providing an U.S. PATENT DOCUMENTS optimized and highly customized combination of functions. 5,689,080 11/1997 Gulick ...... 84/604 5,909,559 6/1999 So ...... 710/127 1 Claim, 2 Drawing Sheets

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79 6,157,976 1 2 PC-PCI BRIDGE AND PCI-BUS AUDIO accesses for execution by a PCI-bus interrupt controller ACCELERATOR INTEGRATED CIRCUIT mapped into a PCI-bus memory resource. Briefly, a circuit embodiment of the present invention FIELD OF THE INVENTION comprises a PCI-PCI bridge core integrated on the same The present invention relates to digital electronic circuits, chip as a PCI-bus audio accelerator. and more particularly to personal PCI-bus SyS An advantage of the present invention is that more temS. functionality can be implemented on both PCI-bus add-in cards and motherboards. DESCRIPTION OF THE PRIOR ART These and other objects and advantages of the present The peripheral component interface (PCI) bus has become invention will no doubt become obvious to those of ordinary the interface bus of choice for high-Speed devices because it skill in the art after having read the following detailed is well-equipped to handle newer, more demanding appli description of the preferred embodiments which are illus cations with its 32-bit data path, 33 MHz clock speed and a trated in the various drawing figures. maximum data transfer rate of 132 MB/sec. 15 IN THE DRAWINGS However, PCI loading constraints limit the number of devices that can be Supported directly on a System mother FIG. 1 is a functional block diagram of a PC system board or through expansion slots, so PCI-to-PCI bridge embodiment of the present invention; and chips have been developed by a number of major Suppliers FIG. 2 is a function block diagram of an audio accelerator to increase the number of available System expansion slots. with an auxiliary integrated PCI-PCI bridge core. Embedding a bridge in a Semiconductor device that also Supplies other functionality provides a higher degree of DETAILED DESCRIPTION OF THE integration and enables the creation of multi-function, mul PREFERRED EMBODIMENT timedia expansion cards, where a single add-in card could FIG. 1 illustrates a (PC) embodiment Support audio, graphics acceleration and Video conferenc 25 of the present invention, referred to herein by the general ing. reference numeral 10. The PC 10 comprises a microproces The PCI bus is typically isolated from the CPU local bus sor (CPU) 12, a system controller (Northbridge “NB”) 14, by a PCI controller, a so-called “Northbridge”. The CPU can and a peripheral component interconnect (PCI) bus 16. A thereby write data to PCI peripherals and go on to its next peripheral-bus controller (Southbridge “SB') 18 provides a operation rather than waiting for the transfer to complete. bridge to Several buses including an industry Standard archi The PCI controller stores the data in its buffer, and sends it tecture (ISA) bus 20. APCI-bus audio accelerator peripheral out later at the most efficient rate. 22 includes a PCI-bus resident audio accelerator 24 and a The PCI-buS Supports intelligent-device , So PCI-PCI bridge 26 both integrated as cores on the same other masters can take control of the bus and do their jobs 35 integrated circuit (IC). The PCI-PCI bridge 26 provides independent of the CPU. The CPU can run in parallel with more slots on a secondary PCI-bus 28 for a plurality of the bus master peripheral because of the buffered design. input-output (I/O) controllers 30. The number of PCI peripheral devices that can be Sup The PCI bus is the ideal medium for utilization as a ported by a single PCI-bus is based on the electrical loading multimedia interface due to its high bandwidth, Support for constraints defined in the industry-standard “PCI 2.1 Speci 40 bus mastering, and low demands on CPU capacity. By using fication'. A compliant PCI-bus is capable of Supporting a the PCI bus as a multimedia bridge, multimedia Subsystems total of ten loads, and two loads are consumed by the basic can be designed on a adapter, e.g., PCI-bus , PCI chipset associated with the CPU. PC-device controllers for different target markets. The high level of integration that are built into the motherboard present only a single load. achieved by using embedded PCI-to-PCI technology is A Single PCI-buS can therefore only Support four expan 45 valuable where motherboard form factors decreased in size Sion slots without violating the Specification's loading and yet the number of multimedia functions expand. constraints, e.g., one PCI device per expansion slot. High In one embodiment, the System controller 14 comprises end System designers have recently begun to build Systems an Advanced Micro-Devices (Sunnyvale, Calif.) AMD-640 using PCI-to-PCI bridges to provide more expansion slots system controller (“Northbridge") has a 64-bit Socket-7 on the motherboard. The PCI bus specifications provide for 50 interface, integrated writeback cache controller, System an automatic configuration of any adapter or peripheral memory controller, and PCI bus controller. Such Socket-7 plugged into the bus to eliminate conflicts between boards in interface is optimized for the AMD-K6 processor, providing the System and the need for jumper headers on a board. 3-1-1-1-1-1-1-1 transfer timing for both read and write transactions from PBSRAM at 66 MHz. (The number SUMMARY OF THE INVENTION 55 sequence refers to the CPU clock “t” cycles for each operation, i.e., 3-1-1-1 means the first data will be available It is therefore an object of the present invention to provide at the third “t” when issue the operation, then the conse a System for Supporting ISA-bus applications Software on a quence data only need additional one “t cycle, and So on.) PCI-based hardware system. The AMD-640's internal memory controller has a data It is a further object of the present invention to provide a 60 buffering design that uses four cache lines, e.g., Sixteen controller that accepts ISA-bus inter quadwords, of processor-to-DRAM or cache-to-DRAM rupt controller commands and accesses and that translates write buffering with concurrent writeback capability to these into PCI-bus equivalent interrupt controller commands accelerate writeback and write-miss cycles. The integrated and accesses. PCI bus controller does concurrent processor and PCI opera It is a still further object of the present invention to 65 tion with a five-doubleword buffer. PCI con emulate an ISA-bus interrupt controller that accepts and currency with DRAM or cache memory is achieved through responds to direct memory acceSS controller commands and a 48-doubleword post write buffer and 26-doubleword 6,157,976 3 4 prefetch buffer. -merging is used to optimize processor now been resolved by vendors such as ESS Technology to-PCI throughput and reduce PCI bus traffic by converting through hardware legacy Support. ESS Technology's consecutive processor addresses into burst PCI cycles. The solution, Transparent DMA, creates a virtual ISA bus that AMD-640 system controller uses a variety of techniques to interfaces with the PCI bus. The expense of the first wavet minimize PCI initiator read and DRAM access, able Synthesis devices has also now been driven down, in including Snoop ahead, Snoop filtering, forwarding cache part through the use of techniques Such as downloadable writebacks to the PCI initiator, and merging L1 writebacks Sound fonts that also enhance performance. into the PCI-posted write buffers to minimize PCI initiator The first PC audio solutions utilized read latency and DRAM utilization. To minimize Snoop ROM to Store the Sound Samples needed to generate Sound. overhead, the integrated PCI controller Supports enhanced The ROM was expensive and limited the number of sounds PCI bus commands, Such as memory-read-line, memory that a wavetable engine could produce. Also, because the read-multiple, and memory-write-invalidate. The combina audio Samples were loaded by the hardware device vendor, tion allows a PCI initiator to achieve the full 133-Mbps burst the software developer had no control over how their transfer rate. application would Sound with a given vendor's wavetable In another embodiment, the peripheral-bus controller 18 15 hardware accelerator. comprises an AMD-645 peripheral bus controller ESS Technology's PC audio solutions utilize the high (“Southbridge”). The AMD-645 has an integrated ISA bus bandwidth PCI bus and WaveCaches8 technology to store controller, enhanced master mode PCI EIDE controller with MIDI sound samples in a PC's main memory. The down Ultra DMA/33 technology, an ACPI-compatible power man loadable sound samples saves the cost of ROM and allows agement unit, a USB controller, a PS2-compatible keyboard/ a Software developer to determine precisely how their title mouse controller, and a real-time clock (RTC) with extended will sound on every system that utilizes downloadable sound 256-byte CMOS RAM. The on-chip EIDE controller has a fonts. dual-channel DMA engine capable of interlaced dual FIG. 2 illustrates a PCI-bus audio accelerator peripheral channel commands. High-bandwidth PCI transfers are 50 that is similar to the audio accelerator peripheral 22 of achieved by a sixteen double-word data FIFO with full 25 FIG. 1. The PCI-bus audio accelerator peripheral 50 com scatter and gather capability. The integrated USB controller prises a PCI-interface 52, a SOUNDBLASTER datapath 54, has a root hub with two ports having 18-level-deep data a wave processor 56, a 512x16 wave cache 58, an applica FIFOs and built-in transceivers. tion specific signal processor (ASSP) 60, a ring bus 62, a The AMD-645 peripheral bus controller is marketed as SIO-2 codec 64, a SIO-1 codec 66, and an IS serial meeting (R 95 Plug-and-Play require interface 68. A high-performance (HPGP) 70 ments with steerable PCI interrupts, ISA interrupts, and provides an interface for a joystick, and a general purpose DMA channels. The integrated power management unit is input-output port (GPI/0) 72 provides connections to mul compliant with ACPI and APM and provides dedicated input tiplexed buses. A PCI-PCI bridge 74 serves to expand the pins for external modem ring indication and power-on, five 35 number of PCI-bus peripheral cards that the PCI-CPU 12 general-purpose I/O pins with option for I2C port, and can address. Sixteen general-purpose pins that can be programmed as The wave processor 56 is a dual-engine, Sixty-four inputs or outputs. To manage power management events, the channel, pipelined wave processor. The ASSP 60 is a pro AMD-645 controller includes an ACPI power management grammable audio signal processor. Together these provide timer, a GPO timer, a GP1 timer, a secondary event timer, 40 Simultaneous Support for multiple audio Streams of different and a conserve mode timer. Two types of Sleep States, e.g., types. Such architecture enables complex, three-dimension Soft-off and power-on Suspend, are Supported with hardware positional gaming Sound effects to be implemented while automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling, hardware and Software also Supporting voice communications over the Internet based event handling, and multiple external SMI Sources. from multiple Sources. Embodiments of the present inven 45 tion preferably Support Sixty-four independently program The PCI-bus audio accelerator peripheral 22 or PCI mable wave processor channels and provide for DIRECT expansion card may comprise an ESS Technology (Fremont, SOUND(R) hardware acceleration with digital mixing of up Cailf.) PCI audio accelerator chip, e.g., marketed as to thirty-two wave Streams. Audio Streams of any frequency MAESTRO-1TM. At a minimum, the PCI-bus audio accel are converted to forty-eight kHz. Each of the sixty-four erator peripheral 22 is preferably compliant with major 50 channels can be assigned its own parameters to control industry Standards including the Audio Subsystem Specifi panning, tremolo, , and tone-filtering. The channels cation of PC97, Windows 95 DirectSoundTM, Windows also Support independently programmable Special effects, Sound System, AC'97 CODEC Interface, and the PCI 2.1 e.g., reverb, chorus, flange, echo, and three-dimension Spa Bus Specification. tial enhancements to create positional Special effects. The The Maestro-1 is a dual audio-engine architecture that 55 high bandwidth PCI-bus is used to store MIDI-samples in comprises of a 64-voice, pipelined, wavetable main memory. Downloadable Sound Samples relieve need and a programmable audio signal processor that can Simul ing ROM-type memory to store sound fonts, a allow soft taneously handle multiple audio Streams of different data ware developers to control the Sound PCI-bus audio accel types, high-quality Synthesis, and Voice compression eratorS. and decompression. Wavetable technology uses algorithms 60 A more obvious advantage that the PCI bus brings to to frequency Shift a stored digitized Sound Sample of the audio applications is sheer bandwidth. At 133 MB/second, instrument playing to create the various notes, tones and the PCI bus represents a much larger “pipe” than the 7 octaves of a performance MB/second ISA bus. In addition to being able to move large Market acceptance of early PC wavetable sound solutions amounts of data quickly through the bus, PCI accelerators was hampered by a lack of compatibility with Software 65 are able to transfer multiple data streams with different developed for the SOUNDBLASTER standard and the high destinations during a Single bus master cycle. Because PCI cost of the first implementations. Software compatibility has audio accelerators can Support multiple data Streams of 6,157,976 S 6 different types, it can also reduce the latencies typically neously handle multiple audio Streams of different data asSociated with Internet-based interactive audio, phone and types, high-quality music Synthesis, and Voice com conferencing applications. pression and decompression, wherein Said wavetable Although the present invention has been described in includes algorithms for frequency shifting Stored digi terms of the presently preferred embodiments, it is to be tized Sound Samples of an instrument playing to create understood that the disclosure is not to be interpreted as a variety of notes, tones and octaves of a performance; limiting. Various alterations and modifications will no doubt wherein the PCI-bus resident audio accelerator core (24) become apparent to those skilled in the art after having read further comprises: the above disclosure. Accordingly, it is intended that the an application specific signal processor (ASSP) (60) appended claims be interpreted as covering all alterations implemented as a programmable audio-signal pro and modifications as fall within the true Spirit and Scope of the invention. cessor that combines with said wave processor (56) What is claimed is: for providing Simultaneous Support for multiple 1. An audio accelerator peripheral (50), comprising: audio Streams of different types, and 15 a wave cache (58) connected to both said ASSP (60) a single integrated circuit (IC) having a PCI-interface (52) and said wave processor (56), and for providing for providing a limited PCI-bus loading to a primary temporary Storage of memory data downloaded from PCI-bus (16); said primary PCI-bus (16) that is later provided a PCI-bus resident audio accelerator core (24) disposed in on-demand to said wave processor (56); and the IC that includes a SOUNDBLASTER-type datap wherein said wave processor (56) and ASSP (60) combine ath (54) connected between said PCI-interface (52) and to enable complex, three-dimension positional gaming a wave processor (56) for creating a virtual ISA bus Sound-effects, and Support Sixty-four independently interfaced with said primary PCI-bus (16); and programmable wave processor channels for a PCI-PCI bridge core (26,74) disposed in the IC and DIRECTSOUND-type hardware acceleration with providing an interface between said PCI-interface (52) 25 digital mixing of up to thirty-two wave Streams, and and a secondary PCI-bus (28) for a plurality of expan wherein audio streams of any frequency are converted sion input-output (I/O) controllers (30); to forty-eight kHz, and each of Sixty-four channels can wherein the PCI-bus resident audio accelerator core (24) be assigned their own parameters to control panning, includes a dual audio-engine architecture with a tremolo, Vibrato, and tone-filtering. 64-voice, pipelined, wavetable Synthesizer, and a pro grammable audio signal processor that can Simulta k k k k k