United States Patent (19) 11 Patent Number: 6,157,976 Tien Et Al
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USOO6157976A United States Patent (19) 11 Patent Number: 6,157,976 Tien et al. (45) Date of Patent: Dec. 5, 2000 54 PCI-PCI BRIDGE AND PCI-BUS AUDIO OTHER PUBLICATIONS ACCELERATOR INTEGRATED CIRCUIT PCI System Architecture, Tom Shanley/Don Anderson, 75 Inventors: Paul Tien, Fremont; Cheng-Yeuan 1995, pp. 381-382. Tsay, Pleasanton; Rsong-Hsiang Shiao, Fremont, all of Calif. Primary Examiner Ayaz R. Sheikh Assistant Examiner Rupal D. Dharia 73 Assignee: ESS Technology, Fremont, Calif. Attorney, Agent, or Firm-Gray Cary Ware & Freidenrich 57 ABSTRACT 21 Appl. No.: 09/074,657 A semiconductor device with an embedded PCI 2.1 com 22 Filed: May 6, 1998 pliant bridge provides expanded functionality as System 51511 Int. Cl. ............................. GO6F13FOO700; GO6F 13/38/ level implementationsp of a PCI-to-PCI bridge,9. and enhances 52 U.S. Cl. ............................ 710/129, 710/127, 710/64; the level of integration possible. The embedded PCI-to-PCI 345/435; 84/604; 84/621; 84/622; 84/647 bridge allows the creation of multi-function, multimedia 58) Field of Search 345/435: 710/127 add-on cards Supporting multiple devices. Multi-function, 710129,6484/602,604 621 622 647. multimedia Subsystems that provide audio, graphics, MPEG, s w is s s 454. 70425s etc., are mapped into a bridged-to PCI-bus that keeps Such s traffic off the main PCI-bus. The advantage for the system or 56) References Cited add-in card Vendor is that the various multimedia chips that are combined can come from different Sources, providing an U.S. PATENT DOCUMENTS optimized and highly customized combination of functions. 5,689,080 11/1997 Gulick ....................................... 84/604 5,909,559 6/1999 So ........................................... 710/127 1 Claim, 2 Drawing Sheets 1O 14 2 PC-bus 22 (10 max) 2 loads each PC I/O controllers U.S. Patent Dec. 5, 2000 Sheet 1 of 2 6,157,976 ZZ 0|| |-61 8? SnG-1Od ?oeespeolz U.S. Patent 6,157,976 99 JOSS300/d?Ae^w ZA. 79 6,157,976 1 2 PC-PCI BRIDGE AND PCI-BUS AUDIO accesses for execution by a PCI-bus interrupt controller ACCELERATOR INTEGRATED CIRCUIT mapped into a PCI-bus memory resource. Briefly, a circuit embodiment of the present invention FIELD OF THE INVENTION comprises a PCI-PCI bridge core integrated on the same The present invention relates to digital electronic circuits, chip as a PCI-bus audio accelerator. and more particularly to personal computer PCI-bus SyS An advantage of the present invention is that more temS. functionality can be implemented on both PCI-bus add-in cards and motherboards. DESCRIPTION OF THE PRIOR ART These and other objects and advantages of the present The peripheral component interface (PCI) bus has become invention will no doubt become obvious to those of ordinary the interface bus of choice for high-Speed devices because it skill in the art after having read the following detailed is well-equipped to handle newer, more demanding appli description of the preferred embodiments which are illus cations with its 32-bit data path, 33 MHz clock speed and a trated in the various drawing figures. maximum data transfer rate of 132 MB/sec. 15 IN THE DRAWINGS However, PCI loading constraints limit the number of devices that can be Supported directly on a System mother FIG. 1 is a functional block diagram of a PC system board or through expansion slots, so PCI-to-PCI bridge embodiment of the present invention; and chips have been developed by a number of major Suppliers FIG. 2 is a function block diagram of an audio accelerator to increase the number of available System expansion slots. with an auxiliary integrated PCI-PCI bridge core. Embedding a bridge in a Semiconductor device that also Supplies other functionality provides a higher degree of DETAILED DESCRIPTION OF THE integration and enables the creation of multi-function, mul PREFERRED EMBODIMENT timedia expansion cards, where a single add-in card could FIG. 1 illustrates a personal computer (PC) embodiment Support audio, graphics acceleration and Video conferenc 25 of the present invention, referred to herein by the general ing. reference numeral 10. The PC 10 comprises a microproces The PCI bus is typically isolated from the CPU local bus sor (CPU) 12, a system controller (Northbridge “NB”) 14, by a PCI controller, a so-called “Northbridge”. The CPU can and a peripheral component interconnect (PCI) bus 16. A thereby write data to PCI peripherals and go on to its next peripheral-bus controller (Southbridge “SB') 18 provides a operation rather than waiting for the transfer to complete. bridge to Several buses including an industry Standard archi The PCI controller stores the data in its buffer, and sends it tecture (ISA) bus 20. APCI-bus audio accelerator peripheral out later at the most efficient rate. 22 includes a PCI-bus resident audio accelerator 24 and a The PCI-buS Supports intelligent-device bus mastering, So PCI-PCI bridge 26 both integrated as cores on the same other masters can take control of the bus and do their jobs 35 integrated circuit (IC). The PCI-PCI bridge 26 provides independent of the CPU. The CPU can run in parallel with more slots on a secondary PCI-bus 28 for a plurality of the bus master peripheral because of the buffered design. input-output (I/O) controllers 30. The number of PCI peripheral devices that can be Sup The PCI bus is the ideal medium for utilization as a ported by a single PCI-bus is based on the electrical loading multimedia interface due to its high bandwidth, Support for constraints defined in the industry-standard “PCI 2.1 Speci 40 bus mastering, and low demands on CPU capacity. By using fication'. A compliant PCI-bus is capable of Supporting a the PCI bus as a multimedia bridge, multimedia Subsystems total of ten loads, and two loads are consumed by the basic can be designed on a adapter, e.g., PCI-bus expansion card, PCI chipset associated with the CPU. PC-device controllers for different target markets. The high level of integration that are built into the motherboard present only a single load. achieved by using embedded PCI-to-PCI technology is A Single PCI-buS can therefore only Support four expan 45 valuable where motherboard form factors decreased in size Sion slots without violating the Specification's loading and yet the number of multimedia functions expand. constraints, e.g., one PCI device per expansion slot. High In one embodiment, the System controller 14 comprises end System designers have recently begun to build Systems an Advanced Micro-Devices (Sunnyvale, Calif.) AMD-640 using PCI-to-PCI bridges to provide more expansion slots system controller (“Northbridge") has a 64-bit Socket-7 on the motherboard. The PCI bus specifications provide for 50 interface, integrated writeback cache controller, System an automatic configuration of any adapter or peripheral memory controller, and PCI bus controller. Such Socket-7 plugged into the bus to eliminate conflicts between boards in interface is optimized for the AMD-K6 processor, providing the System and the need for jumper headers on a board. 3-1-1-1-1-1-1-1 transfer timing for both read and write transactions from PBSRAM at 66 MHz. (The number SUMMARY OF THE INVENTION 55 sequence refers to the CPU clock “t” cycles for each operation, i.e., 3-1-1-1 means the first data will be available It is therefore an object of the present invention to provide at the third “t” when issue the operation, then the conse a System for Supporting ISA-bus applications Software on a quence data only need additional one “t cycle, and So on.) PCI-based hardware system. The AMD-640's internal memory controller has a data It is a further object of the present invention to provide a 60 buffering design that uses four cache lines, e.g., Sixteen direct memory access controller that accepts ISA-bus inter quadwords, of processor-to-DRAM or cache-to-DRAM rupt controller commands and accesses and that translates write buffering with concurrent writeback capability to these into PCI-bus equivalent interrupt controller commands accelerate writeback and write-miss cycles. The integrated and accesses. PCI bus controller does concurrent processor and PCI opera It is a still further object of the present invention to 65 tion with a five-doubleword posted write buffer. PCI con emulate an ISA-bus interrupt controller that accepts and currency with DRAM or cache memory is achieved through responds to direct memory acceSS controller commands and a 48-doubleword post write buffer and 26-doubleword 6,157,976 3 4 prefetch buffer. Byte-merging is used to optimize processor now been resolved by vendors such as ESS Technology to-PCI throughput and reduce PCI bus traffic by converting through hardware legacy Support. ESS Technology's consecutive processor addresses into burst PCI cycles. The solution, Transparent DMA, creates a virtual ISA bus that AMD-640 system controller uses a variety of techniques to interfaces with the PCI bus. The expense of the first wavet minimize PCI initiator read latency and DRAM access, able Synthesis devices has also now been driven down, in including Snoop ahead, Snoop filtering, forwarding cache part through the use of techniques Such as downloadable writebacks to the PCI initiator, and merging L1 writebacks Sound fonts that also enhance performance. into the PCI-posted write buffers to minimize PCI initiator The first wavetable synthesis PC audio solutions utilized read latency and DRAM utilization. To minimize Snoop ROM to Store the Sound Samples needed to generate Sound.