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Intel® Chipsets Low Pin Count Interface Specification

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Intel® Chipsets Low Pin Count Interface Specification R Intel® Low Pin Count (LPC) Interface Specification August 2002 Revision 1.1 Document Number: 251289-001 Introduction R Information in this document is provided in connection with Intel® products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of informa tion in this specification.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein, except that a li cense is hereby granted to copy and reproduce this specification for internal use only. Intel may have patents and/or patent applications related to the various Low Pin Count interfaces described in the Low Pin Count (LPC) Interface Specification, Revision 1.1. A reciprocal, royalty-free license to the electrical interfaces and bus protocols described in, and required by, the Low Pin Count (LPC) Interface Specification, Revision 1.1 is available from Intel. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2002, Intel Corporation 2 251289-001 Introduction R Contents 1 Introduction........................................................................................................................ 7 1.1 Goals of the LPC Interface (I/F) ............................................................................ 7 1.2 Assumptions and Functionality Requirements...................................................... 7 1.3 Terminology .......................................................................................................... 8 2 Signal Definition................................................................................................................. 9 3 Block Diagram ................................................................................................................. 11 4 Protocol Overview ........................................................................................................... 13 4.1 Cycle Types ........................................................................................................ 13 4.2 Memory, I/O, and DMA Cycle Overview ............................................................. 14 4.2.1 LAD[3:0]............................................................................................... 14 4.2.1.1 START................................................................................ 15 4.2.1.2 Cycle Type / Direction (CYCTYPE + DIR) .......................... 15 4.2.1.3 SIZE ................................................................................... 16 4.2.1.4 Turn-Around (TAR)............................................................. 16 4.2.1.5 ADDR ................................................................................. 16 4.2.1.6 CHANNEL .......................................................................... 16 4.2.1.7 DATA.................................................................................. 16 4.2.1.8 SYNC ................................................................................. 17 4.2.1.9 SYNC Time-out .................................................................. 17 4.2.1.10 SYNC Error Indication ........................................................ 18 4.2.1.11 LFRAME#........................................................................... 18 4.2.1.12 Start of Cycle...................................................................... 19 4.2.1.13 Abort Mechanism ............................................................... 20 4.3 Firmware Memory Cycle Overview ..................................................................... 21 4.3.1 Field Definitions ................................................................................... 21 4.3.1.1 START................................................................................ 21 4.3.1.2 IDSEL (Device Select)........................................................ 21 4.3.1.3 MADDR (Memory Address)................................................ 21 4.3.1.4 MSIZE (Memory Size) ........................................................ 21 4.3.1.5 TAR .................................................................................... 22 4.3.1.6 SYNC ................................................................................. 22 4.3.1.7 DATA.................................................................................. 22 4.3.1.8 Protocol .............................................................................. 22 4.3.1.9 Preamble............................................................................ 22 4.3.1.10 Firmware Memory Read Cycle ........................................... 23 4.3.1.11 Firmware Memory Write Cycles ......................................... 23 4.3.1.12 Error Reporting................................................................... 24 5 Target Protocol................................................................................................................ 25 5.1 Memory Cycles ................................................................................................... 25 5.2 I/O Cycles ........................................................................................................... 26 251289-001 3 Introduction R 5.3 Firmware Memory Cycles ................................................................................... 29 6 Direct Memory Access (DMA) Protocol ........................................................................... 31 6.1 Introduction ......................................................................................................... 31 6.2 Asserting DMA Requests.................................................................................... 31 6.3 Abandoning DMA Requests................................................................................ 32 6.4 DMA Transfers.................................................................................................... 32 6.4.1 Terminal Count.................................................................................... 34 6.4.2 Verify Mode ......................................................................................... 34 6.4.3 DMA Request De-Assertion................................................................. 35 6.4.4 SYNC field / LDRQ# Rules .................................................................. 36 6.4.5 Performance Analysis.......................................................................... 36 6.5 Other Notes on 16 and 32 Bit DMA..................................................................... 37 7 Bus Master Protocol ........................................................................................................ 39 7.1 Introduction ......................................................................................................... 39 7.2 Cycle Formats and Timing .................................................................................. 39 7.3 Request Assertion Rules..................................................................................... 43 8 Power Management ........................................................................................................ 45 8.1 CLKRUN# Protocol ............................................................................................. 45 8.2 LPCPD# Protocol................................................................................................ 45 8.3 LPME# Usage..................................................................................................... 46 8.4 Lower Voltages ................................................................................................... 46 9 Reset Policy..................................................................................................................... 47 10 Electrical Specification....................................................................................................
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