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Green Electronics: High Efficiency On-Chip Power Management Green Electronics: High Efficiency On-chip Power Management Solutions for Portable and Battery-Powered Applications Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Anqiao Hu, B.S., M.S. Graduate Program in Electrical and Computer Engineering The Ohio State University 2010 Dissertation Committee: Mohammed Ismail, Advisor Steven Bibyk Waleed Khalil Copyright by Anqiao Hu 2010 Abstract With increasing recognition of green house gas emission as a major contributor to global warming, and that fossil fuels are finite resources that would eventually dwin- dle, green electronics, a commitment toward designing more energy-efficient products, is not only an environmental, social, and ethical imperative for the integrated circuit research community, but also a shrewd business practice for industry. This dissertation discusses various mixed-signal VLSI techniques at system and circuit (transistor) levels that would help build energy-efficient green electronics, which are instrumental for current consumer applications and future sustainable renewable-energy economy. At system level, a truly effective power management scheme should be a holistic solution involving system software, VLSI architecture, and silicon IPs. Sleep-mode efficiency is pointed out as the bottleneck for low power battery-powered applications, and around 30% battery runtime extension is estimated based on published experimental data if sleep-mode efficient power management IPs are available and used in place. At circuit level, a number of linear regulator and switch-mode power converter designs are presented. A sleep-mode ready, current-area efficient capacitor-free low drop-out regulator with input current-differencing is designed, fabricated, and mea- sured in 0.5 µm CMOS process. A long-sleep model that improves the light-load ii efficiency of DC-DC Buck converter under mW to µW load during system sleep- mode is also proposed. The common theme among the designs is high efficiency and full on-chip, which are uniquely required by portable and battery-powered applica- tions; The key innovation is the enhanced sleep-mode efficiency, which is driven by, and effectively supports the holistic power management solution. iii To my parents iv Acknowledgments First of all, I would like to thank my adviser, Professor Mohammed Ismail. He saw the good in me and never gave up inspiring me to reach my full potentials. He pulled me back from a cozy work and shouldered me through some of the toughest moments in research and publishing. He sets an example for me on what a professor should be like, and he remains hopeful that I can follow his footsteps. The longer I know Professor Ismail, the better I see myself. I would also like to thank my former adviser, Professor Steven Bibyk. He is the source of wisdom and candid critic for me when Professor Ismail is not around, not to mention that he almost single-handedly paved my study and career path in the United States, for which I will always be grateful. In addition, I would like to thank Professor Waleed Khalil for his technical and professional advices. He is a true role model and an inspiration for me as I get ready to step into the semiconductor industry. My special thanks also go to Professor Ayman Fayed, who guided me through the early confusion period of my Ph.D. studies when we were both at TI, and answered many of my technical questions ever since. I am grateful to Texas Instruments, which has provided me with a generous fel- lowship and multiple internship opportunities. The people I have worked with at TI from Dallas to Baltimore are beyond marvelous. Among them I want to thank in particular Gordhan Barevadia, Edward Chalfin, and Joel Zolnier for their support v and recommendations, as well as Alan Hastings and Edward Coleman for sharing their IC design experiences and insights. Finally, I want to thank my parents for almost everything I have accomplished. Thank you for your constant reminder to write my dissertation, and the unyielding belief that I can succeed in a field that was once considered completely foreign and formidable–engineering. vi Vita 2002 ........................................High School Attached to the Hunan Normal University, China 2006 ........................................B.S. Electrical Engineering, Beijing University of Aeronautics and Astro- nautics 2007 ........................................M.S. Electrical and Computer Engi- neering, The Ohio State University Summer 2008-2010 ......................... Intern, Texas Instruments 2009-present ................................Graduate Research Associate, The Ohio State University. Publications Research Publications J. Hu, W. Liu, and M. Ismail “Sleep-mode ready, area efficient capacitor-free low- dropout regulator with input current-differencing”. Analog Integrated Circuits and Signal Processing, 63(1):107–112, Apr. 2010. Fields of Study Major Field: Electrical and Computer Engineering vii Table of Contents Page Abstract....................................... ii Dedication...................................... iv Acknowledgments.................................. v Vita ......................................... vii ListofTables.................................... xi ListofFigures ................................... xii 1. Introduction.................................. 1 1.1 TheConceptofGreenElectronics. 2 1.2 The Applications of Green Electronics . 5 1.2.1 SmartGrid ........................... 5 1.2.2 WildLifeMonitoring. 7 1.3 GreenElectronicsSystems. 8 1.4 Power Management IC Design . 11 1.4.1 Challenges: High Efficiency and Full On-chip . 11 1.4.2 Specifications versus Performance . 13 1.4.3 Multi-Dimensional Trade-Off . 14 1.5 StructureoftheDissertation . 15 2. SystemPowerManagement ......................... 17 2.1 Overview: A Holistic Approach . 18 2.2 Very Low Power Applications: A Sleep Mode Perspective . 23 2.2.1 PowerChainStudy. 25 2.2.2 Power Saving from Proposed Structure . 27 viii 2.3 Summary ................................ 33 3. LinearRegulators............................... 34 3.1 High Efficiency: Low-dropout (LDO) Topology . 35 3.2 LDO Performance and Design Challenges . 40 3.2.1 DCParameters......................... 41 3.2.2 ACParameters......................... 49 3.2.3 Transient Parameters . 58 3.3 ExternalCapacitor-FreeLDO . 60 3.3.1 Challenges ........................... 60 3.3.2 ExistingSolutions . 63 3.4 Current-Area Efficient Capacitor-free LDO . 66 3.4.1 Motivation: Efficiency Size Trade-off . 66 3.4.2 Approach: Excessive Gain Reduction . 67 3.4.3 Method: InputCurrent-Differencing . 69 3.4.4 SimulationResults . 74 3.4.5 MeasurementResults . 81 3.5 Summary ................................ 93 4. Switch-ModeDC-DCConverters . 94 4.1 Light-Load Efficiency Challenge . 95 4.2 Conventional Efficiency Boosting Techniques . 96 4.3 Sleep-Wake Efficiency Boosting . 97 4.4 TheLong-SleepModel . 103 4.4.1 Definition............................ 104 4.4.2 Implication: Large-I0 Approximation . 104 4.4.3 Characteristics . 105 4.4.4 Novelty ............................. 109 4.5 LSM Buck Converter Design Example . 110 4.5.1 System Design Considerations . 110 4.5.2 Power Train Design . 111 4.5.3 Control Loop Design . 112 4.6 SimulationResults ........................... 115 4.7 Summary ................................ 120 5. Conclusion................................... 123 ix Appendices 125 A. TestPlanfortheDual-CoreLDO . 125 A.1 LDO 2: Conventional Topology . 125 A.2 LDO1:ProposedTopology . 128 Bibliography .................................... 130 x List of Tables Table Page 2.1 Battery current (unit:µA) at different RAM voltages (VDD)...... 32 3.1 TSMC 0.18 µm CMOS Process Technology (2V nominal devices) . 76 3.2 Performance Comparison of the Capacitor-free LDOs . 76 3.3 Capacitor-free LDO Design Specifications . 77 3.4 Battery current saving from the proposed technique . 80 4.1 Advantages and disadvantages of existing techniques . 98 4.2 Design specifications for the Buck Converter . 110 A.1 InputStimuli ............................... 126 A.2 OutputPins................................ 126 A.3 Difference in Input Stimuli for the Proposed Topology . 128 A.4 Differences in Output Waveforms to be Observed . 129 xi List of Figures Figure Page 1.1 Rate of Server Management and Power/Cooling Cost Increase [1] . 4 1.2 A Holistic Approach toward Green Electronics . 5 1.3 A Possible Scenario of Future Power System Based on Smart Grid [2] 6 1.4 Block Diagram of A Green Electronics Micro System . 9 1.5 Power Management Octagon . 14 2.1 A Holistic Approach to System Power Management . 19 2.2 DVFS versus Traditional Constant Supply Power Management Scheme 21 2.3 Active and sleep mode current consumption for a IEEE 802.15.4/Zig- beecompatibleSoC[3] .......................... 24 2.4 Power chain example 1: STMicroelectronics STM32W108 2.4G wire- lessSoC .................................. 25 2.5 Power Chain example 2: TI CC253x 2.4G SoC . 26 2.6 Power chain example 3: Freescale MC1322x 2.4G PiP . 27 2.7 Configuration of the sleep mode power chain: existing solutions and proposed. ................................. 28 2.8 Experimental data from 65 nm CMOS Ultra Low Power SRAM: Leak- age reduction with VDD.[4] ....................... 30 xii 2.9 Comparison between an LDO-based and a DC/DC based power chain insleepmode ............................... 31 2.10 Battery Current Reduction using DC/DC converter . 32 3.1 Linear Regulator: A Controllable Impedance that Forms a Voltage DividerwiththeLoad .........................
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