Green Electronics: High Efficiency On-Chip Power Management

Green Electronics: High Eﬃciency On-chip Power Management Solutions for Portable and Battery-Powered Applications

Dissertation

Presented in Partial Fulﬁllment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University

Anqiao Hu, B.S., M.S.

Graduate Program in Electrical and Computer Engineering

The Ohio State University

2010

Dissertation Committee:

Mohammed Ismail, Advisor Steven Bibyk Waleed Khalil Copyright by

Anqiao Hu

2010 Abstract

With increasing recognition of green house gas emission as a major contributor to global warming, and that fossil fuels are ﬁnite resources that would eventually dwin- dle, green electronics, a commitment toward designing more energy-eﬃcient products, is not only an environmental, social, and ethical imperative for the integrated circuit research community, but also a shrewd business practice for industry.

This dissertation discusses various mixed-signal VLSI techniques at system and circuit (transistor) levels that would help build energy-efficient green electronics, which are instrumental for current consumer applications and future sustainable renewable-energy economy. At system level, a truly effective power management scheme should be a holistic solution involving system software, VLSI architecture, and silicon IPs. Sleep-mode efficiency is pointed out as the bottleneck for low power battery-powered applications, and around 30% battery runtime extension is estimated based on published experimental data if sleep-mode efficient power management IPs are available and used in place.

At circuit level, a number of linear regulator and switch-mode power converter designs are presented. A sleep-mode ready, current-area eﬃcient capacitor-free low drop-out regulator with input current-diﬀerencing is designed, fabricated, and measured in 0.5 µm CMOS process. A long-sleep model that improves the light-load

ii efficiency of DC-DC Buck converter under mW to µW load during system sleep- mode is also proposed. The common theme among the designs is high efficiency and full on-chip, which are uniquely required by portable and battery-powered applications; The key innovation is the enhanced sleep-mode efficiency, which is driven by, and effectively supports the holistic power management solution.

iii To my parents

iv Acknowledgments

First of all, I would like to thank my adviser, Professor Mohammed Ismail. He

saw the good in me and never gave up inspiring me to reach my full potentials. He

pulled me back from a cozy work and shouldered me through some of the toughest

moments in research and publishing. He sets an example for me on what a professor

should be like, and he remains hopeful that I can follow his footsteps. The longer I

know Professor Ismail, the better I see myself.

I would also like to thank my former adviser, Professor Steven Bibyk. He is the source of wisdom and candid critic for me when Professor Ismail is not around, not to mention that he almost single-handedly paved my study and career path in the

United States, for which I will always be grateful.

In addition, I would like to thank Professor Waleed Khalil for his technical and professional advices. He is a true role model and an inspiration for me as I get ready to step into the semiconductor industry. My special thanks also go to Professor Ayman

Fayed, who guided me through the early confusion period of my Ph.D. studies when we were both at TI, and answered many of my technical questions ever since.

I am grateful to Texas Instruments, which has provided me with a generous fel- lowship and multiple internship opportunities. The people I have worked with at TI from Dallas to Baltimore are beyond marvelous. Among them I want to thank in particular Gordhan Barevadia, Edward Chalﬁn, and Joel Zolnier for their support

v and recommendations, as well as Alan Hastings and Edward Coleman for sharing

their IC design experiences and insights.

Finally, I want to thank my parents for almost everything I have accomplished.

Thank you for your constant reminder to write my dissertation, and the unyielding belief that I can succeed in a ﬁeld that was once considered completely foreign and formidable–engineering.

vi Vita

2002 ...... High School Attached to the Hunan Normal University, China 2006 ...... B.S. Electrical Engineering, Beijing University of Aeronautics and Astro- nautics 2007 ...... M.S. Electrical and Computer Engi- neering, The Ohio State University Summer 2008-2010 ...... Intern, Texas Instruments

2009-present ...... Graduate Research Associate, The Ohio State University.

Publications

Research Publications

J. Hu, W. Liu, and M. Ismail “Sleep-mode ready, area eﬃcient capacitor-free low- dropout regulator with input current-diﬀerencing”. Analog Integrated Circuits and Signal Processing, 63(1):107–112, Apr. 2010.

Fields of Study

Major Field: Electrical and Computer Engineering

vii Table of Contents

Page

Abstract...... ii

Dedication...... iv

Acknowledgments...... v

Vita ...... vii

ListofTables...... xi

ListofFigures ...... xii

1. Introduction...... 1

1.1 TheConceptofGreenElectronics...... 2 1.2 The Applications of Green Electronics ...... 5 1.2.1 SmartGrid ...... 5 1.2.2 WildLifeMonitoring...... 7 1.3 GreenElectronicsSystems...... 8 1.4 Power Management IC Design ...... 11 1.4.1 Challenges: High Efficiency and Full On-chip ...... 11 1.4.2 Specifications versus Performance ...... 13 1.4.3 Multi-Dimensional Trade-Off ...... 14 1.5 StructureoftheDissertation ...... 15

2. SystemPowerManagement ...... 17

2.1 Overview: A Holistic Approach ...... 18 2.2 Very Low Power Applications: A Sleep Mode Perspective ...... 23 2.2.1 PowerChainStudy...... 25 2.2.2 Power Saving from Proposed Structure ...... 27

viii 2.3 Summary ...... 33

3. LinearRegulators...... 34

3.1 High Efficiency: Low-dropout (LDO) Topology ...... 35 3.2 LDO Performance and Design Challenges ...... 40 3.2.1 DCParameters...... 41 3.2.2 ACParameters...... 49 3.2.3 Transient Parameters ...... 58 3.3 ExternalCapacitor-FreeLDO ...... 60 3.3.1 Challenges ...... 60 3.3.2 ExistingSolutions ...... 63 3.4 Current-Area Efficient Capacitor-free LDO ...... 66 3.4.1 Motivation: Efficiency Size Trade-off ...... 66 3.4.2 Approach: Excessive Gain Reduction ...... 67 3.4.3 Method: InputCurrent-Differencing ...... 69 3.4.4 SimulationResults ...... 74 3.4.5 MeasurementResults ...... 81 3.5 Summary ...... 93

4. Switch-ModeDC-DCConverters ...... 94

4.1 Light-Load Efficiency Challenge ...... 95 4.2 Conventional Efficiency Boosting Techniques ...... 96 4.3 Sleep-Wake Efficiency Boosting ...... 97 4.4 TheLong-SleepModel ...... 103 4.4.1 Definition...... 104 4.4.2 Implication: Large-I0 Approximation ...... 104 4.4.3 Characteristics ...... 105 4.4.4 Novelty ...... 109 4.5 LSM Buck Converter Design Example ...... 110 4.5.1 System Design Considerations ...... 110 4.5.2 Power Train Design ...... 111 4.5.3 Control Loop Design ...... 112 4.6 SimulationResults ...... 115 4.7 Summary ...... 120

5. Conclusion...... 123

ix Appendices 125

A. TestPlanfortheDual-CoreLDO ...... 125

A.1 LDO 2: Conventional Topology ...... 125 A.2 LDO1:ProposedTopology ...... 128

Bibliography ...... 130

x List of Tables

Table Page

2.1 Battery current (unit:µA) at diﬀerent RAM voltages (VDD)...... 32

3.1 TSMC 0.18 µm CMOS Process Technology (2V nominal devices) . . 76

3.2 Performance Comparison of the Capacitor-free LDOs ...... 76

3.3 Capacitor-free LDO Design Speciﬁcations ...... 77

3.4 Battery current saving from the proposed technique ...... 80

4.1 Advantages and disadvantages of existing techniques ...... 98

4.2 Design speciﬁcations for the Buck Converter ...... 110

A.1 InputStimuli ...... 126

A.2 OutputPins...... 126

A.3 Diﬀerence in Input Stimuli for the Proposed Topology ...... 128

A.4 Diﬀerences in Output Waveforms to be Observed ...... 129

xi List of Figures

Figure Page

1.1 Rate of Server Management and Power/Cooling Cost Increase [1] . . 4

1.2 A Holistic Approach toward Green Electronics ...... 5

1.3 A Possible Scenario of Future Power System Based on Smart Grid [2] 6

1.4 Block Diagram of A Green Electronics Micro System ...... 9

1.5 Power Management Octagon ...... 14

2.1 A Holistic Approach to System Power Management ...... 19

2.2 DVFS versus Traditional Constant Supply Power Management Scheme 21

2.3 Active and sleep mode current consumption for a IEEE 802.15.4/Zig- beecompatibleSoC[3] ...... 24

2.4 Power chain example 1: STMicroelectronics STM32W108 2.4G wire- lessSoC ...... 25

2.5 Power Chain example 2: TI CC253x 2.4G SoC ...... 26

2.6 Power chain example 3: Freescale MC1322x 2.4G PiP ...... 27

2.7 Conﬁguration of the sleep mode power chain: existing solutions and proposed...... 28

2.8 Experimental data from 65 nm CMOS Ultra Low Power SRAM: Leak- age reduction with VDD.[4] ...... 30

xii 2.9 Comparison between an LDO-based and a DC/DC based power chain insleepmode ...... 31

2.10 Battery Current Reduction using DC/DC converter ...... 32

3.1 Linear Regulator: A Controllable Impedance that Forms a Voltage DividerwiththeLoad ...... 35

3.2 LDOversusHDOtopology...... 37

3.3 ExamplesofNMOSLDOreportedinliterature ...... 39

3.4 Qualitative Analysis of DC Line Regulation using PMOS I-V curve . 41

3.5 Quantitative Line Regulation Analysis ...... 43

3.6 Qualitative Analysis of DC Load Regulation using PMOS I-V curve . 45

3.7 Error Voltage Vǫ duetoFiniteDCLoopGain ...... 47

3.8 MethodsofimprovingDCparameters...... 49

3.9 FrequencyCompensationMethodsofaPMOSLDO ...... 52

3.10 PoleLocationsandPSRofaPMOSLDO ...... 54

3.11PSRderivation ...... 55

3.12 Power Supply Rejection Enhancement Methods for a PMOS LDO . . 57

3.13 Thevenin Equivalent Circuit in Analyzing Overshot and Undershot . 58

3.14 Transient Response Enhancement Techniques for a PMOS LDO . . . 61

3.15 Existing Methods of Designing External Capacitor-free LDOs . . . . 65

3.16 (a) Excessive Gain in Existing Solutions and (b) Excessive Gain Re- duction ...... 67

3.17 Schematic of the Proposed Capacitor-free LDO ...... 69

xiii 3.18 Principle of Input Current-Diﬀerencing: (a) bipolar implementation (b) CMOS version (c) Advantages over Prior Arts ...... 71

3.19 LDO Stability Analysis (a) Two-port Model (b) Bode Plot (c) Small- signalEquivalentCircuit ...... 72

3.20 Transient response of LDO under diﬀerent output parasitic and corner conditions Iout: 20 mA/div., Vout: 100 mV/div., 10 us/div...... 75

3.21 Bode plots of the conventional and proposed LDOs at Iout,min = 100µA 78

3.22 Bode plots of the conventional and proposed LDOs at Iout,min = 0 . . 79

3.23 Load transient waveforms with 100 µA of “stay alive” current. V: 400 mV/div, I: 25 mA/div, t: 50 µs/div...... 80

3.24 Load transient waveforms without “stay alive” current. V: 200 mV/div, I: 25 mA/div, t: 50 µs/div...... 81

3.25 On-chip test structure with oﬀ-chip option ...... 82

3.26 Schematic of the Electrostatic Discharge (ESD) protection circuit . . 83

3.27 Die Photo showing the Electrostatic Discharge (ESD) structure ... 84

3.28 Die Photo of the Dual-Core Capacitor-Free LDO ...... 85

3.29 Detailed Die Photo showing Integrated Circuit Components: Resistors, Capacitors, Pass Elements, and Error Ampliﬁers...... 86

3.30 Schematic of the Printed Circuit Board (PCB) ...... 87

3.31PhotoofthePCB...... 88

3.32 Test Equipment and Proper Connection for the Test ...... 89

3.33 Measured Transient Response of the Fabricated Conventional LDO with”stayalive”current...... 90

3.34 Layout Error Identiﬁed in the top-level interconnect of the Proposed LDOCore...... 90

xiv 3.35 Diagnostic Test Bench to Analyze the Measurement-Simulation Dis- crepancies ...... 91

3.36 Schematic and Post-layout Simulations of the Proposed LDO with Dis- connected VBIAS,1 that Correlate with Measurement Results . . . . . 92

4.1 Eﬃciency Curve of a DC-DC converter ...... 95

4.2 A general illustration of the optimum output power point Popt at which a DC-DC converter achieves maximum eﬃciency ηmax ...... 100

4.3 Block diagram of a Sleep-Wake DC-DC Converter with an Energy Stor- ageElement...... 102

4.4 Large-I0 approximation in typical Buck converter ...... 105

4.5 Long-Sleep Model waveforms and inductor current proﬁles ...... 106

4.6 Load Regulation of a conventional DC-DC vs a sleep-wake DC-DC . . 107

4.7 System Block Diagram of the DC-DC Converter ...... 111

4.8 Schematic of the clocked comparator ...... 114

4.9 Test benches for the DC-DC converter in Normal Mode and Sleep Mode116

4.10 Open-loop Dynamic of the Optimized Power Train ...... 117

4.11 Inductor Current IL duringHeavyModeOperation ...... 117

4.12 Close-loop Sleep-wake Operation of the Buck Converter ...... 118

4.13 Inductor Current IL during twake ...... 118

4.14 LoadregulationinSleepMode...... 119

4.15 Simulated Eﬃciency of the Proposed Converter ...... 120

4.16 The Chip Layout of the Proposed Converter ...... 121

xv Chapter 1: Introduction

The last few decades have seen climate disruption unprecedented over the recent

millenia. The trend toward global warming is virtually certain: the earth surface has

increased by about 0.74 ◦C since 1906 [5], and there is a strong consensus among scientists that this is a result of the emission of greenhouse gases, pre-eminent of which is CO2, mainly originating from fossil fuel burns. Aside from the negative

environmental impact, fossil fuels are non-renewable resources that take millions of

years to form, but are now depleting at a much faster speed than new ones are being

made. As a result, the world is facing an unprecedented challenge to switch from

fossil fuel, carbon-emission driven growth to an eco-friendly, low carbon economy to

the meet the energy need as well as mitigating the environmental consequences [6].

Next to replacement of fossil fuels by alternatives, such as solar, wind, geothermal,

biomass, and so forth, there is also increasing awareness that scrutiny of existing

technology and applications can have an immediate, and profound impact [7]. Energy

eﬃciency (EE), which is to reduce the amount of energy required to provide products

and services, is often considered as the parallel pillar to renewable energy (RE) in a

sustainable energy economy [8]. Parallel to the large-scale energy grand challenge,

portable and battery-powered products are facing a similar power crisis a mini-scale:

consumers appreciate the multimedia experience and ubiquitous connectivity in an

1 increasingly compact size, but they are unwilling to sacriﬁce, and even demand longer

battery runtime for new generations of devices.

This dissertation, therefore, is focused on improving the energy eﬃciency of elec-

tronic products, especially portable and battery-powered ones, using advanced power

management and very-large-scale integration (VLSI) design techniques, These elec-

tronics will not only eﬀectively reduce the power consumption and extend the battery

life for current consumer products, but also enable and assist future clean energy gen-

eration and distribution, leading to a new era of “Green Electronics” in the future

renewable-energy economy.

1.1 The Concept of Green Electronics

The term green electronics has been used to refer to a number of initiatives.

From the perspective of manufacturing, “green” has been used to refer to a design and manufacturing process that is environmentally friendly, which does not create or involve the use of hazardous materials and chemicals [9]. The motivation is that consumers today are increasingly more environmentally aware, that they are willing to pay a little extra for the same quality and performance if the products they purchase are green [10].

From the perspective of recycling and waste management, “green” may also refer

to advanced product design that have less impact on the environment by using cleaner

materials, having a longer product life, and reducing the electronic waste (e-waste)

generated [11]. It may also refer to public programs that encourages reuse and re-

cycle of electronics (e-Cycle), such as computers and cell phones [12]. The rationale

is that electronics consists of valuable resources such as precious metals, copper, and

2 engineered plastics, all of which require considerable energy to process and manu- facture. eCycle recovers valuable materials, conserves virgin resources, and results in lower environmental emissions (including greenhouse gases) than making products from virgin materials [13].

From the perspective of sustainable practices, “green electronics” is often used interchangeable with “green computing”, which refers to the environmentally responsible use of computers and related resources, such as powering down the CPU and all peripherals during extend period of inactivity, powering up energy-intensive peripherals such as laser printer according to need, and using power management features for hard disks and displays [14]. For consumers planning to purchase new electronic devices, there are various tools that can help consumers make the right choices to save money and protect the environment. Energy Star, for instance, is a joint program of

U.S. Environmental Protection Agency (EPA) and the U.S. Department of Energy

(DOE) started in 1992 and designed to identify and promote energy-eﬃcient products to reduce greenhouse gas emissions [15].

Finally from the perspective of electronic design, “green” refers to the innovative designs and techniques that improve energy efficiency. In addition to the benefit of reducing energy consumption, carbon emission, and e-waste disposal, energy efficiency reduces the cost and increases the appeal of the products. In high performance computing applications such as data centers, power and cooling cost has increased by

400% over the past decade, and these costs are expected to continue to rise (as seen in Fig. 1.1. In some cases, power costs account for 40-50% of the total data-center operation budget [1]. In portable and battery-powered applications like laptops, cell- phones, and PDAs, high energy eﬃciency translates to a longer runtime for the same

3 Figure 1.1: Rate of Server Management and Power/Cooling Cost Increase [1]

rechargeable battery, which improves consumer quality-of-experience (QoE) [16]. It also reduced heat dissipation, which eliminates the need for large heat sinks, enabling smaller, thinner, and more compact electronic products.

This dissertation mostly uses the term “green electronics” in its last interpreta- tion. In other word, this research focuses on the technical challenges and solutions in designing energy eﬃcient electronic products. However, it is important to realize the goal of green electronics can only be achieved with a joint eﬀort from all perspec- tives, that the combination of green design, green manufacturing, green computing, and green disposal forms a holistic approach to green electronics in a sustainable renewable-energy economy [14] (as seen in Fig. 1.2).

4 green manufacturing green use

Green Electronics

green green design disposal

Figure 1.2: A Holistic Approach toward Green Electronics

1.2 The Applications of Green Electronics

The applications of green electronics go beyond relieving the fore mentioned power, energy, and environmental crises in the near term and the longer future. They may also beneﬁt various research in industrial, science, and medical (ISM) ﬁelds.

1.2.1 Smart Grid

A major application of green electronics is in the future smart grid. The 2007

Energy Independence and Security Act of deﬁned the term “smart grid” as the mod- ernization of the electricity delivery system that monitors, protects, and automatically optimizes the operation of its interconnected elements from a central and distributed generator through a high-voltage transmission network and distribution system, to industrial users and building automation systems, and to end-use consumers and their thermostats, appliances, other handheld devices, and even electric vehicles [17].

A possible scenario of future power system based on smart grid technologies can be modeled by two concentric circles, as illustrated in Fig. 1.3. The outer circle

5 Figure 1.3: A Possible Scenario of Future Power System Based on Smart Grid [2]

represents energy ﬂow and the inner circle models information ﬂow over communica-

tion networks [2]. Power electronics building blocks (PEBB) and mechanical building

blocks (MEBB) are needed in a number of energy “hubs”, which manage multiple

energy carriers (e.g., electricity, natural gas, and district heating) and transform part

of the energy ﬂow into another form of energy.

As a result, a variety of green electronic circuits would be needed. To ensure efficient energy flow and flexible interconnection of the different smart grid players

(producers, energy storage systems, and loads), highly eﬃcient power converters in

6 the form of high voltage DC and ﬂexible AC converters, bidirectional energy conversion structures adopting pulse-width modulation(PWM) technology and other control algorithms are essential [2]. To better match energy demand, avoid excessive load peaks, and coordinate between producers and consumers, communication and information technologies would play a critical role [18]. Information exchange in the upper grid levels is usually covered by existing communication networks such as on

fiber-optic links that are installed in parallel to the high voltage grid, but medium and low voltage interconnection remains to be developed. Public telecommunication network (GSM, GPRS, UMTS), wireless network (WLAN, WiMAX), or powerline communication systems are all potential candidates, which all needs large numbers of high efficiency communication electronics. In addition, power generation at producer also opens up a significant demand for digital signal processing (DSP) and microcontroller (MCU) technologies. For example, in wind power generation, optimizing the angle of the blades of wind mill would required some sophisticated and signal processing and computing [17]. This is a good example of green electronics minimizing energy usage in various other applications and assisting clean energy generation.

1.2.2 Wild Life Monitoring

Another possible application of green electronics is in wild life monitoring and research. In ecology and social biology, there are huge interests in observing long- distance migration, inter-species interaction, and nocturnal behavior. For example,

Central Kenya is becoming more densely populated with smaller landholdings and more crop acreage. How fences and human presence aﬀect large scale (tens of kilo- meters) zebra migration is still unknown [19].

7 Existing technologies applied toward wild life tracking are surprisingly primitive or overly expensive. They include attaching VHF transmitters to the animals and use ﬂyovers to detect locations and using commercial GPS and satellite uploads to track locations. [20] Recently, wireless ad-hoc networks that automatically discover neighbors, self-organize, and perform peer-to-peer data routing was also proposed

[21]. However, the common limitation of these methods is power management, which includes the constraint of the battery power given the weight limit, and the energy eﬃciency of the hardware platforms and network algorithms. Future green electronics with improved energy eﬃciency would prolong the tracking period between each battery recharge, increase the reliable signal transmission distance by allowing more complex radio communication, and enable long-term non-invasive observations.

1.3 Green Electronics Systems

With various existing and emerging applications of green electronics, it is impossi- ble and unnecessary to deﬁne a universal structure or system architecture. However, it remains meaningful to outline a possible solution targeting a selective subset of applications as a mean to identify the various challenges. Fig. 1.4 shows such a system: a portable, battery-powered or self-sustainable, low-power green electronic microsystem. The choice for portability and

The green electronics micro system can be divided into three parts: energy sources, user applications, and power management. Energy sources may include primary (non rechargeable) or secondary (rechargeable) batteries, 110 V AC wall power, 5 V DC

USB power, and non-conventional energy sources such as energy harvesters and fuel

8 hrepms racmiaino ohwl enee [30]. needed be will both of c fuel combination of a voltage or output pumps, low charge the thr to due current But electric oxidant. generates an and which fuel 31], possib [30, third A cell fuel system. the a in is the needed rectiﬁes are harvesters or these DC of low electri 29] the into [28, converts them up converter that and 27] [24, energy converter [26] RF and kine [25], ambient scavenge solar to able are hand, other the ch on wall harvesters, of availability limited the as well as battery, the of siz c the given this runtime with system therefore problem and The total energy [22]. limited pa connected battery is the cable USB recharge or would adapter they and batteries, oﬀ Li-Ion power cell today electronics handheld and portable Many cells. AC, USBpower Energy−Harvesters Thermoelectric Energy Sources

Photovoltaic Fuel Cell Electrostatic iue14 lc iga fAGenEetoisMcoSystem Micro Electronics Green A of Diagram Block 1.4: Figure Li−Ion Battery Battery Boost Converter Charger Green ElectronicsMicroSystem Power Management Power Management and Delivery Current &VoltageReference Buck Converter 9 low drop−out(LDO) Regulator resdrn rvl Energy travel. during argers uhratosbtena between reactions ough Digital (CPU/MCU) n egtconstraint weight and e User ApplicationsUser Radio (TX/RX) ls os converters, boost ells, igecl rmulti- or single-cell a I/O interface i 2] hra [24], thermal [23], tic kweee nAC an whenever ck ADC/DAC Cotu voltages output AC Memory Analog oe.Aboost A power. c ngrto sthe is onﬁguration eeeg source energy le Wireless Sensors The second part of the green electronics systems is user applications. In order to provide maximum functionality and add value to diﬀerent applications, the system envisioned in Fig. 1.4 includes the following key components:

1. Intelligence. Electronic intelligence is often realized through embedded com-

puting in the form of microcontroller (MCU) or central processing unit (CPU).

Random access memory (RAM) and various forms of read-only memory (ROM)

are also needed to store the corresponding algorithms and processed data.

2. Communication. Green electronics in future smart grid or wild life monitor-

ing applications would also require wired or most likely wireless communication

capabilities to send useful information and coordinate operation. The commu-

nication protocol may not be advanced and the data rate need not be high, but

this feature is essential for mobility and networking. As a result, some form of

radio transceiver (TX/RX) is assumed present.

3. Sensing. Another important component of green electronics is its sensing and

control circuits. In future homes connected to smart grid, temperature, humid-

ity, and motion detectors would be needed to automatically control air condi-

tioning and other power utilities. Analog-to-digital (A/D) and digital-to-analog

(D/A) converters will be required to sample, measure, and adjust various real

world analog signals.

The third part of the system is power management, which includes the boost converters, charge pumps, battery chargers, buck converters, and linear regulators mentioned above. The function of power management circuits is to properly condition, convert, and deliver energy from various sources to loads. Even though they do not

10 directly provide user with a speciﬁc type of functionality or application, they are just

as important–if not more important–than the other two parts of the system due to

the considerations described in the next section.

1.4 Power Management IC Design

1.4.1 Challenges: High Eﬃciency and Full On-chip

The design considerations for power management circuits in a portable and low power green electronic system should include but not limited to the following:

1. Longevity. A major limitation for many portable and battery-powered elec-

tronics is their short battery life, or the constant need for battery recharge

and replacement. In applications involving large number of devices deployed

at hard-to-reach locations, industrial hazardous environment, or military com-

bat missions, this may be problematic, as the eﬀort and expense to locate the

devices and replace the batteries outlast whatever beneﬁts the electronics may

oﬀer.

2. Compactness. Another requirement for portable applications is the compactness

of the solution in all dimensions, including size, height, and weight. Large

discrete components, such as inductors, could be too thick to ﬁt in a slim smart

phone. Too many discrete capacitors could take up considerable amount of

board area that prevent the system from use in small footprint science, medical,

and military applications.

3. Manufactureability. In order for the whole green electronics system to be com-

mercially feasible, the power management circuits, together with other circuit

11 components, need to be manufactureable within reasonable cost. In other words,

all the electronic circuits within the system should be compatible with the main-

stream CMOS process and be easily implemented as an integrated circuit (IC)

or system-on-chip (SoC).

Power management circuits are primarily responsible for maintaining system ef-

ﬁciency, guaranteeing battery runtime, and achieving system longevity. The ideal solutions that address those concerns should possess the following characteristics:

1. High Eﬃciency. There are two levels of meanings involved. First, all the power

converters, such as buck, boost, linear regulators, have to enjoy high eﬃciency.

As a result, low drop-out (LDO) topologies for linear regulators and synchronous

rectifying structure for buck converter are preferred over high drop-out and free-

wheeling topologies. Secondly, power management circuits need to be designed

such that system eﬃciency is maximized. Therefore, system power consumption

and budget has to be studied, and power converters design techniques that

enable them to operate in various system power modes need to be analyzed.

2. Full On-chip. Compactness at board level translates to both fewer oﬀ-chip com-

ponents and smaller on-chip die area for integrated circuits. Oﬀ-chip capacitors,

resistors, inductors, and transformers, should be kept at a minimum, and full

on-chip power management IC topologies are highly desirable [32]. Meanwhile,

on-chip die area eﬃciency is also important, as smaller die size would allow

usage of smaller packages.

3. CMOS integrated circuits. Although BiCMOS technologies have been for a

favorite standalone power management integrated circuits, full CMOS design

12 would be more desirable due to the possibility of higher-level integration with

RF, digital, and analog circuitry.

1.4.2 Speciﬁcations versus Performance

This dissertation seeks to make a distinction between design speciﬁcations (“specs”) and circuit performance. Specs are considered to be the conditions under which an electronic circuit should operate, such as minimum and maximum output power, minimum and maximum power supply voltages. Performance parameters, on the other hand, describes how well the electronic circuit perform certain functions, such as eﬃciency, slew rate, and power supply rejection.

In the real world of electronic product development, the two categories often

overlap. A datasheet of a product would often guarantee certain performance for

customers, making those performance parameters part of the “specs” during the en-

gineering development. Diﬀerent “specs”, on the other hand, can signiﬁcantly alter

the ease of achieving many, if not all of the performance parameters, making the

comparison of any performance parameters meaningful only if the electronics circuits

are bound to the same “specs”. Thus, it is the belief of the author that no mandatory

“specs” need to be imposed throughout the dissertation, as that would be of interest

to industrial production and marketing. Rather, key performance (i.e. the circuit

performance of engineering and scientiﬁc importance) parameters of each individual

integrated circuit, design methods to achieve and improve those parameters, and the

inevitable trade-oﬀs involved in these methods are explored to advance the-state-of-

the-art in power electronics and integrated circuit and system science (ICSS).

13 Efficiency Power

Off-chip Supply Voltage component

Battery Supply Rejection Current

Stability Regulation

Figure 1.5: Power Management Octagon

1.4.3 Multi-Dimensional Trade-Oﬀ

This dissertation will focus on the design challenges and solutions in the power management circuits within the big picture of the fore mentioned green electronic system. Similar to analog IC design [33], power management integrated circuit design involves multi-dimensional trade-oﬀ.

Fig. 1.5 shows the “power management octagon” as a counter part to the “analog design octagon” in [33]. In addition to the common concerns of voltage supply, power, noise, and stability, power management circuits are uniquely challenged in its achievable eﬃciency. Output ripple (in switching converters) and ripple rejection (in linear regulators) are also essential, as power management circuits are primarily responsible for supply conditioning for other application circuits on chip. Finally, in the context of portable and battery-powered green electronics, oﬀ-chip components and battery current become important, as large on-chip components reduce the system portability, and large battery current reduces battery runtime.

14 1.5 Structure of the Dissertation

The rest of the dissertation is organized as follows. Chapter 2 discusses power management at the system level. It is important to realize that energy efficiency of any portable and battery-powered electronics cannot be achieved using a single remedy, that power management by definition is a system level effort. A holistic approach that involves system level software, SoC architecture, and silicon IPs is presented. Meanwhile, due to the unique requirements for portable and battery- powered applications, the importance of sleep mode operation is discussed. The benefit (battery life extension) of using silicon IPs with enhanced sleep-mode efficiency is quantized, and the design of sleep-mode efficient power converter IPs becomes the theme for the rest of the dissertation.

In Chapter 3, linear power converter designs are discussed with an emphasis on the more power efficient low drop-out (LDO) topology. The generic LDO performance matrix and design challenges are discussed next, which can be broadly divided into DC, AC, and transient categories. Special to portable applications, external capacitor-free LDOs are extremely attractive, and their design challenges and existing solutions are presented. The existing work on cap-free LDO, however, suffers from sleep-mode power inefficiency or large on-chip die area. A novel sleep-mode ready, area-efficient external capacitor-free low drop-out regulator using input current- differencing is proposed. Its design motivation, method, approach, simulation, and measurements are presented in details.

In Chapter 4, non-linear switch-mode power converter designs are studied with a focus on light-load efficiency improvement. The root cause of the light-load efficiency roll-off is first identified, which is the non-proportional power loss scaling with the

15 load, and both conventional and sleep-wake light-load eﬃciency boosting techniques

are discussed. A long-sleep model (LSM), which embodies an improved sleep-wake

eﬃcient boosting method is proposed, and a design example of a light-load eﬃcient

DC-DC buck converter using LSM is provided. The characteristics, implementation,

implication, and novelty of LSM are studied thoroughly.

Finally, chapter 5 concludes the dissertation by restating the mission of green electronics and summarizing the various techniques at circuits and system level that can be used to implement it. The potential impact of the research and its future directions are also discussed.

16 Chapter 2: System Power Management

Power management for a portable and battery-powered product is ultimately a system level challenge. The total energy available from a battery is usually constant, and every components on the system will consume power to a diﬀerent extend, from the power hungry LCD touch screen to low power digital registers and memories. It may seem that the system level power management schemes go beyond an integrated circuit (IC) designer’s concern. However, understanding these methods could give

IC designers insights to the relative importance of diﬀerent parameters within an IC block and eﬀectively guide their transistor-level innovations.

This chapter first reviews some existing system level power management schemes, mostly notably a holistic approach consisting of system software, SoC architecture, and silicon IP [34]. Regarding low power, low duty-cycle portable electronics in particular, this dissertation studies the relative importance of active mode and sleep mode, and concludes that sleep-mode efficiency is of greater importance, especially in highly integrated systems in advanced sub-micron processes. Potential battery life extension using a sleep-mode efficient DC-DC converter is estimated from reported experimental data and a log-linear prediction of leakage-supply dependence.

17 2.1 Overview: A Holistic Approach

A good example that embodies all the major challenges in portable power management is the design of a mobile smart phone. Consumers increasing rely on their smart phones for communication, computing, and entertaining. Meanwhile, they want sleek, compact devices that can easily be ﬁt into a pocket. Integration at the chip level combining multiple processing cores in the same device and smaller, sub-micron fabrication processes from 90nm to 45 nm help to reduce the size of wireless handsets while enabling added functionality. Unfortunately, smaller sub-micron processes ex- acerbate the problem of standby leakage power, and the added transistors and gates increase the dynamic power, making the task of battery extension more challenging

[34]. It was estimated that an average of 10 times better power management scheme is needed from one technology node to another just to maintain the same level of talk and standby time, yet there is increasing demand for longer battery despite all the technical diﬃculties [35].

To address this challenge, some research and industrial products [34, 35, 36] have proposed or adopted a holistic approach to system power management, which include a bundle of technologies and intellectual properties (IP). Fig. 2.1 shows a pyramid consists of:

1. System Software. Various system power management software can run on

mobile phone operating system (OS). An example of this can be a real-time task

scheduler [37], which monitors the work load of the system, adaptively schedule

tasks for execution while maintaining deadline. With the help of task scheduler,

power and performance can be boosted during heavy work load and critical

18 work load monitoring Syst. real−time schduler Software

power domains DVFS, AVS SoC Architecture

variable output linear, DC−DC Silicon IPs converters

Figure 2.1: A Holistic Approach to System Power Management

tasks, while the opposite can be done during idle time to reduce consumption.

These adjustments of power proﬁles can be either autonomously [34] or via

OS/user intervention.

2. SoC Architecture. In addition to software algorithm, certain SoC level archi-

tectural power management strategies can also be applied, such as power domain

devision [38], dynamic frequency and voltage scaling (DFVS) [39], adaptive volt-

age scaling (AVS) [34], and memory retention [40, 4].

Power domain division divides a complex SoC with multiple sub-systems and

processor cores into diﬀerent power domains, each enjoying its own supply volt-

ages and leakage current control (often through power gating). For example,

mobile baseband processor OMAP 3430 [41] is divided to four to ﬁve power

domains: MCU core, DSP core, graphic accelerator, Peripherals, and always-on

circuits, each of them could be conﬁgured independently.

19 Another architectural power management scheme is dynamic frequency and voltage scaling (DFVS) [39]. It is well known that the processing time T of a speciﬁc task and the dynamic power dissipated during computation can be modeled as

T = N/f (2.1)

2 Pdyn = CVDDf (2.2) in which the frequency of operation is given by f and the total switching capacitance is C. For compute-intensive and latency-critical tasks such as video decompression, where short T is critical, raising the clock frequency f can cause the tasks to be completed sooner. For low speed or idle tasks, only a fraction of throughput is required, and completing them ahead of their timing deadline leads to no discernible beneﬁts. Reducing f for these tasks reduces the power consumption, but does not aﬀect the total energy required to complete

2 the task, which is E = NCVDD. (Another way of understanding is that even though power consumption is lower, the time required to execute the task becomes longer.) Therefore, supply voltage VDD needs to be reduced together with frequency f, leading to signiﬁcant, sometimes an order of magnitude of energy saving [42]. When working closely with a real-time work monitoring and scheduler, this technique can provide the optimum supply voltages and clock frequencies such that all computing tasks and processing needs are completed

“just in time”, thereby eliminating any slack period. A simple illustration of the principles of DVFS is shown in Fig. 2.2.

20 Traditional

t Real−time Task Scheduling

Performance Performance

t DVFS

Performance t

Figure 2.2: DVFS versus Traditional Constant Supply Power Management Scheme

Adaptive Voltage Scaling (AVS) is similar to DVFS, but serves as a ﬁne tune,

self-adaptive power management. It detects the variations in process, tempera-

ture and aging and adaptively lower or raise the voltage level accordingly [36].

21 The hardware for AVS usually consists of sensor circuitry, such as ring oscil-

lators capable of self-monitoring the frequency of oscillation (or loop delay),

which is often an indicator of device corners, temperature and aging.

3. Silicon IPs. To support the architectural power management schemes, at

least two types of silicon IPs are needed. One type is the various forms of

integrated power converters that can execute the DVFS scheme by generating,

distributing, and delivering the variable supply voltages to diﬀerent circuits and

power domains, such as multiple- and variable-output DC-DC converters [39].

Due to the dynamic nature of DVFS, fast reference tracking DC-DC converters

are also essential [43, 44]. In addition, continual variation of output voltage

is desirable, making switched-capacitor type converter less attractive (as they

provide discrete supply voltages given by gain ratios (GR) [45]).

The other type is power conﬁgurable analog and digital sub-systems and build-

ing blocks, such as processors with multiple discrete Operating/Performance

Points (OPPs) for diﬀerent application scenarios (full-speed, low-power, standby,

and hibernation), and multi-threshold (Vt) CMOS cells: low Vt MOSFETs to

boost the performance during high-performance high-speed operation, and high

Vt MOSFETs to suppress leakage during standby periods.

The study and development of power management software fall beyond the scope of this dissertation, but the SoC architectural level power management related highly eﬃcient, application-aware integrated power converters design is a key enabling factor within the holistic approach. Before a detailed discussion on that topic in the following chapters, however, the uniqueness of the system power management for very

22 low power portable applications is ﬁrst studied, revealing an interesting property of

sleep-mode dominance, which will serve as a guiding motivation for the rest of the

dissertation.

2.2 Very Low Power Applications: A Sleep Mode Perspec- tive

For portable and battery-powered applications, the success of system power management is often measured by battery runtime. Short battery life is not only in- convenient for consumer electronics like laptops and cell phones, but also fatal to the commercial success of very low power, multi-year electronic devices like IEEE

802.15.4 and Zigbee compliant wireless SoCs for industrial, scientiﬁc, and medical

(ISM) applications.

Despite the innovations in battery technologies, from primary Ni-Cd and alkaline batteries to advanced rechargeable Li-Ion and Li-Polymer batteries, there will always be a limit on the total amount of energy available per size, weight, and reasonable cost. Consumers, however, are not only unwilling to sacrifice, but also craving for more functionality and better performance for newer portable and battery-powered electronics. Thus, increasing electronic circuits’ efficiency remains the most effective way to prolong battery life.

The bottleneck of power eﬃciency improvement, however, lies in the sleep mode

[46]. For example, battery-operated IEEE 802.15.4/Zigbee sensor nodes will be in sleep mode 99.9% of the time, waking up periodically for a few milliseconds to check a sensor or poll the other radios. [3] Thus, the total power consumption will approach sleep mode power consumption, as depicted in Fig. 2.3, with duty cycle (wake up time per operating period) well below 10%.

23 Current consumption

< 10% duty cycle

Active Icc

Average Icc Sleep Icc

Time

Figure 2.3: Active and sleep mode current consumption for a IEEE 802.15.4/Zigbee compatible SoC[3]

1 However, reducing the current consumption of the chip, Icc , during the sleep

mode of a low power integrated circuit (IC) or System-on-Chip (SoC) is non-trivial.

The sleep mode Icc is usually made up of the biasing and quiescent current (Iq) of the key sub blocks that remains on during sleep, such as power-on-reset (POR), brown- out-detection (BoD), memory data retention, and sleep timer, as well as the leakage current of the rest of the circuits. It is challenging to reduce Iq of a circuit block without huge performance penalty, but it is even more challenging to control the leakage as the CMOS IC technology scales into the nanometer regimes, where leakage increases dramatically.

The reduction of standby leakage has been addressed by diﬀerent techniques such as power gating [47], dynamic voltage scaling (DVS) [42], and body biasing [48].

Power gating and DVS use the power supply voltage, Vdd, as the primary knob for reducing leakage currents, by either cutting oﬀ, or gating, a circuit from its power

1 Notice that the total chip current (Icc), more precisely the battery current (Ibatt) decides the battery life, because the battery voltage remains relatively constant.

24 STM32W108HB: (STMicroelectronics) 2.1 ~ 3.6 V

LDO#1: 1.25 V, 10 mA LDO#2: 1.8 V, 50 mA

GPIO POR I/O #1 CPU Analog RF MEM watch−dog I/O #2 timer ARM ADC 2.4 G 128k Flash cortex M3 8k RAM

Figure 2.4: Power chain example 1: STMicroelectronics STM32W108 2.4G wireless SoC

supply, or lowering Vdd to reduce leakage. The penalty is mostly the area and design overhead. Body biasing adjusts the threshold voltage, Vth to reduce transistor sub-

threshold leakage. However, reverse body biasing worsens short channel eﬀects like

drain induced barrier lowering (DIBL), and increases Vth variation across a die, which

makes it less eﬀective with technology scaling [48].

Motivated by the important role the power supply, Vdd, plays in standby leakage

reduction and sleep mode eﬃciency boosting, this section investigates the power chain

structure within the widely used low power SoCs. A DC-DC converter based power

chain is proposed to eﬀectively reduces sleep mode battery current [49].

2.2.1 Power Chain Study

A power chain can be loosely deﬁned in this dissertation as a power ﬂowing path

from the battery to a point of load. Each load circuit will have one or more power

chains to the battery. Depending on the power mode, diﬀerent chains can be selected

and activated.

Several examples of the power chains within in state-of-the-art commercial prod-

ucts are shown in Fig. 2.4, 2.5, and 2.6 respectively. Fig. 2.4 shows a 2.4 GHz wireless

25 CC253x (Texas Instruments)

2.0 ~ 3.6 V LDO

5.0 V Power supply supervisery CPU Analog RF MEM USB USB interface 8051 ADC 2.4 G 8k RAM POR,BoD 64/128/256k Flash

Figure 2.5: Power Chain example 2: TI CC253x 2.4G SoC

SoC from STMicroelectronics built in ST’s proprietary 0.18µm process [50]. Circuit blocks such as General Purpose Input-Output (GPIO) and Power-on-Reset (POR) are directly powered from the battery due to voltage level compatibility and the need for direct battery voltage access. Analog, RF, and memory circuits are powered oﬀ an internal 1.8 V LDO, which provides the standard supply voltage of a 0.18µm process

and allows for maximum IP reuse. The CPU, on the other hand, operates oﬀ a 1.25

V LDO to reduce power consumption.

Fig. 2.5 shows a 2.4 GHz low power wireless SoC from Texas Instruments [51].

Unlike Fig. 2.4, both digital and analog sub-blocks are powered by a single 1.8 V

LDO for simplicity. Notice that all sub-blocks can be disconnected from the supply

rail during sleep mode to save on leakage, and the LDO can be by passed for direct

battery operation.

Finally, Fig. 2.6 shows a 2.4 GHz low power wireless Platform in Package from

Freescale Semiconductor [52]. It is similar to Fig. 2.5 expect that an optional Buck

converter is added in series of an LDO to create the internal 1.8 V power supply

rail. According to its datasheet [52], the converter will be activated during heavy

load in active operations to save on battery current. During sleep mode, where the

26 MC1322x Platform in Package (PiP) (Freescale) 2.0 ~ 3.6 V Buck LDO

Battery Detect MCU Analog RF MEM

ARM7 core ADC 2.4 G 96k SRAM 80k ROM 128k Flash

Figure 2.6: Power chain example 3: Freescale MC1322x 2.4G PiP

load current is low, the converter will be bypassed to avoid the Buck converter’s operational overhead in power consumption.

In summary, the common theme for all three products is that the sleep mode power chain (the power chain to the load that remains on during sleep, e.g., Load 1 as in Fig. 2.7) consists of LDOs only, if not merely a wire. Even if a DC-DC converter is available in the structure, it is disabled during sleep mode. This paper proposes using DC-DC converters in sleep mode so that the battery current in sleep mode will also be reduced.

2.2.2 Power Saving from Proposed Structure

This section will quantify the power saving by replacing the conventional LDO- based power chain with the proposed DC-DC-based structure during a leakage-dominated sleep mode operation for a hypothetical IEEE 802.15.4/Zigbee wireless SoC in a digital 65 nm CMOS process. Even though the analysis is based on a speciﬁc genre of low power wireless SoCs, the ﬁndings are nevertheless general and can be applied to other standby-power-critical applications as well.

27 Sleep mode Bypassed DC/DC

LDO

LDO LDO LDO LDO LDO

Load#1 Load#2 Load#3 Load#1 Load#2 Load#3

(a) STMicro: STM32x (b) Freescale: MC1322x

Available in DC/DC LDO All modes

LDO LDO

Load#1 Load#2 Load#3 Load#1 Load#2 Load#3

Figure 2.7: Conﬁguration of the sleep mode power chain: existing solutions and proposed.

The system is assumed to operate from a single-cell Li-Ion battery with nominal voltage of 3 V. During its sleep mode, 0.5 µA of “always-on” static power consumption is assumed for the essential functional blocks operated directed oﬀ the battery supply.

Leakage reduction techniques such as power gating are assumed to have been applied such that the leakage from RF and analog is negligible due to the small number of transistors involved. Leakage from the CPU is assumed to be less of an impact than

28 that of the memory, since Vdd of combinational logic circuits, which usually make up

the majority of CPU, can be set very close to zero without any major concern 2, but

a Vddmin is needed by a considerable portion of memory circuits like random-access

memory (RAM) to retain their contents. To simplify the analysis, the sleep mode

current budget will focus on the “always-on” and the leakage caused by data retention

with Vddmin of 500 mV.

The leakage current of a MOSFET is made up of gate tunneling, Igate, gate induced

junction leakage, IGIDL, and the subthreshold current, Isub, which often dominates

and can be expressed as [40]:

W Vgs Vth VDS Isub = Itexp( − )[1 exp( )] (2.3) L nVT − − VT

As we can see from equation 2.3, the Isub decrease exponentially as the supply voltage VDD is reduced. Decreasing VDD would also reduce Igate and IGIDL as well

[40]. To comprehensively model the leakage-supply relation, experimental data from a 65 nm ultra-low-power CMOS SRAM design [4], is used to construct an empirical formula.

As seen in Fig. 2.8 curve (a), the total leakage per bit decreases almost linearly with VDD in the logarithm scale, which is in agreement with the exponential VDD- relationship of Isub, which is supposed be dominant. Though additional techniques like

PMOS back gate bias (b) and virtual ground raise (c) would reduce the leakage further as reported in [4], this paper assumes a simple exponential ILEAK -VDD relation, i.e., assume

2In practice, sleep mode wake-up latency and current surge that leads to large IR drop is a concern. [53]

29 Figure 2.8: Experimental data from 65 nm CMOS Ultra Low Power SRAM: Leakage reduction with VDD. [4]

log(I /bit)= k V (2.4) LEAK · DD Given the data pair (20pA/bit, 1.2V ), (2.8pA/bit, 0.5V ) in [4], the parameter in

equation 2.4 can be estimated as k = (k1 + k2)/2 = 2.38. Assume that 16 KB of SRAM is on-board the SoC forb data retention, the total leakage current can be modeled as

I = 8bit/B 16KB exp(2.38 V )pA/bit (2.5) LEAK × × · DD

30 VBATT = 3V VBATT = 3V

VDDILEAK IBATT ILEAK IBATT ≈ ≈ ηVBATT

VDD η = 30%, 60%, 90% VDD

ILEAK = f(VDD) ILEAK = f(VDD)

8KB RAM 8KB RAM data data IQ 0 ≈ retention retention

(a) Ideal LDO (b) DC/DC

Figure 2.9: Comparison between an LDO-based and a DC/DC based power chain in sleep mode

The comparison is made between the conventional LDO based power chain and the proposed DC-DC converter, as seen in Fig. 2.9. The LDO is assumed to be ideal, thus

I = I + I I (2.6) BATT LDO LEAK QLDO ≈ LEAK The DC/DC converter is assumed to have eﬃciency of η.

V I I = DD LEAK (2.7) BATT DCDC η V · BATT Fig. 2.10 shows the battery currents of the resulting system during sleep mode.

A 30% eﬃcient DC-DC converter would consume more battery current compared to the ideal LDO unless the RAM data retention voltage, VDD, is lowered below 0.9 V.

This is because an ideal LDO’s eﬃciency improves as the drop-out voltage is reduced

31 Battery Current vs Vdd 3 Ideal LDO (Iq=0) 2.5 30% efficiency DC/DC 60% efficiency DC/DC 2 90% efficiency DC/DC Always ON (I=0.5u) 1.5

IBATT (uA) IBATT 1

0.5

0 0.5 0.6 0.7 0.8 0.9 1 1.1 Vdd

Figure 2.10: Battery Current Reduction using DC/DC converter

VDD 1.2 V 0.9 V 0.5 V

LDO 2.74 1.60 0.93 60% DC-DC 2.00 1.04 0.62

IBATT saving 27% 35% 33%

Table 2.1: Battery current (unit:µA) at diﬀerent RAM voltages (VDD)

(This will be discussed further in Chapter 3), but DC-DC converter is assumed to have a flat 30% efficiency in this case. A 60% efficient DC-DC converter, on the other hand, would reduce the battery current by 35% at 0.9 V or 20% to 30% across the entire VDD range of interest (0.5 V to 1.2 V). A 90% efficient DC-DC converter would reduce the battery current even further. However, the physical design of a 90% efficient DC-DC converter silicon IP at light load is much more challenging (as will

32 be discussed in Chapter 4). Table 2.1 summarize the battery current savings from a

60% eﬃcient DC-DC at three bench mark voltages.

2.3 Summary

This chapter discusses the system level power management strategies. A truly eﬀective power management scheme involves multiple levels of eﬀort from system software, SoC architecture to Silicon IPs. These discussions may seem unrelated to

IC design at ﬁrst glance, they actually provide important insights and guidelines for transistor-level design, which is to innovate in ways that enables power management

IC blocks to fully and better support the holistic power management scheme at the top level.

As an example of the said insight, the characteristics of very low power, low duty cycle battery-powered electronics are studied. Sleep mode efficiency is found to be the dominating factor in determining the overall system efficiency (compared to the active mode efficiency) because of the much longer sleep time the devices usually go through. Case studies on the system-level power chain of existing IEEE

802.15.4 Zigbee solutions reveals the lack of sleep-mode focus, and the battery runtime extension is estimated should diﬀerent sleep-mode eﬃcient DC-DC converter silicon

IPs are available. This observation serves as a primary motivation for the transistor- level DC-DC converter design in Chapter 4.

33 Chapter 3: Linear Regulators

Linear voltage regulators are probably the most fundamental power management

IC circuits. A linear regulator is a circuit that accepts a poorly speciﬁed (often

ﬂuctuating) dc input voltage and produces from it a constant, well-speciﬁed output

voltage than can be used as a supply for other circuits [54]. They are widely used to

generate high quality power supplies for sensitive analog and RF circuits due to their

superb noise, output ripple, and supply rejection performance. They are also favorites

in low cost low complexity applications, as they do not require an external inductor

(compared to switch-mode DC-DC converters), and the circuits are relatively simple,

leading to a shorter design time and lower risk associated.

The drawback of a linear regulator is that its eﬃciency is limited by its dropout voltage. Hence, low drop-out (LDO) regulators are more popular. [55, 56, 57] As current portable electronics industry and future green electronics continue to push for more compact solutions, capacitor-free LDOs are very attractive, as they eliminate the need for the bulky external capacitors, which will save in pin count, board area, and bill-of-material (BoM) [58, 59, 32, 46].

In this chapter, both conventional and capacitor-free LDO are discussed with an emphasis on how the removal of the external capacitor challenges the design and

34 Zeq Vin Vout

control Zload IQ Iout

Figure 3.1: Linear Regulator: A Controllable Impedance that Forms a Voltage Divider with the Load

circuit performance. Then some latest capacitor-free LDO designs are reviewed, re-

vealing the inherent trade-oﬀ among stability, power eﬃciency, and die area. A new

method that better addresses the trade-oﬀ and makes capacitor-free LDO more suit-

able for high eﬃciency battery-powered applications is introduced. The theoretical

analysis, circuit design, simulation, and measurements of the proposed LDO are also

presented.

3.1 High Eﬃciency: Low-dropout (LDO) Topology

A linear series voltage regulator can be viewed as a controllable impedance (resis-

tance) Zeq (Req) connecting between the input and output. The resistance Zeq forms a voltage divider with the load Zload, as shown in Fig. 3.1, such that the output

voltage Vout is always a portion of the input voltage Vin. As either Vin or Zload varies,

Zeq can be tuned within a range of values such that Vout remains relatively constant

(Eq. 3.1). As a result, the eﬃciency is independent of the load Iout, and it is simply

decided by the input-output voltage (Eq. 3.2). These reveal the basic limitation of

35 a linear regulator: the drop-out voltage V = V V 3. The larger the drop-out DO in − out voltage, the smaller the eﬃciency. In many applications, the drop-out voltage is determined by system power management requirement, such as the need to generate a

1.8 V supply rail from a 3 V I/O voltage, or the need to regulate 1.2 V supply for low power digital circuits from 1.8 V internal power rail.

Zload Vout = Vin (3.1) Zload + Zeq V η = out (3.2) Vin

A more detailed analysis of the linear regulator eﬃciency should also take into

the account of the output and quiescent current (Iout and IQ). The controllable

impedance is also called the pass element [60], and it can be implemented using

NPN, PNP, NMOS, and PMOS [61]. Additional circuitry is needed to control the

pass element, and any current that is drain from Vin and does not ﬂow to Iout is called

the quiescent current IQ. Thus,

V I V I η = out · out = out · out (3.3) V I V (I + I ) in · in in · Q out As long as the quiescent current I I , the LDO eﬃciency can be approx- Q ≪ out imated by the Eq. 3.2 very well. The ratio η = Iout remains important, and i Iout+IQ is often referred to as the current eﬃciency [62]. In portable and battery-powered

applications, it is important to keep the current eﬃciency high (e.g. above 90%) to

prolong the system runtime.

3 Another definition sometimes used in industry and products is Vin Vout measured when Vout is 100 mV below the pre-fined output voltage, or in other words when the− linear regulator is no longer in regulation [60]. The drop-out voltage defined in this manner will be VDO,min. A higher VDO is always possible, but it further reduces η.

36 VDD VDD

VBG VBG V ov V M1 M1 sg V Vout out

R1 Cout R1 VFB VFB

RESR R2 R2

Off−chip capacitor

PMOS Low−dropout (LDO) NMOS High−dropout (HDO)

Figure 3.2: LDO versus HDO topology

Fig 3.2 shows two transistor-level implementations of Fig. 3.1. The left conﬁgura-

tion uses a common-source PMOS as the pass element. Assume that M1 operates in the saturation region, the minimum VDO is approximately the overdrive of of the pass element, typically below 200mV . The conﬁguration on the right, on the other hand, uses a common-drain (source-follower) NMOS pass element. The minimum VDO in this case is Vgs,N = Vth,N + Vov, which is at least one threshold voltage higher, assuming that the gate of M1 cannot go above Vin. In this dissertation, the two topologies are called low drop-out (LDO) and high drop-out (HDO) respectively.

From Eq. 3.2, it is obvious that an HDO is less eﬃcient as an LDO. However,

NMOS HDO has a number of performance advantages over PMOS LDO, regardless of its eﬃciency drawback 4.

1. Stability. NMOS pass element connected in a common-drain (source follower)

conﬁguration is a good buﬀer when driving capacitative loads. In other words,

the output pole of the regulator is at very high frequency compared to the

4Many of the parameters mentioned here will be discussed in details in the following sections.

37 PMOS common-source conﬁguration so that the LDO would always be stable

as long as the rest of the circuit (e.g. error ampliﬁer) is properly compensated.

2. Area. Voltage regulators using NMOS are likely to require less die area because

a NMOS based pass element would be smaller than a PMOS one due to better

carrier mobility (electrons): µn can be three times as large as that of the PMOS

(holes) µ . Thus,to achieve the same I = 1/2µC W/L(V V )2, NMOS p D ox gs − th would need smaller W/L ratio, which translates to smaller area W L given · the same channel length L. This can be a major consideration for area eﬃcient

applications, because pass elements usually occupy most of the die area within

a regulator.

3. Power Supply Rejection. NMOS based structure would generally have better

PSR because the NMOS behaves like a cascode device for the output node.

PMOS, however, does little to shield the ripple since the supply is directly

connected to the source.

4. Load transient. NMOS based regulator enjoys better AC line regulation due

to better PSR. DC line regulation of a regulator depends on the DC open-loop

gain, which is often suﬃcient in design ( 60dB) regardless of the pass element ≥ type. NMOS regulator is also superior in load regulation because of the source

follower conﬁguration. The output impedance of a source follower, 1/gm,N , is

much smaller than that of a common source ampliﬁer, rds,P . Therefore, NMOS

regulator would experience less voltage undershot or overshot during abrupt

load current changes.

38 VG

VDD

CLK

VBG Charge Pump Vout

Design of [63]: Besten98JSSC

CLK VG CLK VG

VDD VDD

VBG VBG Vout Vout

R1 R1

R2 R2

Design of [64]: Kruiskamp08ESSCIRC Design of [66]: Giustolisi09AICSP and [65]: Camacho09MWSCAS

Figure 3.3: Examples of NMOS LDO reported in literature

Because of these advantages, researchers have studied methods to keep the NMOS

HDO advantages while improving the eﬃciency, leading to topologies with NMOS pass element in a low drop-out (LDO) conﬁguration, i.e. NMOS LDO. To do that, the circuit needs to generate a higher-than-supply gate voltage VG. If VG,max can be made higher than VDD, the NMOS drop-out voltage Vds,N would be as small as an overdrive, which is comparable to that of a PMOS LDO. A good example of NMOS

LDO is [63]. A charge pump is used to boost the NMOS gate voltage above supply.

39 More recent examples include [64, 65, 66], which use ﬂoating capacitor as voltage

source. Their simpliﬁed block diagrams are shown in Fig 3.3.

Higher-than supply VG generation, however, becomes a major challenge for NMOS

LDO. The high voltage switching involved in VG generation [63, 65, 66] introduces

additional noise in the control loop. The noise attenuation relies solely on the loop

gain at the switching frequency. Also, the circuit now needs additional capacitance,

non-overlapping clock generation, and high voltage switches, in addition to the linear

regulator core. Because of this, the design is more complicated, and the NMOS LDO

would no longer has as signiﬁcant amount of area saving as the pass element size

suggested (µn/µp). Finally, higher-than-supply VG may pose reliability threat, as the process feature size continue to scale down and the breakdown voltages of transistors are lower.

As a result, PMOS LDOs, though void of the advantages in stability, PSR, and load regulation, remains dominant in battery-powered applications because of its high eﬃciency, compactness if well designed, and simplicity [61]. Their performance has improved substantially thanks to numerous research on PMOS LDO design techniques.

3.2 LDO Performance and Design Challenges

In this section, the commonly used LDO performance parameters and their design challenges are discussed. LDO performance parameters can be categorized into DC,

AC and transient aspects. DC performance matrix includes line regulation, load regulation, drop-out voltage, quiescent current, and output accuracy. AC performance

40 ID

V =V SG2 SG,max VSG0

P P P 2 0 1 Iout VSG1

Req Req Req

V V V V DS DO,min DO DO,1

Figure 3.4: Qualitative Analysis of DC Line Regulation using PMOS I-V curve

matrix includes stability, noise, and power supply rejection (PSR), and transient per- formances includes line and load transient response, such as settling time, undershot and overshot.

3.2.1 DC Parameters

1. Line Regulation. The DC line regulation measures the capability of the regulator

to maintain Vout with varying Vin in a DC sense [67]. Qualitatively, it can be

analyzed using the MOSFET I-V curve in Fig. 3.4.

41 Suppose the regulator needs to source a constant Iout to the load and maintain a stable Vout while Vin changes slowly in a DC sense. The drop-out voltage

V = V V , which also happens to be the drain-source voltage of the pass DO in − out element, changes accordingly. If Vin increases above its nominal value, VDO will increase to VDO,1 in order to keep Vout constant. In the MOSFET I-V curve, this change is reﬂected by the shift of the operating point from P0 to P2, which resides on a curve with slightly lower VSG value. This usually would not cause the circuit any trouble as long as Vin are not too high to cause drain junction of the pass element to breakdown. However, it does degrade the circuit eﬃciency, as suggested by Eq. 3.2.

If Vin decreases from its nominal value, VDO will decrease, and the operating point will shift from P0 to P2. There is a limit, however, on how much VDO can be reduced. Recall from Fig. 3.1 that the PMOS is a controllable impedance

(resistance) in the DC sense. As the operating shift from P0 to P2, the controllable resistance Req is reduced accordingly. But the Req is ultimately lower bounded by Rds,ON , which is the on-resistance of the MOSFET in deep triode region. In other words

1 R R = (3.4) eq ≥ ds,ON µ C W (V V ) p ox L SG − TH,p

As VDO is reduced, MOSFET will eventually enter the triode region because the previous gain stage that is driving the pass element can only provide a limited

VSG,max. As VDO is further reduced, the pass element will reach the boundary of saturation and linear region (depicted as P2 in Fig. 3.4).

42 ∆VIN

VBG ∆V1 APT AEA ∆Vout

V β∆Vout FB R1 β

Figure 3.5: Quantitative Line Regulation Analysis

Quantitatively, the amount of DC line regulation can be deﬁned and calculated using Fig. 3.5.

∆V Line Regulation = out or (3.5) ∆Vin ∆V 100 = out %/V (3.6) ∆Vin · Vout

Let AEA, APT be the DC gain of the error ampliﬁer and the PMOS pass element respectively. Suppose a DC voltage increase in the supply voltage ∆VIN is introduced, and the corresponding output voltage shift of ∆VOUT follows:

43 ∆V = A β∆V (3.7) 1 EA · OUT ∆V = A (∆V ∆V ) (3.8) out PT · IN − 1 = A (∆V A β∆V ) (3.9) PT · IN − EA · OUT ∆V A 1 ∴ OUT = PT (3.10) ∆VIN 1+ βAPT AEA ≈ βAEA

As a result, a higher error ampliﬁer gain, which is part of the DC loop gain,

improves the line regulation. Notice that the derivation does not take into

account factors such as the DC line regulations of the error ampliﬁer or voltage

reference, or the op-amp input oﬀset voltages, all of which could introduce

additional error.

In conclusion, DC line regulation is determined by the tunable range of Req

of the pass element, given the output current and voltage it has to maintain.

The method to improve line regulation includes up sizing the pass element

(increasing W/L), and increasing the DC loop gain. However, the analysis in

the following sections would reveal that these methods would lead to increased

parasitics, slower slew rate, and instability. This gives the ﬁrst example of

the various trade-oﬀs involved in power management IC design as indicated in

Section 1.4.3. A common trade-oﬀ is to size the power MOSFET moderately

such that at the maximum output Iout,max and minimum input Vin,min, the

MOSFET would still operate at the boundary of the saturation region (P2).

2. Load Regulation. The DC line regulation measures the capability of the reg-

ulator to maintain Vout with varying Iload in a DC sense [67]. Similar to line

regulation, it can be analyzed through the MOSFET I-V curve in Fig. 3.6.

44 ID V =V GS2 GS,max P =I 3 VGS0 Iout,2 out,max P I 0 out VGS1 I out,1 P 4 Req

V V DS DO

Figure 3.6: Qualitative Analysis of DC Load Regulation using PMOS I-V curve

Suppose the regulator operates under a ﬁxed VDO to maintain a stable Vout

while Iload changes slowly in a DC sense. Iload in this case happens to be the

drain current ID of the PMOS pass element. If Iload drops below its nominal

value to Iload,1, VSG will drop in order to source the same amount of Iload, and

the operating point moves down from P0 to P4 accordingly.

If Iload increases from its nominal value, VSG will need to increase as the operat-

ing point move up from P0 to P3. There is a limit, however, on how much VSG

is available from the preceding driving stage. As the maximum VSG curve is

reached and Iload continues to rise, the operating point will have to move along

the VSG,max curve to the right, which increases VDO and causes the LDO to

45 lose regulation. (V smaller than V V ). As a result, adequate DC out in − DO,defined load regulation requires a similar sizing strategy for the PMOS pass element,

which is to guarantee its operation in saturation region at maximum Iload and

minimum VDO.

3. Drop-out Voltage. As described above and in section 3.1, VDO directly aﬀects

the line regulation, load regulation, and achievable eﬃciency. Unfortunately,

VDO,min is usually determined by the applications (input, output voltages and

eﬃciency required) and beyond a circuit designer’s control. However, if the

drop-out voltage is ﬂexible, it can be determined by the power transistor size,

as the minimum VDO for a MOSFET pass element is

2ID VDO,min = VDS,min = Vov = (3.11) sµCox(W/L)

The larger the pass element W/L is, the smaller VDO,min gets, and the higher η

the LDO achieves.

4. Output Accuracy. The output accuracy of an LDO takes into account all the

internal and external factors that may inﬂuence Vout, including line regulation,

load regulation, reference ﬂuctuation, temperature dependence, and transient

response. As stated in [68], let Vout and Vref be the nominal output voltage and

reference voltage, Vreference, the actual reference voltage applied at the feedback

node, and β be the feedback factor.

V V 1/β +∆V +∆V +∆V V (3.12) out,min ≤ reference · load line TC ≤ out,max

46 includes the EA and PMOS

Vref

Vout a

Vfb

Figure 3.7: Error Voltage Vǫ due to Finite DC Loop Gain

where ∆Vload, ∆Vline, and ∆VTC are voltage variations resulting from load regulation, line regulation, and temperature dependence respectively. The actual reference voltage Vreference can be further expressed as

Vreference = Vref +∆VT C,ref +∆Vlinereg,ref +∆Vos + Vǫ (3.13)

where Vref , ∆VT C,ref , and ∆Vlinereg,ref are the nominal reference voltage, reference temperature dependence introduced error, and reference line regulation introduced error respectively. Methods to reduce their effects are addressed through advanced voltage reference designs [68] and are beyond the scope of this dissertation. ∆Vos is the input offset voltages of the error amplifier within the LDO. Methods of low offset designs are well documented in [54, 69], which usually involves eliminating systematic offset [69] and reducing random offset by larger geometry, smaller input overdrive, and better transistor matching [54].

47 Finally, there is also a term Vǫ, which is the error introduced by limited DC gain of the LDO. This points to a fact that even if all the other circuit components are ideal, and all external error sources are not present, Vo would still be diﬀerent from Vref /β. As shown in Fig. 3.7, assume that the open-loop DC gain of the

LDO is a and the feedback factor Vfb/Vo is β,

a V = V (3.14) o 1+ aβ · ref aβ V = β V = V (3.15) fb · o 1+ aβ · ref 1 ∴ V = V V = V (3.16) ǫ ref − fb 1+ aβ · ref

For a quick estimate of the magnitude of Vǫ, in the LDO in Fig. 3.2, assume a 60 dB DC gain of the LDO, R1 = R2 (i.e. β = 1/2), VBG = 1.225V , and

Vout = 2.45V ,

1 1 V = V = 1.225 V = 2.445 mV (3.17) ǫ 1+ aβ · ref 1 + 103 1/2 · ·

And the resulting output error from Vǫ alone (other error sources ignored) can be found from Eq. 3.12 and 3.13:

∆V V 2.445 mV ∆V = reference = ǫ = = 4.89 mV (3.18) out β β 1/2

In conclusion, when all other factors are equivalent, a higher DC open-loop gain would reduce ∆Vload, ∆Vline, and Vǫ, which all help improve the LDO output accuracy. Unfortunately, increasing the open-loop gain alone would introduce a number of negative eﬀectives to other performance parameters, such as stability.

48 Loop Gain p 1 p x adjusted system

z 1 p p 2 VDD 1 V z fb x z p 1 2 freq p V 3 out V VDD ref R1 Vref A 1 Vfb V out R low R2

A 2 R1

VFB Design of [70]: Dokanian02EL R2

Design of [56]: Rincon−Mora98TCAS−II

Figure 3.8: Methods of improving DC parameters

[56] alleviated the trade-oﬀ by inserting a zero/pole pair, which increased the

loop gain roll-oﬀ from 20 dB/dec to 40 dB/dec for most part of bandwidth, thus

allowing higher DC loop gain and better load regulation. Another method to

improve load regulation is to use ﬂoating Vref [70] to cancel load current change.

A brief illustration of these methods are included in Fig. 3.8.

3.2.2 AC Parameters

1. Stability. The control of the pass element Req in Fig. 3.1 usually involves

negative feedback, and the stability of the control loop should be guaranteed

49 under all line and load conditions. Stability of a linear feedback system can be analyzed using either loop gain or return ratio [54]. This dissertation adopts the ﬁrst approach, where the parasitic phase shift around a negative feedback loop is analyzed. When the parasitic phase shift reaches 180◦, the loop gain should be less than unity (0 dB); and when the loop gain drops to unity, the parasitic phase shift should be less than 180◦ with an appropriate amount of phase margin [33].

There are at least two poles in the LDO feedback loop. One is associated with the node of the error ampliﬁer output (usually also the gate of the pass element) p = 1 . The other is associated with the LDO output, EA Rout,EACpar p = 1 . The challenge with stabilizing the loop lies within the fact that out RoutCout

LDO needs to be stable across a wide range of output current. As a result, pout changes substantially, as the pass element r = 1 varies with I (I ). In ds λID D out applications where an external capacitor is available, a large Cout of 1 to 10 µF can be applied [68] such that pout

In addition to poles, there are also zeros in the loop. Equivalent series resistance

(ESR) R of the external cap C help creates a LHP zero z = 1 , ESR out ESR RESRCout and it can often be used to cancel pEA. However, RESR values are not well predicted and vary with temperature. In addition, large RESR values are required for zESR to cancel pEA eﬀectively, which limits the choice of the capacitor and also leads to high output ripples. There is also a RHP zero in the loop due to the large Cgd of the PMOS pass element.

50 Popular compensation methods include using various forms of buﬀers. [55] pro-

posed inserting a dynamically biased emitter-follower between the error ampli-

ﬁer and the pass element. From a stability point of view, it disconnects the high

output impedance of error ampliﬁer with the large gate parasitic capacitance,

pushing pEA to a higher frequency and improves the phase margin. Another

compensation method is to create an on-chip zero using a high frequency bypass

path or voltage controlled current source (VCCS) [71, 72] to reduce the RESR

value required. As a result, cheaper and smaller multilayer ceramic capacitors

can be used, in addition to the bulky tantalum capacitors. A brief illustration

of these methods are included in Fig. 3.9.

2. Power Supply Rejection. A major advantage of linear regulator is its power sup-

ply rejection (PSR), which is the ability to AC power supply ripples at diﬀerent

frequency ranges. This makes linear regulators useful as post-regulators after

switching converters, whose eﬃciency can be higher but suﬀer from large out-

put ripples. PSR can be deﬁned as PSR = ∆Vout . Though PSR of operational ∆Vdd ampliﬁers are well documented in [73] and [54], PSR for linear regulators was

not well studied until [74] qualitatively described the parameter as follows.

PSR of an LDO can be approximated by the superposition of the inverse of the

loop gain within UGF and the output ﬁltering beyond the UGF, as depicted

in Fig. 3.10: row (a) is the loop gain, row (b) is the inverse of (a), row (c) is

the low-pass ﬁltering Cout and Rout,LDO would oﬀer (i.e. p2), and row (d) is the

superposition of row (b) and row (c). Notice that from row (a) to row (b), zeros

and poles in loop gain transfer function become poles and zeros in the reverse

of loop gain, denoted as “in-band PSR” in Fig. 3.10. Also notice that in row

51 Vin

VBG Vin

AEA VBG APT APT AEA Vout Vout

VFB V R1 FB R1 C1

R2 R2

Design of [55]: Ricon−Mora98JSSC Commonly used high freq bypass (phase lead)

Vin

VBG APT AEA Vout

V FB R1

R2 C1

on−chip zero generation

Design of [71]:Chava03TCAS−I and [72]:Lin08TCAS−II

Figure 3.9: Frequency Compensation Methods of a PMOS LDO

(c), the low-pass ﬁltering would be limited by ESR, i.e. beyond frequency of

zESR there will be no low-pass ﬁltering eﬀect since Cout is a virtual short and

the PSR is merely the division ratio of Rds,P MOS and RESR. As a result, p2 and

z cancels each other, which keeps very good PSR (low in y axis since PSR 1 −

52 is expressed in negative dB) for a conventional PMOS LDO on the left. (The capacitor-free LDO scenario will be discussed later in the dissertation.)

Quantitatively, PSR can be calculated using a method similar to DC line regulation. Assume the same notation of letting AEA,APT be the open-loop gain of the error amplifier (1st stage) and the pass element (2nd stage), Ap1 be the power gain of the error amplifier, β be the feedback factor R2/(R1 +R2). An AC small-signal analysis can be drawn as in Fig. 3.11. First, set the small-signal vdd of the 2nd stage (pass element) to zero, assuming all ripples are injected from error amplifier supply rail.

∵ v = β v A + v A (3.19) EA · out · 1 dd · p1 ∴ v = v A out EA · PT

= βAEAAPT vout + APT Ap1vdd (3.20) A A ∴ v = PT p1 v (3.21) out 1 βA A dd − EA PT

Next, set the small-signal vdd of the 1st stage (error ampliﬁer) to zero. All ripples are now injected from the source of the pass element.

∵ v = β v A (3.22) EA · out · EA ∴ v =(v v ) A out EA − dd · PT = βA A v A v (3.23) EA PT out − PT dd A ∴ v = − PT v (3.24) out 1 βA A dd − EA PT

53 Off−chip Cap External Cap−free

Loop Gain Loop Gain p* p* 1 1

p p* p p* 2 2 1 2

z p 1 1 freq freq p 3 p p (a) 2 3

In Band PSR In Band PSR

p z p 1 1 p 2 1

freq freq

(b)

Output filtering Output filtering

p 2 p z 2 1

freq freq

UGF

p p In BW1 out of BW1 In BW out of BW

freq freq

(d)

Figure 3.10: Pole Locations and PSR of a PMOS LDO

54 vdd = 0 vdd = 0

VBG VBG

V V FB R1 FB R1 β β R2 R2

Figure 3.11: PSR derivation

Finally add the two together according to the property of superposition.

A A A (1 A )A v = PT p1 v + − PT v = − p1 PT v (3.25) out 1 βA A dd 1 βA A dd 1 βA A dd − EA PT − EA PT − EA PT

Notice that if Ap1 = 1, i.e., the error ampliﬁer has unity power supply gain (no power supply rejection), vout = 0 regardless of the amplitude of vdd. If Ap1 = 0, v = APT v . As a result, A = 1 turns out to be best for the PSR of a out 1−βAEAAPT dd p1 PMOS-based LDO. The counter-intuitive conclusion can be understood by the fact that Ap1 = 1 leads to an identical copy of the supply ripple being fed from the pass element’s source to the pass element’s gate, which cancels the ripple eﬀect altogether (similar to a common-mode topology).

Following this principle, a number of PSR enhancing techniques have been proposed. A resistive divider stage is often inserted between the pass element and error ampliﬁer gain stage, either with low impedance to the power supply

(diode-connected MOSFETs [75]) or high impedance to the ground (cascode

55 device [76]). As a result, the supply gain Ap1 was signiﬁcantly increased and

PSR of the LDO greatly improved. [77] proposed a ripple feed forward path

that tracks Vgate to VS. Other approaches to boost PSR include cascoding the

pass element [78, 76, 79]. Cascoding eﬀectively increases the output impedance

of pass element, which help improve out-of-band PSR at high frequency, which

is ultimately limited by the voltage division from the supply to the output

node. However, VDO increases with cascoding, and that degrades the regulator

eﬃciency. A brief illustration of these methods are included in Fig. 3.12.

3. Noise. When an LDO is used to regulate power supply to RF blocks such as

VCO, output noise of the regulator becomes a major concern. Typically, noise

in an LDO is speciﬁed as output-referred noise [80]. The input referred noise of

the LDO is ﬁrst found, then multiplied by the close-loop gain, Vout/VBG.

The major contributors to LDO output noise are the bandgap reference, feed-

back resistors, and the error ampliﬁer input stages. Interestingly, the large pass

element do not contribute a signiﬁcant amount of output noise due to the large

gm, which reduces its noise contribution when referred to the gate input [81].

A low noise voltage reference is needed for a low noise LDO design. A common

method is to use a large RC filter. However, it is difficult to filter out the

1/f noise, and a large capacitor could slow down the regulator start-up. To

reduce the thermal noise from the feedback resistor would require using smaller

resistors, which leads to more quiescent current ﬂowing through the pass element

and the feedback network. Finally, the error ampliﬁer input stage contributes to

the input-referred noise (hence output noise, as they are related by a constant

56 Vin

Vin

Vout VBG V out VBG AEA

AEA R1

R1 VFB VFB R2 R2 Design of [75]: Hoon05CICC Design of [76]:Wong06ESSCIRC

Vin V in Charge Vref Pump AEA

V Vref BG Vout

A AEA EA Vout

R1 V R1 VFB FB

R2 R2

Design of [77]:El−Nozahi10JSSC Design of [79]:Gupta07ISSCC

Figure 3.12: Power Supply Rejection Enhancement Methods for a PMOS LDO

Vout/VBG factor). 1/f ﬂicker noise is usually dominant, and it can be reduced

by increasing W and L of the input pair. The penalty is obviously a larger area.

Similar to low noise instrument ampliﬁer, chopper stabilization techniques [82]

can be applied to the error ampliﬁer and reduce 1/f noise accordingly.

57 Rs Vin Vout

Zload Zload,1

Iout Iout,1

Thevenin Equivalent

Figure 3.13: Thevenin Equivalent Circuit in Analyzing Overshot and Undershot

3.2.3 Transient Parameters

As a power supply module, LDO would face various degree of load variations,

such as sudden load increase and decrease from digital processors as their computing

need changes. As a result, the output voltage of the LDO would ﬂuctuate, experience

undershot and overshot, and takes ﬁnite amount of time settle to the new values.

The undershot and overshot problem can be qualitatively analyzed using Thevenin

equivalent circuit shown in Fig. 3.13.

Assume that at time t0− that a load branch Iout,1 is switched on. The overall load resistance suddenly decreases. In the small-signal sense, if the Thevenin equivalent of linear regular has a high internal impedance, than the output voltage would change dramatically from t0− to t0+, which will cause a huge undershot. The magnitude of the undershot would be related to the small-signal impedance at the output node of

58 the linear regulator, as well as the loop response time. The finite response time is due to the finite loop bandwidth (BW) and Error Amplifier (EA) Slew Rate (SR) [55]:

1 1 ∆Vout,EA ∆t1 + tSR = + Cpar (3.26) ≈ BW BW ISR As a result, transient response can be improved by reducing the settling time.

For example, increasing IQ of the error amplifier would increases the slew rate at the pass element gate, as SR I /C The obvious downside is the increase in ∝ Q par power consumption. The bipolar emitter-follower buffer proposed in [55] not only helped with stability (as discussed earlier), but also increases the gate drive current during slewing period without huge increase in error amplifier quiescent current: extra current is dedicated to improving the gate charge speed, and the error amplifier sees a reduced Cpar and can therefore be designed to be more power efficient. [62] further improved the buffer technique through Buffer-Impedance Attenuation (BIA): a BJT used in series-shunt negative feedback, which enhances the buffer performance even when a PMOS source-follower is used.

Transient response can also be improved by reducing the small-signal impedance at the output node. [83] proposed using a current-feedback amplifier (CFA) as the buffer between the error amplifier and the pass element. The CFA then introduces a low ac impedance path at the output, which achieves fast transient with low power consumption. [84] used dual-loop replica biasing, with a low BW loop for voltage regulation and a high BW low-dropout source follower for fast transient. It also leverages voltage positioning, such that ∆VAC = ∆VDC , or in this dissertation’s notation, letting RS in Fig. 3.13 be equal to Req in Fig. 3.1. [85] replaced the conventional error amplifier with a high slew rate push-pull amplifier (translinear Gm

59 cell) such that ISR >Ibias. A brief illustration of these methods are included in Fig.

3.14.

3.3 External Capacitor-Free LDO

Almost all LDOs described so far use an external capacitor Cout at the output of the LDO as shown in Fig 3.2. With the development of advanced sub-micron

CMOS technologies and the economic beneﬁt of process scaling and integration, LDOs are now being used in large numbers on a system-on-chip (SoC) settings. For the conventional LDO topologies, each LDO would at least require an external capacitor and its dedicated output pin. The combined eﬀect, therefore, includes a large number of external bulky components, more PCB board space, increased pin count of the IC, and higher Bill-of-Material (BoM). This goes against the trend in consumer portable electronics, which is pushing for higher integration and smaller form factor. It is also undesirable for future green electronic systems, which are characterized by their compactness and manufactureability.

In this section, the challenges and methods of designing an external capacitor-free

LDO are discussed. A new approach that better addresses power, eﬃciency, supply voltage, and die area will be presented in the next section.

3.3.1 Challenges

The challenges for designing external capacitor-free LDO is best understood by studying the role of Cout in a typical LDO topology. There are at least three purposes for employing Cout in an LDO:

60 Vin

VBG Vin

AEA APT VBG

V APT out AEA

VFB Vout R1

VFB R1 R2

Design of [55]: Ricon−Mora98JSSC Design of [62]: Al−shyoukh07JSSC

Vin Vin V BG

AEA V CFA out VBG Vout

AEA

R1 R1 V VFB FB R2 R2

Design of [83]: Oh07TCAS−II Design of [84]: Hazucha05JSSC

V BG Vin Vin gm

gm Vout

VFB R1

I out

R2 Design of [85]: Man07TCAS−II

Figure 3.14: Transient Response Enhancement Techniques for a PMOS LDO

61 1. Cout stabilizes the feedback loop by creating the external dominant pole pout =

1 , as described in section 3.2.2. Although the pole position would still RoutCout

vary from heavy load to light load (due to changing Rout), but RESR values

are usually well chosen such that the ampliﬁer dominant pole are canceled out

appropriately, and that high frequency poles/zeros do not fall below the Unity

Gain Frequency (UGF).

2. Cout smooths the voltage droop during load transients. As described in section

3.2.3, it takes the LDO feedback loop at least ∆t1 to respond to any Iload change,

during which the Vout would experience overshot or undershot. A signiﬁcantly

large Cout could charge or discharge itself to absorb or provide for the excess

dVout transient current, as I = Cout dt , before the LDO feedback loop responds.

Notice that the contribution of Cout in reducing the transient undershot and

overshot was not included in the analysis using Thevenin equivalent in Fig.

3.13. If included, when calculating the Thevenin equivalent circuit at AC,

RS will include the 1/sCout impedance shunt to ground. For higher frequency

sinusoid stimuli, which are exactly what an abrupt load transient generates,

R 0 faster at the frequency of interest if a larger C is included. This S → out is in agreement with the analysis above using only the characteristics of the

capacitor.

3. Cout improves PSR performance. As explained in [86], at high frequencies, e.g.

100 kHz and beyond, the output impedance of the pass element and Cout forms a

low pass ﬁlter that ﬁlters out high frequency supply ripple. The only limitation

of this benefit is the ESR of Cout: the low pass filtering effect diminishes at very

62 high frequency, e.g. 10 MHz and beyond when the Cout is shorted and the ESR

and pass element output impedance forms a resistive divider [74].

As a result, capacitor-free LDO design will face signiﬁcant challenges in but not limited to stability (frequency compensation), load transient response, and PSR performance due to the absence of Cout.

3.3.2 Existing Solutions

Existing designs of an external capacitor-free LDO fall into two categories: two- stage approach and three-stage approach. In both approaches, the output power

MOSFET is considered the last gain stage. Depending on the error ampliﬁer structure

(whether it is a single stage, or more precisely, single dominant pole structure, or a two-stage two-pole system), the division can be made accordingly.

Generally speaking, three-stage designs enjoy higher DC loop gain, therefore require less on-chip compensation capacitor (die area). However, multi-stage system are prone to introduce complex poles, which means even though the compensation capacitance can be small, but certain conditions have to be guarded carefully. As will be discussed later, the output power MOSFET stage needs to be kept above minimum power level. Two-stage designs, on the other hand, require larger compensation capacitance, but would not have as many inherent poles and additional phase shift.

It can be very attractive when power consumption is a premium, but the on-chip die area overhead is not negligible.

63 [58] first proposed a capacitor-free LDO based on a three-stage approach: Damp- ing Factor (ζ) Control (DFC) method used in low voltage, multi-stage amplifier driving large capacitive load [87]. DFC was an improvement on Nested Miller Compensa- tion (NMC), a well known low voltage high gain multi-stage amplifier compensation method [88, 89]. Instead of nesting Cm1 and Cm2, [87] disconnected Cm2 from the output node to reduce loading, which improved BW, and kept Cm2 connected to the output of the first stage with an extra gain stage to boost Cm2 effect, which reduced the magnitude peaking of the loop gain around unity gain frequency (UGF) from the complex pole pair. [59] improved the method of [58] by an alternative connection of

Cm2 without the extra gain stage.

[32] proposed a capacitor-free LDO from a different perspective. If a single-stage error amplifier is used, topology wise, the LDO is very similar to a classic two-stage operational amplifier. Miller compensation, which is the most common compensation method for a two-stage opamp, can be easily applied. The difference is that load current varies by orders of magnitude, which means the gain of the second stage also varies significantly. To guarantee the effectiveness of the pole-splitting, a relative large on-chip compensation capacitance is needed to take advantage of the Miller effect. [32] proposed a “pseudo-differentiator”, which effective amplifies the capacitative feedback current. It also embodied Ahuja compensation method [90], which removed the RHP zero by blocking the capacitative feed forward path while reducing capacitative loading for the input stage.

Methods of implementing an external capacitor-free LDO other than three-stage or two-stage approaches do exist. For example, [91] proposed a single-transistor-control

64 Vin Vin

Vref Vref AEA gm AEA gm Vout Vout CM1

V C V FB M2 FB CM1 R1 R1 Damping −g Q−reduction C Factor m cf Control buffer R2 R2

Design of [58]: Leung03JSSC Design of [59]: Lau07JSSC

Vin V sg Vin V ref VrefV out AEA Vout V ov C M1 R1

R2 Design of [32]: Milliken07TCAS−I Design of [91]: Man08TCAS−I

Figure 3.15: Existing Methods of Designing External Capacitor-free LDOs

65 (STC) LDO, which replaced the EA with a ﬂipped voltage follower. Though the small- signal output impedance is reduced, which will improve the load transient response, a signiﬁcant draw back is the lack of DC line regulation. However, V < V +V V , in out gs − ov which greatly compromised line regulation range. As a result, STC-LDO and its various forms will not be discussed in details in this dissertation. A brief illustration of these methods are included in Fig. 3.15.

3.4 Current-Area Eﬃcient Capacitor-free LDO

3.4.1 Motivation: Eﬃciency Size Trade-oﬀ

As described in section 3.3.2, a major limitation in prior arts on capacitor-free

LDO is the trade-off between size and efficiency: In the two-stage approach, a significant amount of on-chip compensation capacitance (23 pF) was employed to compensate for full load range (0 - Iout,max) [32]. In the three-stage approaches, a minimum load current of Iout,min ranging from 1 mA [58] to 100 µA [59] is required for loop stability. This minimum current constantly drains the battery and degrades the system efficiency. Although 100 µA is small compared to Iout,max of 100 mA, it still larger than the SoC average sleep current in standby-power-critical applications. Even if an

LDO is not required to operate under extremely low Iout, in which cases the LDO itself will be shut down to save power (also known as hibernate mode), having a truly stable regulator at zero output current helps guard against unexpected load transient dips. Hence, a new capacitor-free topology that is both eﬃcient and compact is needed.

66 "Excessive" Contributing to Gain the Miller effect

G1 G2 G3 VREF Vout

p1 p2 p3

CM2

CM1

(a)

Excessive Gain Reduction

G1 G1 G’2 G’3 VREF Vout

p* p’1 p’2 p’3

CM2

CM1

(b)

Figure 3.16: (a) Excessive Gain in Existing Solutions and (b) Excessive Gain Reduc- tion

3.4.2 Approach: Excessive Gain Reduction

The main observation from existing three-stage capacitor-free LDO designs is that not all gain contribute to the desired Nested Miller eﬀect. DC gain in stages that do not contribute to Miller pole-splitting should be minimized, and if possible, be redistributed to stages that do. As a result, given a total DC gain budget to meet the

LDO accuracy requirement, the stability of the LDO can be greatly improved [92].

67 The input diﬀerential ampliﬁer, G1, is an example of an excessive gain stage, as seen in Fig. 3.16 (a), which analyses the stability of a conventional three-stage nested-

Miller capacitor-free LDO. G1,G2,and G3 represents the input diﬀerential stage, high gain intermediate stage, and the common-source pass element output stage respectively. At least three parasitic poles are present in the loop: p1 = 1/(R1CM1G2G3), p2 = 1/(R2CM2G3), and p3 = gm3/C3, where Ri,Ci and gmi refer to the output resistance, parasitic capacitance, and transconductance of gain stage Gi (i = 1, 2, 3) respectively [46].

Notice the gain G1 does not contribute to creating the dominant pole p1, or the pole-splitting of p2 and p3. Other than tracking the diﬀerence between the actual output Vout and the desired output VREF , G1 is an excessive gain stage that eats into the total DC gain A (0) = G + G + G budget . Thus, this paper proposes v |dB 1 2 3 inserting an attenuating stage, G (in dB), to reduce the excessive loop gain G . − 1 1

G2,G3 and gm3 can therefore be designed with larger values, enhancing the Miller

′ ′ eﬀect by pushing p1 to a lower value of p1 and splitting p2 and p3 further apart to p2

′ and p3.

Ideally the attenuation should cancel the excess gain completely, leading to a unity gain diﬀerential ampliﬁer. In practice, the attenuation might not be exactly equal to the excessive gain due to the mismatch. However, a smaller than needed attenuation would still be helpful, as long as it does not add additional parasitic pole, p∗, into the loop.

68 Vin

M3 M4 M10 M11

M7 MPT CM R1 Vout V BG Ccf

Vfb Ibias R2 M1M2 M5 M6 M8 M9

Input Current−Differencing (CD) Gain Stage Output Stage

Transistor aspect ratio (W/L) (um)

M1=6/2 M4=8/2 M7=20/1 M10=M11=24/1 Ibias =20uA

M2=2/2 M5=2/2 M8=5/1 MPT=7200/0.18 CM =4pF

M3=8/2 M6=6/2 M9=5/1 R1=R2=100K Ccf =500fF

Figure 3.17: Schematic of the Proposed Capacitor-free LDO

3.4.3 Method: Input Current-Diﬀerencing

The schematic of proposed capacitor-free LDO is shown in Fig. 3.17. Instead of using an operational amplifier as the error amplification block, it consists of current- differencing (CD) stage (M M ), positive gain stage (M M ), PMOS pass 1 − 6 7 − 10

element (MPT), and resistive network (R1,R2). The CD stage is a CMOS version of [93], also widely used in analog signal processing and frequency ﬁltering [94]. The

LDO is internally compensated by MOSFET capacitance CM and Ccf of 4.5 pF and

500 fF respectively. No external capacitor is needed. Other component values and transistor aspect ratios are listed in Fig. 3.17.

69 Input current-diﬀerencing technique was originally proposed in [93] for bipolar monolithic opamp design. As shown in Fig. 3.18 (a), A “current mirror” was added across the common-emitter input, resulting in a current mode operation where the input currents are compared or diﬀerenced. With input resistance converting input voltage into current, a wide common-mode input range can be accommodated since both inputs are built-in biased with only +VBE above ground. A CMOS version,

however, requires a third current mirror, as shown in Fig. 3.18, due to its zero gate

current.

There are two major advantages when the technique is applied in an LDO. First

of all, it allows low voltage operation. Notice that M2, M3, M4 and M6 can be viewed

as an N-input diﬀerential pair, except for the removal of the tail current source due

to the built-in biasing by the diode-connected M1 and M5. As a result, the minimum

supply voltage could be as low as V + V 0.9 1.1V . In [59], the conventional gs ov ≈ −

P-input diﬀerential pair would require Vgs + 2Vov or Vref + Vgs + Vov, whichever is

higher, as shown in Fig 3.18. Secondly, this conﬁguration renders a smaller feedback

factor β that helps reducing the excessive loop gain that threatens stability in zero

load [58, 59]. An alternative approach to lower loop gain would be reducing gm, since

changes in ro shifts dc gain and the dominant pole simultaneously (constant GBW).

Since g = 2ID in saturation region, reducing g would require either increasing V , m Vov m ov which is already limited in a low voltage situation, or lowering ID, which is eﬀective only to a certain extent before the input devices enters weak inversion where g = 2ID m Vov is no longer valid.

The stability of the proposed LDO can be analyzed as follows. Fig. 3.19 (a) shows

that the LDO consists of a basic ampliﬁer a(jω) and a feedback network f(jω) using

70 I1 Q1

+ I2 − I2 Q2 + CR1 −

(a) "Current mirror"

VDD V M3 M4 sg

V ov I2 M1 M2 M6 M5 CMOS Current−Differencing

(b) This Work [37]: Hu10AICSP

V ov

VDD V V ref sg

V ov

Figure 3.18: Principle of Input Current-Diﬀerencing: (a) bipolar implementation (b) CMOS version (c) Advantages over Prior Arts

71 Gain (dB) Basic amplifier

20log a0 a(jw) p 1 20log a(jw) Loop Gain 1 20log f f(jw) peeking w Feedback network p p 2 3

(a) (b)

a(jw)

CM f(jw) Cgd R2 v vfb out

1 v1 v2 v3 v4 g m_M2 Cin2 g v1 rcf r1 C g v3 r2 g v4 r3 mI Cp g v2 1 mG C2 mL C3 m_M4

Ccf v = 0 ref 1 v5 g g v5 m_M6 Cin1 m_M5

(c)

Figure 3.19: LDO Stability Analysis (a) Two-port Model (b) Bode Plot (c) Small- signal Equivalent Circuit

72 two-port analysis. Fig. 3.19 (b) show the gain magnitude versus frequency for the

basic amplifier of the LDO, where different feedback factor f influencing the loop gain.

The key to stabilizing the LDO is designing a small feedback factor f = 1/gmM1 1/gmM1+R2 in reducing the loop gain to avoid the residual a(jω) peaking in addition to the Q- reduction compensation [59]. The stability of the LDO can be analyzed in details with the small-signal equivalent circuit in Fig. 3.19 (c). Let gmMi be the transconductance of transistor M (i = 1, 2, , 10). Let g , g and g be the transconductance for i ··· mI mG mL the CD stage (M M ), gain stage (M M ), and output stage (MPT) respectively. 1 − 6 7 − 10

Let ri, Ci (i = 1, 2, 3) be the output resistance and capacitance for each of the three

stages. Let rcf , Cp be the output resistance and capacitance associated with the drain

of M2, and Cgd be the gate-drain capacitance of MPT.

Assuming ideal frequency response of the Q-reduction current buﬀer (M M ) 3 − 4 [59], the loop gain of the LDO can be found by breaking the voltage feedback before

R2 and calculating the open-loop transfer function from Vfb to Vout:

v (s) L(s)= out = vfb(s) 1/gmM1 g g g r r r 1+ s(r C Cgd ) s2( Cm(Cgd+C2) + Cgdrcf Ccf ) 1/gmM1+R2 mI mG mL 1 2 3 cf cf gmL gmGgmL gmL · − − − · (1 + sC g g r r r )(1 + s CmCgdn(gmL gmG)+Ccf C3gmG+CmCcf gmGgmLrcf + s2 (Cgd+C2+Cocf ) C3 ) M mG mL 1 2 3 CmgmGgmL gmGgmL (3.27)

Since the transconductance of the pass element gmL varies greatly with the output current, the stability of the LDO should be analyzed in three diﬀerent load conditions.

In the case of moderate to high output current (Iout > 1mA), the loop gain can be

simpliﬁed as:

73 1/gmM1 v (s) 2 gmI gmGgmLr1r2r3(1 + s(rcf Ccf )) L(s)= out = 1/gmM1+R · (3.28) C +C (C +C2+C )·C3 vfb(s) (1 + s/p )(1 + s gd cf + s2 gd cf ) 1 gmG gmGgmL

where p1 = 1/(sCM gmGgmLr1r2r3) is the dominant pole. Two real roots p2,p3 exist for the quadratic function as (4(C + C + C ) C )/g (C + C )2/g gd 2 cf · 3 mL ≤ gd cf mG holds due to a big gmL. Zero z1 = 1/rcf Ccf cancels p2, and p3 is located at a much higher frequency.

In the case of low output current (I : 100µA 1mA), the loop gain expression out − needs to be analyzed in full as Eq. 3.27. Though p1 = 1/(sCM gmGgmLr1r2r3) remains the dominant pole, the discriminant of the quadratic function in the denominator

− · ∆ = [ CmCgd(gmL gmG)+Ccf C3gmG+CmCcf gmGgmLrcf ]2 4(Cgd+C2+Ccf ) C3 is less than 0 due CmgmGgmL − gmGgmL to a smaller gmL. Thus, p2 and p3 form a non-dominant complex pole pair located

at ω = gmGgmL with frequency peaking in magnitude due to a large Q-factor 2,3 (Cgd+C2)·C3 q [59]. An optional Ccf of 500 fF is used here to reduce the peaking.

In the case of near zero output current (I : 0 100µA), g is minimal. This out − mL would result in an unstable LDO in existing topologies [58, 59] as the complex pole

magnitude peak rises above 0 dB near crossover. However, the feedback factor f =

1/gmM1 from the CD stage of the proposed LDO lowers DC loop gain and eﬀectively 1/gmM1+R2 suppresses the peak below 0 dB even with zero output current.

3.4.4 Simulation Results

The proposed LDO has been simulated in TSMC 0.18 µm 1.8V/3.3V RFIC

1P6M+ process with key technology data listed in Table 3.1. It regulates 1.2 to

1.8 V input supply to ﬁxed 1 V output with 51 µA quiescent current and 100 mA

maximum outputs current. No minimum output current is required, i.e., the LDO is

74 Figure 3.20: Transient response of LDO under diﬀerent output parasitic and corner conditions Iout: 20 mA/div., Vout: 100 mV/div., 10 us/div.

stable at Iout = 0. Line regulation at output Iout = 0 and Iout = 100mA are 0.223%/V

and 0.728%/V respectively. Load regulation is 10.7ppm/mA at Vin = 1.2V . Fig.

3.20 shows the transient response at various load parasitic and process corner condi-

tions. Worst-case 0.5% error recovery time is less than 13 µs under full load transient

(0 100mA) of 1 µs rise and fall time. Power supply rejection ratio (PSRR) is -41 − dB at 1kHz, and output noise is 6.3 µV/sqrtHz and 640 nV/√Hz at 100 Hz and 10 kHz respectively.

To demonstrate the advantage of proposed work, a brief comparison with existing work is shown in Table 3.2. This work reduces Iout,min to zero [59] and compensation

cap from 21 pF [32] to 4.5 pF, which contributes greatly to the area saving. A ﬁgure of

75 1.8 V NMOS 1.8 V PMOS

Vth,0 (mV) 475 449

tox (nm) 4.08 4.08 2 Cox (fF/µm ) 8.46 8.46 ′ 2 k = 1/2µCox (µA/V ) 340 70 Breakdown Voltage 1.8 1.8

Table 3.1: TSMC 0.18 µm CMOS Process Technology (2V nominal devices)

[59] [32] This work [46]

Process CMOS 0.35 CMOS 0.35 CMOS 0.18 Year 2007 2007 2009

Vin (V) 1.2-3.3 3-4.2 1.2-1.8

Vout (V) 1 2.8 1 Settling time (µs) Not reported 15 13

Iout,max (mA) 100 50 100

Iout,min (µA) 100 0 0

Iq (µA) 100 65 51 On-chip cap (pF) 6 21 4.5 Area (mm2) 0.125 0.120 0.020 Area/L2 1.020 0.980 0.617 FOM 0.120 0.273 0.027

Table 3.2: Performance Comparison of the Capacitor-free LDOs

76 Category Parameter Specs

V 2.5-5 V Voltage in Vout 2.3 V I 0 Current out,min Iout,max 100 mA Output external not required Capacitor on-chip parasitic 0-100 pF Eﬃciency I 100µA Q ≤

Table 3.3: Capacitor-free LDO Design Speciﬁcations

merit adapted from [84] defined as F OM = Iout,min+Iq Conchip takes both effects into Iout,max × Cout,par account. The smaller the FOM, the better current-area efficiency the LDO achieves.

Notice that in Table 3.2, the three LDOs are manufactured in diﬀerent CMOS

processes. Even though the FOM, as well as area comparison have all taken the

process advancement into account, a more fair comparison would be to design both

the proposed LDO and an existing three-stage approach capacitor-free LDO is the

same process, and ideally designed for the same speciﬁcations. This dissertatin went

on and did that. A sample proof-of-concept set of LDO speciﬁcations as listed in Table

3.3, and the common CMOS process chosen was the ON Semiconductor (previously

AMIS) 0.5 µm CMOS process available through MOSIS educational service. The two

LDOs are designed and placed side by side in 1.5mm 1.5mm area within a DIP40 × package.

Fig. 3.21 shows the Bode plots of the conventional and proposed capacitor-free

LDOs at Iout,min = 100µA. Notice that both LDO have the same DC gain of 84 dB, but the proposed LDO has a lower dominant pole and hence a smaller unity

77 Peaking below 0 dB Gain Plot

Conventional: “stay alive” Proposed UGF

Phase Plot

Conventional: “stay alive” Proposed

Figure 3.21: Bode plots of the conventional and proposed LDOs at Iout,min = 100µA

gain frequency (UGF) of 200 kHz instead of 2 MHz 5. The phase margins are 60◦

(conventional) and 90◦ (proposed) respectively. Fig. 3.22 shows the same Bode plots when the “stay alive” Iout,min of 100 µA is not available. Notice that the conventional design is not stable because of the gain magnitude peaking, which leads to negative phase margin. The proposed design, on the other hand, is stable with a phase margin of 70◦.

5A smaller UGF inevitably slows down loop transient response. However, the settling time of a LDO is usually limited by the slew rate at the gate of the pass element [95, 96]. Thus, it is assumed in the paper that the trade-oﬀ in UGF is acceptable, as long as the settling time does not deteriorate signiﬁcantly (as seen later in Fig. 3.23 and 3.24). In addition, transient enhancement techniques reported in [95, 96] can be always be applied as needed.

78 Peaking above 0 dB

Gain Plot

Conventional: “stay alive” N/A UGF Proposed

p p’ 1 1 p p 2 3

Phase Plot p’ 2 p’ Conventional: “stay alive” N/A 3 Proposed

Figure 3.22: Bode plots of the conventional and proposed LDOs at Iout,min = 0

Fig. 3.23 and 3.24 show the output voltage waveforms of the conventional and

proposed LDOs in face of full-range load current transients (0 to 100 mA in 1 µs

[58, 59, 32, 95]). In Fig. 3.23, “stay alive” current Iout,min of 100 µA is assumed, and both LDOs are stable, though they have various degrees of undershot and overshot.

In Fig. 3.24, however, when “stay alive” current is not available, the conventional

LDO oscillates, but the proposed LDO remains stable.

The power eﬃciency of an LDO for portable application is often measured by its current eﬃciency during normal operation [62] and its total battery current drain during sleep [46]. Since the proposed technique would not require any “stay alive”

79 Conventional: Vout

Conventional: Iout

Proposed: Vout

Proposed: Iout

Figure 3.23: Load transient waveforms with 100 µA of “stay alive” current. V: 400 mV/div, I: 25 mA/div, t: 50 µs/div

IQ Iout,min Ibatt,idle

Conventional 100 µA 100 µA 200 µA Proposed 65 µA 0 65 µA Saving 67.5%

Table 3.4: Battery current saving from the proposed technique

current Iout,min to combat zero-load oscillation, the total battery current drain during

idle can be greatly reduced, as indicated in Table 3.4.

80 Conventional: Vout

Conventional: Iout

Proposed: Vout

Proposed: Iout

Figure 3.24: Load transient waveforms without “stay alive” current. V: 200 mV/div, I: 25 mA/div, t: 50 µs/div

3.4.5 Measurement Results Test Solutions Design

To effectively test the fabricated circuits, a complete set of test solutions, including on-chip test structure, chip-package interface, and PCB test board, need to be designed. In fact, IC testing is by no means trivial, and it has grown into a highly specialized field of its own [97]. In industry, verification and production test represents up to 50-60% of the total time and cost in making Very Large Scale Integrated

(VLSI) chips, making it the biggest single expense of the chip fabrication process

81 Vin

Vout

LDO Rmin VX R’min

M N M’N

gate drive signal

on−chip test off−chip test

Figure 3.25: On-chip test structure with oﬀ-chip option

[98]. It was also predicted by the Semiconductor Industry Association in 2003 that by 2014, the cost of testing a transistor would exceed the cost of its manufacturing

[99].

In academic settings, the need for test engineering education has yet to be fully recognized in most schools and institutions [99, 98, 100, 101, 102]. Though certain approaches that do not require expensive automatic test equipment (ATE) have been proposed for mixed-signal IC testing [102], the task of testing power management ICs at academic institutions with low cost and low complexity remains a challenge.

The test solution design starts with the on-chip test structure. Since capacitor-free

LDOs are most likely to be used to power on-chip loads, an on-chip load test structure

[95] is included in the design, as seen in Fig. 3.25. A gate drive signal will turn on and oﬀ MN periodically to introduce load current variation from 0 to Iout,max. Vout and VX

− are directly monitored by the scope, while I is obtained indirectly as Vout VX . The out Rmin

82 VDD

Pad Signal

VSS

Figure 3.26: Schematic of the Electrostatic Discharge (ESD) protection circuit

drawback of this test structure is the variation of Rmin after fabrication. As a result,

′ an oﬀ-chip load test option with external high precision Rmin is also supported.

When the LDO cores are connected to the padding frames, Electrostatic Discharge

(ESD) protection should also be considered. Without proper protection, human or machine touch of the packaged chip could introduce transient high voltage up to

1000 V, which can easily damage the MOSFET gate or open-drain connected to the pad. In industrial products, sophisticated ESD protection circuits are designed for each type of input/ouput pad. In this design, however, a simple two diode-connected

MOSFET was used for ESD protection. The schematic of the ESD is shown in Fig.

3.26. During normal operation, both the top PMOS and bottom NMOS are oﬀ, introducing no additional loading to the power rail. When the input voltage starts to rise above VDD, the top PMOS would clamp the pad voltage to be one VSG above

VDD. Likewise, the bottom NMOS would clamp the pad voltage to be one VGS below

83 VDD PMOS

NMOS VSS

Figure 3.27: Die Photo showing the Electrostatic Discharge (ESD) structure

VSS (GND in this design). Both MOSFETs are designed to be suﬃciently large to be able to carry the large transient current. The photo of the ESD structures after fabrication is shown in Fig. 3.27. Notice that there are two guard rings around the two power MOSFETs respectively. The N-type guard ring of the NMOS and the source of the PMOS should be connected to the highest voltage (VDD), and the P-

type guard ring for the PMOS and the source of the NMOS should be connected to

the lowest voltage (VSS).

84 Conventional Proposed

on-chip load test

Figure 3.28: Die Photo of the Dual-Core Capacitor-Free LDO

As mentioned earlier, both the proposed and the existing LDOs are implemented on the same chip in ON Semi 0.5 µm CMOS process. A die photo of the “dual core” power management chip is shown in Fig. 3.28, which also shows the bond wires that connects the I/O pads to the package. The core of the two LDOs are laid side by side, each with their dedicated bias, power supply, and ground. A zoom-in view shows the on-chip resistance (implemented using High RES poly), capacitance

(MOSFET capacitance), the pass element (multiple instance, multiple ﬁnger parallel connection), and the error ampliﬁers. (Fig. 3.29)

85 Cap Cap Pass Element error amplifier

Proposed Conventional

Figure 3.29: Detailed Die Photo showing Integrated Circuit Components: Resistors, Capacitors, Pass Elements, and Error Ampliﬁers.

To test the packaged chip, a customized printed circuit board (PCB) was also designed, the schematic of which is shown in Fig. 3.30. Due to the lack of on- chip reference generation, a number of external stimuli other than Vin and GND are required, which are accommodated by test points. The external forced voltages are supposed to be tuned as the biasing conditions of key stages are monitored.

In the conventional LDO, the biasing current of the input pair will be monitored.

In the proposed LDO shown in Fig. 3.17, the biasing current of the second stage

(M M ) is monitored by having an identical MOSFET M as M with gate and 7 − 10 iprb 9

86 Figure 3.30: Schematic of the Printed Circuit Board (PCB)

source connected. The open drain of Miprb is pinned out to pin Iprb,2, such that a pull-up resistance R4 : 75KΩ in Fig. 3.30 can be used to monitor the current.

Oﬀ-chip test structure takes up a large portion of the PCB area, which includes power NMOS (Q Q : ZVNL120A, R = 10Ω, BV= 200 V, 0.5 < V < 1.5, 1 − 2 ds,ON th

Pmax = 0.25W ) as switches and 10 Ω power resistors as loads. An external gate-drive signal can be applied to the gate of Q Q to introduce the load variations. The 1 − 2 presence and absence of the “stay alive” current was controlled by an additional load branch with R5,8 = 23KΩ. At nominal output voltage (2.3 V), it would introduce a

87 Gate Drive Signal

Load Test Vin1

Vout1 Vout2

Vin2

Load Test

Figure 3.31: Photo of the PCB

100 µA “stay alive” current. The current can be removed by disconnecting jumper

J5,8. Power supply ﬁltering capacitor was chosen as 0.1 µF . The photo of the PCB is shown in Fig. 3.31. The board size was 3’ by 5’.

Finally, certain equipment and meters are needed for testing, which include DC tunable power supplies, function generator, and oscilloscope for the least. A portable multimeter and a voltage meter are also helpful in the debugging process. The connection of major test equipment to the chip under test is shown in Fig. 3.32. Notice that the connection is speciﬁc for load transient response measurement, which is usually the key one which measures the LDO loop stability, speed, and transient response all-in-one. Slightly diﬀerent connections (mostly at the load side) are needed for other tests.

88 HPE3620A HP6284 HP54603B oscilloscope Power Supplies

GND

10 Ohm

GND GND HP8116A Function HPE3620A HP6284 Generator Power Supplies

Figure 3.32: Test Equipment and Proper Connection for the Test

Measurements and Discrepancies

The measured load transient response of the conventional LDO [59] is shown in

Fig. 3.33. The input voltage Vin is 3.7 V, and the nominal output is 3.469 V. When

jumper J5 is connected, R5 provides the conventional LDO with approximately 150µA of “stay alive” current A periodic (100 kHz) square waveform (Vlow=1 V, Vhigh= 2 V)

was applied at the gate of Q1. According to the measurement at the test point U10 in

Fig. 3.30 and the resistance value of R10, the load current change ∆Iout is as large as

137 mA. The output voltage dropped from 3.469 V to 3.094 V, with corresponds to a

375 mV drop. No oscillation or settling time is observed, which is in agreement with

the the analysis of this dissertation and [59], as well as the measurements of [59].

The proposed LDO, however, suﬀers from over current (Iin > 1A) in a random

amount of time after system power up. The cause has been identiﬁed as design

89 Figure 3.33: Measured Transient Response of the Fabricated Conventional LDO with ”stay alive” current.

Rbg Rfb IPRB1 VBIAS1

Vias present

Vias missing

Figure 3.34: Layout Error Identiﬁed in the top-level interconnect of the Proposed LDO Core

90 Figure 3.35: Diagnostic Test Bench to Analyze the Measurement-Simulation Discrep- ancies

errors at top level interconnect. As seen in Fig. 3.34, three global interconnects that are supposed to pin out Rfb, Iprb,2, and VBIAS,1 are in fact disconnected because of missing vias from Metal 1 to Metal 2. The disconnection of Rfb and Iprb,2 deprives the opportunity to monitor the attenuation factor f = 1/gmM1 , and the biasing status 1/gmM1+R2 of the second gain stage G2 in Fig. 3.16. The disconnection of VBIAS,1, however, is fatal, because the gate of M10 (in Fig. 3.17) is not deﬁned, leaving the high impedance node of the drain of M10 and M9 unpredictable, which could easily trigger a large amount of current ﬂow in MP T by going below its Vth. The design error could have been avoided if padframe level layout-versus-schematic (LVS) were conducted.

The hypothesis can be further veriﬁed by block level post-layout simulation with the disconnection of VBIAS,1 properly modeled. A diagnostic test bench is shown in

Fig. 3.35. The voltage at the reference pin VBIAS,1 was set as a DC variable ranging from the supply to ground. A DC sweep on the VBIAS,1 from 0 to 2.5 V under 3.5

91 DC Response Nominal Operating Region

0/V0/PLUS<0> /V0/PLUS<1>

Power MOS Current Surge −.250

−. 500

−.750

I (mA) Pre-layout Simulation −1. 0

−1.25

−1. 5 Post-layout Simulation

−1.75 0 .5 1. 0 1. 5 2. 0 2. 5 Vfloat ()

Figure 3.36: Schematic and Post-layout Simulations of the Proposed LDO with Dis- connected VBIAS,1 that Correlate with Measurement Results

V input is shown in Fig. 3.36, where the total battery current (negative in polarity)

is monitored. If VBIAS,1 were properly connected to the external bias, it would be

very close to 2.5 V, approximately one VSG below Vin to properly turn on the power

MOSFET. The battery current would be equal to the load current in the diagnostic

test bench in Fig. 3.35, which is on the order of 100 µA. However, as the simulation in

Fig. 3.36 shows, the battery current increases dramatically as the voltage at VBIAS,1 is reduced, leading to potentially 5X increase in schematic level simulation, even more after post-layout extraction. This qualitatively correlates the 50-50 chance of input current surge observed during silicon measurements.

92 3.5 Summary

In this chapter, linear power management methods are discussed. A linear se-

ries voltage regulator is studied as a proxy, with special focus on PMOS low drop-

out (LDO) topologies because of their high eﬃciency, though NMOS high drop-out

(HDO) designs are also brieﬂy discussed. The design parameters of an LDO are then

studied in details, which can be divided into three categories: DC, AC, and tran-

sient parameters. The technical challenges of improving those parameters are also

presented.

Due to the growing trend of high-level integration and the strict requirement for small footprint in portable devices, external capacitor-free LDOs and their unique design challenges are also studied. A sleep-mode current-area efficient LDO using input current-differencing technique is proposed. The motivation stems from the fact that existing cap-free LDOs either sacrifice sleep-mode efficiency or require large on-chip die area. The proposed design reduces the excessive loop gain, which help addresses the current-area trade-off at sleep mode. The simulation and measurement results are also presented with analysis on the discrepancies between measurement and simulation data.

93 Chapter 4: Switch-Mode DC-DC Converters

Switch mode DC-DC converters are widely used in residential and consumer applications like switch-mode power supply (SMPS) [103] and DC motor drives [104].

Unlike linear regulators, whose eﬃciencies are limited by their dropout voltages, switching regulators enjoys 100% eﬃciency in theory. They make use of fully ON and OFF switches: fully ON switches conduct high current (I) but with zero voltage

(V ) across, while fully OFF switches have high V across the two terminals but with zero I ﬂowing through, keeping the I V product zero at all times. × In high power applications, switch-mode DC-DC converters are often used with an electrical isolation transformer [104]. However, these transformers are bulky and not always necessary for low power applications. On-chip non-isolated switch-mode DC-

DC converters with integrated power MOSFETs and control circuits (except external inductor and capacitor) are of primary interest for green electronics due to the needs for both high eﬃciency and compactness. The topologies involved include buck (step- down), boost (step-up), buck-boost, and so forth.

As discussed in chapter 2, buck converters could reduce the supply current and prolong the battery life signiﬁcantly if they are eﬃcient across a wide load range, especially at light load conditions. In this chapter, the challenges and designs of

94 Efficiency (%)

Light−Load Heavy−Load 90

60 Switching Loss Conduction Loss

50 0 200 400 600 800

I Load (mA)

Figure 4.1: Eﬃciency Curve of a DC-DC converter

light-load eﬃcient buck converters are discussed in details, and a Long-Sleep Model

(LSM) that improves on existing methods and facilitates design re-use is proposed.

4.1 Light-Load Eﬃciency Challenge

It is well known that the eﬃciency of a buck converter depends on the output power [105]. As seen in Fig 4.1, the eﬃciency of a buck converter peaks at moderate load current and declines at both high load current and low load current.

A detailed semi-quantitative analysis can be conducted as follows. The power consumption of a DC-DC converter can be expressed as

Pin = Pout + Psw + Pcond + PQ + PL,C (4.1)

95 Psw, Pcond, PL,C and PQ represent the switching loss, conduction loss, passive component power loss, and the circuit static power loss respectively [43]. Pcond is proportional to Iout, thus as Iout (i.e. Pout, assuming a constant Vout) decreases, Pcond is reduced accordingly. Psw and PQ, however, do not scale accordingly or proportion to

Iout, which causes the power loss to remain ﬂat while the output power is diminished, causing the eﬃciency η = Pout/Pin to drop substantially.

4.2 Conventional Eﬃciency Boosting Techniques

As a result, there are two main approaches to boost the light-load eﬃciency of a

DC-DC converter. This ﬁrst approach focuses on reducing Psw, or making Psw scal-

able to the diminishing load. Within this approach, two sub-approaches can be identi-

ﬁed: reducing switching frequency fs and reducing one-time switching loss Esw (since

P = f E ). Methods of reducing f include variable-frequency operation [106], sw s × sw s where buck converter runs in discontinuous-conduction mode (DCM), hybrid mode

[107], or automatic Mode Hopping (MH) [105], where the converter switches to asyn- chronous DCM during light load, compared to synchronous continuous-conduction mode (CCM) during heavy mode. Latest progress within the sub-approach of reducing fs includes performance enhancement in dynamics and output ripples [108, 109].

1 2 Methods of reducing Esw also include two sub methods. Since Esw = 2 CgateVswing,

either reducing Cgate or Vswing will be reduce Esw eﬀectively. Power FET segmenta-

tion, or optimum MOSFET width control, is a method to reduce Cgate. In this

method, the power transistor is implemented with segments of small transistors con-

nected in parallel. All the segments are activated only at peak load power to achieve

the minimum conduction loss. For a lighter load, only a few segments of transistors

96 are activated, while the others are turned oﬀ to reduce the switching loss [43, 110, 111].

Methods to reduce Vswing include statically [112] and dynamically [113] reducing the gate drive voltage swing, compared to the otherwise rail-to-rail Vswing.

The second approach of improving light load eﬃciency focuses on reducing PQ: the static or quiescent power consumed by the power converter circuits, such as comparator, saw-tooth waveform generator etc. In most applications where I out ≥

10mA, PQ would be minimal compared to other type of power losses. However, as

Iout continues to decrease to a point that it becomes comparable to IQ, then the limit to eﬃciency becomes PQ. [114] used a zero-DC current comparator with digital

PWM/PFM modulation that achieved 70% power eﬃciency at Iout = 100µA.A summary of existing light-load eﬃciency improvement methods and their advantages and disadvantages are listed in Table 4.1.

4.3 Sleep-Wake Eﬃciency Boosting

In face of the growing need for low power green electronics, integrated DC-DC converters that remain highly efficient at miliwatt (mW) or microwatt (µW ) of output power are required [115]. The demand is partially fueled by the potential benefits of highly integrated, miniaturized wireless micro-sensors [116], which enable a variety of applications such as military target tracking, industrial monitoring, environmental control, and remote healthcare[116, 117, 118]. The need is also driven by the need for standby power reduction in mainstream portable applications [46], whose sleep mode power can be reduced into milliwatt or microwatt range [114]. As described in chapter 2, the sleep mode time can be significantly longer than active time, making

97 Technique Advantages Disadvantages

Variable fs [106] Efficiency improvement in- DCM only, output spec- dependent of load trum needs to be random- ized Hybrid mode Flexibility in selecting sync. Trade-off between conduc- [107] and async. rectifier for option loss (Schottky) and timum efficiency switching loss Traditional Flexibility in selecting Performance degrades with mode-hopping CCM/DCM for optimum large output voltage ripple [105] efficiency Improved mode- Constant ripple and fast Trade-off between efficiency hopping [108] transient with good effi- and performance ciency Non-linear Different inductance value Usage of non-standard com- inductor [109] for PFM/PWM ponent: saturable inductor Gate drive scal- Reduces switching loss Limited effectiveness due to ing [113, 112] other power loss factors

IQ reduction Improved light load eﬃ- Diﬃculties in designing low [114] ciency IQ circuitry

Table 4.1: Advantages and disadvantages of existing techniques

the overall efficiency a strong function of sleep mode efficiency. Thus, microwatt efficient integrated DC-DC converters are highly desirable.

At sub-mW or µW loads, PQ becomes the dominant form of power loss [114, 115], and the conventional light-load eﬃciency boosting techniques alone are no longer eﬀective. A common method of reducing PQ is “burst mode” operation [119, 120, 121].

It is a sleep-wake type of operation in which a series of inductor current pulses are

applied to the output capacitor and load [121]. The power converter delivers energy

to the the output until it is regulated and then goes into idle or sleep. As long as the

98 output voltage is within preset boundaries, the converter consumes ideally zero (in

reality in the orders of µA [122]) quiescent power.

“Burst” mode, or sleep-wake operation 6not only make use of conventional ef-

ﬁciency boosting methods by eﬀectively lowering the frequency of the switching fs,

thereby lowering the Esw, but also reduces the overall equivalent quiescent current IQ.

Notice that there is a limit in conventional methods of reducing the quiescent current

IQ of key analog and biasing circuits without signiﬁcant performance penalties. In

sleep-wake operation, assuming that the wake time (“burst”) and the sleep time (no

“burst”) are Twake and Tsleep respectively, the equivalent quiescent current IQ,eff can

be found as:

Twake IQ,eff = IQ,wake (4.2) · Twake + Tsleep

From Eq. 4.2, the longer Tsleep is compared to Twake, the lower IQ,eff can be.

Recently, an improvement to the sleep-wake operation has been proposed [123]. It was based on the observation that a non-sleep-wake conventional DC-DC converter operates continuously, which means that the apparent output power of the converter,

Pout, is always equal to the required load power, Pload in the steady state. A sleep- wake DC-DC converter, on the other hand, breaks the connection between Pout and

Pload. The apparent output power of the converter Pout can be set to be an arbitrary value (larger than Pload), and the power delivered to the load on average would still be

Pload, as long as the proper sleep-wake ratio is chosen, and some appropriate energy storage elements are present as energy buﬀers.

6In this dissertation, the term sleep-wake operation will be used interchangeably with “burst mode” operation, evev though the later is sometimes used exclusively to refer to certain patented implementations.

99 Efficiency

100%

ηmax

PLL POPT PHL

Output Power

Figure 4.2: A general illustration of the optimum output power point Popt at which a DC-DC converter achieves maximum eﬃciency ηmax

The free choice of apparent output power Pout, has a significant benefit in efficiency.

Notice that every DC-DC converter reaches its intrinsic maximum power eﬃciency

(ηmax) at a speciﬁc output power level, Popt, as seen in Fig 4.2. In the improved sleep-wake operation [123], the wake-time apparent output power Pout can be chosen to be Popt, achieving the maximum eﬃciency available ηmax. The sleep-time apparent output power Pout should be strictly zero, eliminating any power loss.

With the fore mentioned principle of power matching, The efficiency benefit of the sleep-wake operation is obvious. If we define the sleep-wake duty ratio D as twake/(twake + tsleep), for a a conventional non-sleep-wake converter, the sleep-wake

duty and achievable eﬃciency are

100 P D = load 1 (4.3) Pout ≡ Pout Pload η = = ηmax (4.4) Pin Pin ≤

Sleep-wake operation, on the other hand, allows

Pload Dopt = < 1 (4.5) Popt Pout Popt ηopt = = = ηmax (4.6) Pin Pin

where Dopt is the corresponding optimum sleep-wake ratio as a result of the prin-

ciple of power matching.

Another major advantage of the method in [123] over previous solutions [107, 124,

105, 111] is that it allows the reuse of existing heavy-load eﬃcient DC-DC converters

for light load operations, avoiding the circuit re-design and optimization for each new

load condition. This is because existing power converter IPs for portable electronics

are usually optimized for normal mode, where η η , making the whole existingIP ≈ max converter design directly re-usable for light-load with only some added sleep-wake control.

A key limitation of [123], however, is the power loss associated with charging and discharging the energy storage elements. Fig. 4.3 shows the conceptual block diagram of a sleep-wake DC-DC converter with an energy storage element, which absorbs the excess power P P during wake time and discharge itself to provide for P out − load load

during sleep time. The charge (Pchg) and discharge (Pdis) power of the energy storage

element can be found as

101 Pin Pout Pload Power Load Converter

Pchg Pdis

Energy−storage Element

Figure 4.3: Block diagram of a Sleep-Wake DC-DC Converter with an Energy Storage Element

P = P P (4.7) chg out − load

Pdis = Pload (4.8)

Assume that the charge and discharge eﬃciencies are ηc and ηd respectively, based on the conservation of power

η η P t = P t (4.9) c · d · chg × wake dis × sleep Thus, the wake-sleep duty ratio and the overall eﬃciency with charging and discharging loss included can be calculated as

1 D = (4.10) (1 η )+ η (P /P ) − ES ES out load P (t + t ) P P 1 η = load × wake sleep = load out Pin twake Pout · Pin · D ×η = η ES (4.11) wake 1 D(1 η ) − − ES 102 where η = η η is the combined eﬃciency of the energy storage element. In ES c · d

the ideal case of ηES = 1, equation 4.10 and 4.11 become 4.5 and 4.6.

Another drawback of [123]’s method is the fact that Popt is not known a priori: it depends on the design parameters and the physical implementation of the DC-DC converter. In other words, ηmax and Popt can only be determined or measured after the converter is designed and implemented, and their values may depend heavily on the components and topologies chosen. As a result, the sleep-wake ratio D is often picked according to experience [123] instead of the design equation of 4.10.

4.4 The Long-Sleep Model

The improved sleep-wake method with the principle of power matching [123] is particularly suitable for emerging multiple power mode electronics with emphasis on sleep-mode eﬃciency. The low cost nature of certain products even prohibits fully- customized design for each additional power saving mode, but the design and power consumption for normal mode is well deﬁned.

If an existing IP of a converter is optimized for the active mode, then Pload,active should be very close to Popt already. In order to provide for a much lighter Pload,sleep, the wake-time output apparent power Pout,wake should be set to Pload,active, and the resulting sleep-wake duty cycle D will be determined by the ratio of Pload,active and

Pload,sleep. In this way, D should be very close to Dopt, and the intrinsic maximum

7 eﬃciency ηmax could still be achieved.

Due to the huge diﬀerence between Pload,active and Pload,sleep in many applications

(For example, the supply current of a coin-cell-powered wireless sensor can vary from

7 To be more precise, only ηactive is achieved. But ηactive should be very close to, if not identical to ηmax, assuming perfect design and optimization for the active mode application.

103 tens of mA during radio transmission (TX) and reception (RX) to a few µA in sleep

[117, 51]), the sleep time could be signiﬁcantly longer than the wake time, leading to a Long-Sleep Model (LSM) with certain unique characteristics [125], which will be described in this section.

4.4.1 Deﬁnition

The Long-Sleep Model (LSM) describes a sleep-wake DC-DC converter with sig- niﬁcantly longer sleep time than wake time. In this dissertation, signiﬁcantly long refers to a ratio of or more than three orders of magnitudes 8.

t sleep 103 (4.12) twake ≥

−3 If we further deﬁne T = tsleep +twake as the sleep-wake period, then D < 10 and

t T,t = DT . sleep ≈ wake

4.4.2 Implication: Large-I0 Approximation

An important implication of LSM is the Large-I0 approximation. Let I0 be the

peak inductor current during T . Since T T , I is much bigger than I . wake sleep ≪ wake 0 load

More speciﬁcally, Large-I0 approximation states that

I I s.t. I = 0 during T (4.13) 0 ≫ out out wake

The importance of Large-I0 approximation manifests itself when applying KCL

at the node X in a typical buck converter as seen in Fig 4.4.

8The choice of 103 within the deﬁnition 4.12 is relatively arbitrary. A less pronounced diﬀerence in twake and tsleep could make some of the conclusions in this chapter less accurate. Ultimately, it is at the discretion of the green electronics designer to decide whether an LSM-approximated analysis and results are accurate enough for their applications.

104 iL Vin ON X Vout

+ i I − OFF C out

Figure 4.4: Large-I0 approximation in typical Buck converter

i = i + I i (4.14) L C out ≈ C If we integrated both sides of Equation 4.14 over one inductor current period, we have

∆QL =∆QC (4.15)

which reveals the underlying principle of charger conservation for large-I0 approxi-

mation: any electric charge delivered through the inductor L , which ultimately came

from the battery, is stored in the capacitor C, as Iout is too small compared to IL during the wake-up moment.

4.4.3 Characteristics Inductor Current

The ﬁrst implication of a much longer sleep is the “pulsiﬁcation” of inductor current (Fig. 4.5). Throughout the sleep time, there is no power delivered to the output. Thus, the inductor current IL is zero. The time when the inductor current

is not zero (such as during twake) is so short that they look like pulses.

105 T

Vout

0 mA t

CCM ramp ramp I L up down steady−state Type I

IL CCM/DCM Type II

IL DCM Type III

t wake

Figure 4.5: Long-Sleep Model waveforms and inductor current proﬁles

Within the “pulsiﬁed” twake, there are still three possible IL scenarios denoted as

Type I, II, and III, as seen in Fig. 4.5. In the Type I scenario, the buck converter operates in a manner similar to continuous conduction mode (CCM), except for the initial ramp-up and ﬁnal ramp-down phases. The converter can also operates on the boundary between continuous conduction mode (CCM) and discontinuous conduction mode (DCM) (Type II) or in DCM completely (Type III).

106 IL Pout2 Pout1 t

D1 (a) D2 > D1

"D=1" Pout2 IL,avg2 IL Pout1 IL,avg1

D= D0 t

D= D0 (b)

Figure 4.6: Load Regulation of a conventional DC-DC vs a sleep-wake DC-DC

The principle of power matching ultimately decides which type is optimum. The

principle of power matching states that Pout = Popt during twake. Since a generic

DC-DC converter is more likely to achieves its best eﬃciency in CCM or CCM/DCM boundary than in DCM, the Type III IL is usually sub optimum.

Load Regulation

In applications where the input and output voltages of the DC-DC converter are

constant, the sleep-wake duty cycle D is an indicator of the output power level and the

counterpart of the average inductor IL,avg of a conventional CCM DC-DC converter.

Therefore, the two topologies respond to a load transient diﬀerently.

When there is a load increase from Iload1 to Iload2 (where Vout is constant), D1 needs to be adjusted to a new value D2, meaning the converter needs to wake up more often

107 (as depicted in Fig. 4.6 (a)), but the duty cycle D during twake may or may not be changed. In a conventional DC-DC converter, however, the average inductor current

IL,avg1 will increase to IL,avg2, which is achieved by a temporary transient (simpliﬁed

′′ as “D = 1 in Fig. 4.6 (b)). The duty cycle D = D0 remains the same before and

after the new steady-state is established.

Output Ripple

Till this point, only the sleep-wake duty cycle D and apparent output power during

twake has been speciﬁed. The sleep period T = tsleep + twake has not been chosen, and

in some applications it can be set to be within a relatively wide frequency range [123].

However, it is important to notice that a group of performance parameters, such as

the output ripples, minimum recovery time, oﬀ-chip component size, and achievable

eﬃciency in practice are all related to T .

The output ripple of a DC-DC converter can be expressed as

∆Vout =∆VC +∆VR (4.16)

where ∆VC and ∆VR refers to the ripple components caused by the capacitor and

its ESR respectively. In a sleep-wake DC-DC converter, the energy storage element

C would discharge itself to provide for the output current during tsleep. Therefore,

∆V I = C C (4.17) load,sleep · T I T ∴ ∆V = load,sleep · (4.18) C C

The shorter the sleep-wake period, the smaller the ripple. From an eﬃciency

perspective, it is desirable to have longer T to reduce the switching and its associated

108 power loss, but it also increases ∆VC . A closer study would show that a longer T

would also increase ∆V ,as∆V I R (according to the Large-I approximation: R R ≈ 0 ESR 0 i i during t ). As T increases, ∆Q = C∆V increases, whereas L ≈ C wake C C

t 2 wake 2∆QL 2∆QC I0 = iL(t) dt = = (4.19) twake Z0 twake twake

Thus, ∆VR would also increase as a result. In green electronics design, the proper sleep-wake period T can be chosen based on the ripple requirements and external

component size limit.

4.4.4 Novelty

The LSM model proposed in the dissertation is similar in many ways to the con-

ventional [119, 120, 121] and improved “burst mode”, or sleep-wake operation [123].

All three methods switch on and oﬀ the DC-DC converter periodically, leading to

the alternation between sleep and wake phases, which eﬀectively reduces fs and PQ.

Conventional burst-mode “burst” are designed for easy implementation. A common

implementation is peak IL current-mode control [121]. The high-side PMOS would

be on until IL reaches the maximum current limit. Then the PMOS is turned oﬀ

and the low-side NMOS is turned on until IL reaches zero. The output voltage is

monitoring using a hysteretic comparator determining whether any more “burst”s

are needed. The improved method [123] proposed the principle of power matching,

but it did not specify how to determine Popt. This dissertation singled out a sub-class

of integrated DC-DC converters with multiple power modes and stringent sleep mode

eﬃcient requirements. LSM proposes using their active mode speciﬁcations as Popt,

and each sleep mode be optimized using the appropriate sleep-wake ratio that satisﬁes

109 Active Mode Sleep Mode

Vin 3 V 3 V

Vout 1.8 V 1 V

Iout 27 mA 5 µ A

Pout 50 mW 50 µ W

Table 4.2: Design speciﬁcations for the Buck Converter

the power matching principle. In this way, the maximum heavy load eﬃciency can also be achieved at light loads, and the same power chain design can be re-used.

4.5 LSM Buck Converter Design Example

In this section, a design example of a dual power mode DC-DC buck converter using LSM is presented. The buck converter is designed for a battery-powered microsystem similar to that of Fig. 1.4. In order to be cost effective, the buck converter will be fully integrated with the rest of the system in a mainstream digital CMOS technology, except for an external capacitor (C) and inductor (L). To realize multi- year operation without battery replacement, the buck converter will have to be highly efficient in all power modes. For simplicity, this example assumes two power modes only. Table 4.2 lists the resulting specifications for the buck converter.

4.5.1 System Design Considerations

Fig. 4.7 shows the system block diagram of the DC-DC converter. The power train, which includes the power MOSFETs, gate driving buﬀers, external inductor (L) and capacitor (C) will be optimized for active mode Pout,active such that

110 Von

Vop Vop

VREF Von

CLK Vin

P−pattern Logic V and out

Control R1 N−pattern

Pseudo−Hysteretic Control Power Train OOK

Figure 4.7: System Block Diagram of the DC-DC Converter

Popt = Pout,active and ηactive = ηmax. The control loop, which includes the clocked

comparator, transmission gate, and synchronization logic will be designed to obtain

the appropriate sleep-wake duty ratio D of Pload,sleep such that η = η . Pload,active sleep max

4.5.2 Power Train Design

The power MOSFETs of the converters have to be sized appropriately to accom- modate the maximum power rating and and optimize the eﬃciency. The on-resistance of the power MOSFETs RDS(ON) in linear region can be reduced by increasing their aspect ratios W/L.

1 R = (4.20) DS(ON) µ C W (V V ) p(n) ox L GS − TH

On the other hand, large size MOSFETs have larger gate-source capacitance Cgs, which requires more gate driving power. Since C W L, the minimum channel gs ∝ · length in the technology L = 0.6µm was chosen to minimize Cgs while achieving the

111 same low RDS(ON) values. In this design, a width of 9000 µm was chosen for the

NMOS to achieve a RDS(ON) of 440 mΩ with Cgs around 7 pF and Cgd of 6 pF.

(Notice that the device is mostly in linear region.) A width of 60000 µm was chosen for the PMOS to achieve an RDS(ON) of 180 mΩ with Cgs and Cgd around 55 pF and 54 pF respectively. Tapered CMOS inverters chains are added as gate drivers for both the PMOS and NMOS power transistors. A tapering ratio of 10 is chosen as a compromise of speed and gate drive power [126].

4.5.3 Control Loop Design Hysteretic Control

There are a number of ways of designing the DC-DC control loop such that the output voltage is stable against load variation. Voltage mode control (VMC) is easy to implement but diﬃcult to stablize or achieve a fast loop response [127, 128]. Current mode control (CMC) provides simpler loop compensation and fast load regulation, but it requires accurate load current sensing and current feedback loop, which increases the converter complexity and power consumption [129, 130].

Hysteretic control (HC) is simple and inherently stable, i.e., it does not require loop compensation. It also responds to load variation quickly, and it is eﬃcient for light-load operations [131, 132]. The draw back of hysteretic control is that its relative large output ripples and variable switching frequency, which complicates Radio

Frequency Interference (RFI) and Electromagnetic Interference (EMI) design.

The characteristics mentioned above make hysteretic control uniquely suitable for sleep-wake operation, though certain modiﬁcations are necessary. Output ripple is not as critical in sleep modes, as key analog and mixed-signal blocks are oﬀ, and the circuits that remain on enjoy much more relaxed performance requirements in supply

112 variation, RFI, and EMI. Variable switching frequency, however, remains an issue, as

timing accuracy in sleep mode is greatly reduced compared to active mode.

Hence, a clocked hysteretic control (CHC) is proposed. Instead of using the a

hysteretic comparator, whose output directly controls the on and oﬀ of the power

MOSFETs, a clocked comparator is used to periodically sample the output voltage,

Vout. If Vout falls below a certain level Vref , the comparator signals a “wake” for the

DC-DC converter. The converter power train will then operate in a open-loop fashion

for a brief twake, during which the power MOSFETs are switched on and oﬀ according

to a pre-determined pattern and a ﬁxed Pout is delivered to the output, before going

back to sleep. If Vout is above Vref , the comparator sends a “sleep” signal. The

DC-DC converter will then remain in sleep until the next sampling period.

9 As such, an equivalent hysteretic voltage window ∆Vout is created, the magnitude

of which is related to the sampling clock period twake and Pout. According to the large-

I approximation of the LSM, I I . Therefore 0 out ≈ C

IC twake Pouttwake ∆Vout = · (4.21) C ≈ VoutC Clocked comparison also allows for better synchronization with other system ac- tivities. In addition, using ﬁxed pattern instead of the hysteretic comparator’s output to switch on and oﬀ the power MOSFETs avoids variable switching frequency and

RFI/EMI problems.

Clocked Comparator

The clocked comparator is the key block that implements the proposed CHC control. To reduce the power loss overhead introduced by the circuit, a zero-DC

9Diﬀerent from the output ripple described in section 4.4.3.

113 VDD

Vop clk clk

Von

Vinp Vinn

clk

Clocked comparator

Figure 4.8: Schematic of the clocked comparator

current comparator [114] is adopted, as seen in Fig 4.8. Notice that the comparator

in Fig 4.8. is a level sensitive latch. To ensure that the hysteretic window is created

properly, and that the DC-DC converter operates in a pseudo open-loop fashion

during twake, a CMOS transmission gate is added in the feedback loop, as seen in the block diagram in Fig., eﬀectively makes the comparator an edge sensitive latch.

Gate Drive Patterns and Logic

The pre-determined gate drive patterns during twake are designed to match the operation at Popt. As explained in Section 4.4.3, a Type-I scenario, which is CCM operation during twake is most likely. In this example, a duty cycle operation proﬁle was selected as one possible design whose Popt coincides with Pload,active. Its synchronous rectiﬁcation and optimum deadtime control are all embedded into the gate

114 drive pattern. Once designed, the patterns can be stored in system ROM, RAM, or

registers for easy access.

The remaining logic circuits in Fig. 4.7 controls the sleep-wake transition. The output of the clocked comparator enables or disables the gate drive pattern through

CMOS NOR gates, which eﬀectively turns the power train on and oﬀ for wake and sleep.

4.6 Simulation Results

The LSM buck converter design example was implemented in MOSIS 0.5 µm

digital CMOS technology. The test benches in normal and sleep modes are shown

in Fig 4.9. Open-loop simulation was performed to mimic normal mode operation

and guide the power train design to have its Popt matched with Pload,active. Close-loop simulation was performed in sleep mode to check the load regulation and eﬃciency.

External stimuli include the voltage reference, wake-up clock, pre-determined NMOS and PMOS gate drive signal patterns.

The open-loop simulation of the optimized power train was shown in Fig 4.10 and

4.11. The loop dynamic is shown in Fig. 4.10, where Vout starts from an initial voltage and settles to a pre-determined ﬁnal value of 1 V (1.03 V in simulation) within 50 µs.

Since it is an open-loop simulation, Vout is not regulated against output load, but it will change will different duty cycles reflected in different gate driving patterns. The detailed inductor current IL waveform is shown in Fig. 4.11, where it can be seen that the optimized power train operates on the CCM-DCM boundary with peak IL of

100 mA and switching frequency of 1.37 MHz. The eﬃciency ηmax, which is the ratio

115 V in

P−pattern

Vout

R out =20 N−pattern

Chip under test: Normal Mode

Vin

Von

Vop Vop

VREF Von

CLK

V out P−pattern Logic and Control N−pattern

R1 = R2 Chip under test: = 200K Sleep Mode

Figure 4.9: Test benches for the DC-DC converter in Normal Mode and Sleep Mode

of the power delivered to Rout in Fig. 4.9 over the power drained from the battery

Vin, is measured to be 89%.

Fig. 4.12 shows the close-loop sleep-wake operation of the buck converter. The top trace in Fig. 4.12 is the sleep timer available in the system. Depending on the

116 Transient Response

3.5 /ndrive 3.0 2. 5 2. 0 1. 5

V (V) N-drive pattern 1. 0 .5 0 −. 5 3.5 /pdrive 3.0 2. 5 2. 0 1. 5 P-drive pattern V (V) 1. 0 .5 0 −. 5 1 7 5 /L/PLUS Inductor Current (IL): 25 mA/div I (mA)

−50 .0 1.1 3 /vout 1.1 1. 08 Output Voltage (Vout): 25 mV/div 1. 05 1. 03 V (V) 1. 0 .975 .95 .925 0 25.0 50 .0 75.0 1 0 0 1 2 5 1 5 0 time (us )

Figure 4.10: Open-loop Dynamic of the Optimized Power Train

Transient Response

/L/PLUS 1 5 0 Inductor Current (IL): 50 mA/div 1 0 0

50 .0 I (mA)

1.1 3 /vout 1.1 1. 08 Output Voltage (Vout): 30 mV/div 1. 05

1. 03 V (V) 1. 0

.975 .95

.925 5 6 Iload 5 5 5 4 5 3 Time: 2.5 us/div Load Current (Iout): 1 mA/div 5 2 5 1 I (mA) 5 0 4 9 4 8 4 7 85 .0 87. 5 90 .0 92. 5 time (us )

Figure 4.11: Inductor Current IL during Heavy Mode Operation

117 Transient Response

3.5 /sleep_b

1. 5 Sleep Timer V (V)

−. 5 1 2 5 /L/PLUS 1 0 0 75.0 50 .0 Inductor Current (IL): 25 mA/div

I (mA) 25.0 0 −2 5.0 1. 08 /vout 1. 05 1. 03 Output Voltage (Vout): 25 mV/div

V (V) 1. 0 .975 .95 3.5 /compp

1. 5 CHC comparator output (P) V (V)

−. 5 3.5 /compn

1. 5 CHC comparator output (N) V (V)

−. 5 0 25.0 50 .0 75.0 1 0 0 time (ms)

Figure 4.12: Close-loop Sleep-wake Operation of the Buck Converter

Transient Response

1 2 5 /L/PLUS 1 0 0 Inductor Current (IL): 75.0 50 mA/div 50 .0 I (mA) 25.0

1. 08 /vout 1. 05 1. 03 1. 0 Output Voltage (Vout):

V (V) .975 25 mV/div .95 .925 .9 1 1 Iload 1 0 Load Current (Iout): 9.0 Time: 2.5 us/div 8.0 1 uA/div 7. 0

I_load6 (uA) .0 5.0 4. 0 49.998 50 .0 50 .003 50 .005 time (ms )

Figure 4.13: Inductor Current IL during twake

118 Figure 4.14: Load regulation in Sleep Mode

actual load, the DC-DC converter wakes up every several clock cycle. The inductor

current was “pulsiﬁed” as expected from analysis in Section 4.4.3, indicating the

appropriateness for various LSM approximations. (Eq. 4.12). During twake, the inductor current matches that of Fig. 4.11, as illustrated in Fig. 4.13, which means the apparent output power during twake has been matched to Popt for maximum

eﬃciency.

The transient load regulation of the buck converter was shown in Fig 4.14. An

abrupt, 100% load increase from 5µA to 10µA was simulated by a switching on a

R2 = 200K in parallel with R1 as seen in Fig 4.9. The converter output voltage

experienced a temporary dip, and the power train waked up more frequently, i.e. on

every wake-up clock cycle. Consequently, Vout recovers within ﬁve sampling cycles

119 Figure 4.15: Simulated Eﬃciency of the Proposed Converter

(Ts), or 50 ms. The signiﬁcance of achieving good load regulation in sleep mode is to prevent power rail runaway in case of leakage and oﬀ-current variations, which also help reduce the system wake-up time from sleep to normal mode.

The simulated eﬃciency of the DC-DC converter is shown in Fig. 4.15. The layout of the example is shown in Fig. 4.16. The power MOSFETs, gate drivers,

CHC comparator and logics are marked.

4.7 Summary

This chapter discusses the design of one type of non-linear power management

ICs: non-isolated switch-mode DC-DC converters. The focus is on their light-load eﬃciency improvement, as system level power management has already demonstrated its importance (Chapter 2). The power loss mechanism of a DC-DC converter is ﬁrst studied, revealing two major types of power losses: the conduction loss that scales with output power, and the other losses (switching loss and quiescent power loss) that

120 Figure 4.16: The Chip Layout of the Proposed Converter

do not scale as well. Major approaches to make them more scalable are discussed, including conventional frequency and gate drive scaling and sleep-wake “burst”-mode operations.

At very light loads at milliwatt or microwatt levels, which are typical for the sleep mode power consumptions of multi-year battery-powered devices, the improved sleep-wake operation with power matching is very attractive. A novel long-sleep model (LSM) was introduced based on this method. It assumes that for any multiple power mode DC-DC converter, the eﬃciency at the active mode is already optimized.

Any additional sleep mode can be optimized accordingly such that the sleep-mode eﬃciency is equal to the active mode eﬃciency.

121 LSM resolves the uncertainty, i.e. the optimum efficiency is not known a priori, in the applying the principle of power matching in prior arts for a whole class of multiple power mode electronics. The method also enables direct silicon IP reuse of the DC-DC converter power train from active mode to sleep mode, which will effectively reduce the design time and shorten the product development cycle, as long as proper energy storage elements are available, and that their charge and discharge loss are minimum. Finally, a design example of a dual power mode, microwatt sleep mode DC-DC Buck converter is provided featuring clocked hysteretic control. The simulated waveforms and efficiencies are also presented.

122 Chapter 5: Conclusion

This dissertation discusses the concept, design, and implementations of green electronics, a new class of energy-eﬃcient portable and battery-powered electronic systems, which are not only essential to satisfy current consumers’ needs for longer battery life and ultra compactness, but also instrumental to assist future renewable- energy generation and delivery.

The dissertation approaches the topic in a top-down fashion. The concept of green electronics is introduced against the backdrop of the world’s energy and environment grand challenges and the consumer electronic industry’s power efficiency and battery life crisis. Power management, an informed and intelligent effort to cur- tail and reduce power consumption, is then introduced through a holistic solution involving multiple levels of abstractions. Transistor-level power management IC designs, including capacitor-free low drop-out regulators and light-load efficient DC-DC converters, are discussed in details, following the logical sequence of explaining the performance requirements to reveal the technical challenges, analyzing the existing methods to understand their respective advantages and drawbacks, and proposing new solutions to better address the trade-offs.

The dissertation is also characterized by a common theme: high eﬃciency and full on-chip integration, both of which stems from the unique requirements for portable

123 and battery-powered applications. Under this theme, the key innovation is the shift

of focus from conventional, active-mode eﬃciency to sleep-mode eﬃciency, as in-

creasing number of portable battery-powered device spend more time in idle than in

active usage. Hence, during the discussions of proposed input-current diﬀerencing

capacitor-free LDOs and long-sleep model DC-DC converters, sleep-mode eﬃciency

improvement has been the driving motivation.

Finally, the dissertation does not seek to establish the solution to the grand challenges mentioned, but rather to serve as a promising starting point that invites more scholarly research and industrial development to the same topic. Future research directions of green electronic IC design may include the eﬃcient interface IC design to energy-harvesting devices, which have demonstrated capabilities to scavenge ambient thermal, kinetic, and electromagnetic energy at sub-mW levels to partially or fully power certain low-power electronics. Another promising angle would be inves- tigating the power conditioning needs at the output of renewable energy generators, such as the output of mini-wind turbines and low-voltage solar cells, and design the appropriate green electronics silicon IPs or SoCs to address those needs.

In conclusion, it is the author’s humble hope that green electronics will attract integrated circuit designers to apply their expertise to address the world’s energy and environmental problems. It is also his belief that the same IC/VLSI design techniques invented in the process can be easily applied to designing more energy- eﬃcient consumer electronic products, creating signiﬁcant business value as well as advancing the state-of-the-art of power management IC design.

124 Appendix A: Test Plan for the Dual-Core LDO

Test plan is the often the ﬁrst step in test solution development [97]. Industrial tests can be categorized as engineering evaluation, characterization, and production tests. Often a tentative data sheet is available before the test solution development.

For research, the requirement and procedure of testing is less stringent. But the draft of a test plan before silicon evaluation is still important, as it guides the test board development and component selection. Once the PCB has been designed, proper soldering techniques are needed to solder the components onto the board and necessary equipment should be identiﬁed before the measurements. A number of helpful documents on these topics can be found here [133, 134].

Below is a sample test plan for the dual-core LDO designed in Chapter 3.

A.1 LDO 2: Conventional Topology

1. DC Biasing.

The following input signals will be fed to the LDO (Table A.1), and the output

of these pins will be carefully observed (Table A.2).

2. Functionality.

125 Value Equipment Note AVDD2 2.5 V Power Supply # 1 AVSS2 0 V GND Star Connection VBG2 1 V Power Supply # 2 VBIAS2 1.35 V Power Supply # 3 Tune the bias current of the input pair to 40 µA (20 µA per branch).

Table A.1: Input Stimuli

Expected Equipment Note IPRB2 20 µA # 1: Keithley source meter. Source a 2.5 V, measure the current (preferred) # 2: Use a 75 kΩ pull-up resistance. Start from high VBIAS2 voltage till voltage at IPRB2 is lowered to 1 V. VOUT2 2.3 V Oscilloscope

Table A.2: Output Pins

DC line regulation needs to be veriﬁed. Change AVDD2 from 2.5 to 5 V. Observe

that VOUT2 stays stable at 2.3 V.

DC load regulation needs to be veriﬁed. Change load resistance from 23 kOhm

to 23 Ohm. Observe that VOUT2 stays stable at 2.3 V.

3. On-chip Load Transient (Available on probe stations).

126 Feed a periodic square wave to drive the on-chip load (EXGATE2). Connect a 23

kΩ as the “stay-alive” load. Monitor the waveform at VOUT2. It should show

stable but with over shots and under shots.

Feed a periodic square wave to drive the on-chip load (EXGATE2). Disconnect

the 23 kΩ as the “stay-alive” load. Monitor the waveform at VOUT2. It should

show oscillation. The current needs to be derived from VOUT2 and ROUT2.

4. Oﬀ-chip Load Transient.

Same as on-chip load test except that jumpers have to be placed at the right

location.

5. Line Transient Response

Disconnect the AVDD2 ﬁlter capacitance. Use a square wave to drive AVDD2,

observe the response of VOUT2.

6. PSRR (optional)

Use manual adjustment (1k to 1M, 1pt per decade). Feed a clean power supply

(2.5+0.5=3 V) with AC 500 mV peak-to-peak. Measure the output ripple.

7. Output Noise (optional)

Use the RF noise source to feed VBG2 (1V). Measure the output noise at VOUT2.

8. Startup (optional)

Ramp up the AVDD2, view the response of VOUT2.

127 A.2 LDO 1: Proposed Topology

The test plan for the proposed topology is very similar to that of the conventional one. The diﬀerences are listed below.

1. Diﬀerence in DC Biasing

The following input signals will be fed to the LDO (Table A.3), and the output

of these pins will be carefully observed (Table A.4).

Value Equipment Note AVDD1 2.5 V Power Supply # 1 AVSS2 0 V GND Star Connection VBG2 2.3 V Power Supply # 2 Whatever value set will be VOUT VBIAS2 1.45 V Power Supply # 3 Tune the bias current of the gain stage to 20-25 µA per limb.

Table A.3: Diﬀerence in Input Stimuli for the Proposed Topology

2. Diﬀerence on oﬀ-chip options.

Pin Rbg and Rfb can also be used as forced-inputs. Connect a variable resistance

R’ between VOUT1 and Rfb. The on-chip R2 (100k) will be put in parallel with

R’. By knowing R’ precisely, the voltage across it, as well as the exact R2 value

can be derived for each chip.

Similarly, we can connect a variable resistor R’’, which is identical to R’, from

Power Supply #2 to Rbg. Disconnect Power Supply #2 to pin VBG1. The

128 Expected Equipment Note IPRB2 20 µA # 1: Use a 75 kΩ pull-up resistance. Start from high VBIAS1 voltage till voltage at IPRB1 is lowered to 1 V. # 2: Use an ampere meter connected between IPRB1 and AVDD1 to read the current VOUT2 2.3 V Oscilloscope Rbg 1.0-1.1 V Multimeter or oscillo- Input reference divider: mid scope point Rfb 1.0-1.1 V Multimeter or oscillo- Feedback voltage: mid scope point

Table A.4: Diﬀerences in Output Waveforms to be Observed

on-chip R1 (100k) will then be by-passed completely. To balance the input, R’’

will need to be tuned smaller than R’ such that it matches R’ R2(100k) value. k

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