Article A Two-Module with 3.9–10 V Input, 2.5 V Output, and 500 mA Load

Quanzhen Duan 1, Weidong Li 1, Shengming Huang 1,*, Yuemin Ding 2,*, Zhen Meng 3 and Kai Shi 2

1 School of Electrical and Electronic Engineering and Tianjin Key Laboratory of Film Electronic and Communication Devices, Tianjin University of Technology, Tianjin 300384, China; [email protected] (Q.D.); [email protected] (W.L.) 2 School of Computer and Science Engineering, Tianjin University of Technology, Tianjin 300384, China; [email protected] 3 Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China; [email protected] * Correspondence: [email protected] (S.H.); [email protected] (Y.D.)

 Received: 7 September 2019; Accepted: 4 October 2019; Published: 10 October 2019 

Abstract: A linear regulator with an input range of 3.9–10 V, 2.5 V output, and a maximal 500 mA load for use with battery systems was developed and presented here. The linear regulator featured two modules of a preregulator and a linear regulator core circuit, offering minimized power dissipation and high-level stability. The preregulator delivered an internal power of 3 V and supplied internal circuits including the second module (the linear regulator core). The preregulator fitted with an active, low-pass filter provided a low-noise reference voltage to the linear regulator core circuit. To ensure operational stability for the linear regulator, error amplifiers incorporating the Miller compensation technique and featuring a large slewing rate were employed in the two modules. The circuit was successfully implemented in a 0.25 µm, 5 V complementary metal-oxide semiconductor (CMOS) process featuring 20 V drain-extended MOS (DMOS)/bipolar high-voltage devices. The total silicon area, including all pads, was approximately 1.67 mm2. To reduce chip area, bipolar rather than DMOS served as the power transistors. Measured results demonstrated that the designed linear regulator was able to operate at an input voltage ranging from 3.9 to 10 V and offer a maximum 500 mA load current with fixed 2.5 V output voltage.

Keywords: linear regulator; low noise; wide input range; high voltage (HV); high stability; large current load; bandgap; protection circuits

1. Introduction Today, high-voltage (HV) battery-powered systems with wide input ranges play major roles in energy storage for portable/palm notebook computers, battery chargers, wireless communication equipment, and so on [1,2]. To ensure safety, long life, and reliable operation of lithium ion batteries, an (IC) is generally required to manage their charging and discharging process. An IC must feature a power management circuit converting a high input voltage to a stable low voltage that supplies other IC circuits. A power management circuit featuring a cascaded DC–DC converter and low-dropout regulator (LDO) with a high system power efficiency is typically termed as a ; however, a DC–DC converter may create large voltage ripples and, thus, reduce output voltage accuracy [3,4]. Also, the design complexity of a DC–DC converter is much higher than that of a linear regulator. The use of a linear regulator for power management affords design simplicity, less silicon area, low cost, and no [5–12].

Electronics 2019, 8, 1143; doi:10.3390/electronics8101143 www.mdpi.com/journal/electronics Electronics 20192019,, 88,, 1143x FOR PEER REVIEW 22 of of 14

Consequently, an HV linear regulator for power management implemented by an HV-LDO aloneConsequently,, even with a anlower HV power linear regulatorefficiency for, becomes power managementattractive for implemented constructing bypower an HV-LDO management alone, evencircuits with used a lower in high power-accuracy efficiency, output becomes battery attractive-powered for systems. constructing Generally, power HV management-LDO composed circuits of usedhigh- involtage high-accuracy DMOS or output bipolar battery-powered transistors (BJTs) systems. only Generally,has a significantly HV-LDO high composed power of consumption high-voltage DMOSand large or bipolar silicon transistors area [13–15]. (BJTs) Additionally, only has a significantly the linear regulator high power applied consumption in HV battery and large-powered silicon areasystems [13– 15must]. Additionally, be capable of the bearing linear regulatora high current applied load in HVin a battery-powered wide input voltage systems range. must Although be capable the ofHV bearing-LDOs presented a high current in [13 load–15] are in aable wide to inputoperate voltage in a wide range. input Although voltage range, the HV-LDOs they cannot presented afford ina high [13– 15current] are able load. to operate in a wide input voltage range, they cannot afford a high current load. Therefore, we we designed designed a anovel, novel, two two-module-module HV HV-linear-linear regulator regulator based based on CMOS, on CMOS, DMOS DMOS,, and andbipolar bipolar transistors,transistors, which which was able was to able operate to operate in a wide in ainput wide voltage input voltagerange (3.9 range–10 V) (3.9–10 and achieved V) and achieveda high load a highcurrent load (500 current mA) with (500 ensured mA) with stability ensured under stability various under conditions. various The conditions. paper is Theorganized paper isas organized follows: Section as follows: 2 introduces Section2 theintroduces configuration the configuration of our HV oflinear our HV regulator linear regulator circuit, Section circuit, 3 Sectiondescribes3 describes the implementation the implementation thereof, Section thereof, 4 Section demonstrates4 demonstrates the test results the test, and results, Section and Section5 contains5 containsconclusions. conclusions.

2. Configuration Configuration of the ProposedProposed HVHV LinearLinear RegulatorRegulator CircuitCircuit FigureFigure1 1 shows shows thethe configurationconfiguration ofof thethe proposedproposed HVHV linearlinear regulator,regulator, consistingconsisting ofof aa bandgapbandgap reference, an over over-temperature-temperature protection protection (OTP) (OTP) circuit, circuit, an an over over-current-current protection protection (OCP) (OCP) circuit, circuit, a apreregulator, preregulator, and and a alinear linear regulator regulator core core circuit circuit.. The The preregulator preregulator and and linear linear regulator regulator core constitute two distinctdistinct modules.modules. TheThe preregulator preregulator converts converts a a high high input input voltage voltage to ato stable a stable low low voltage voltage (Vdd (Vdd= 3 = V 3) usedV) used for for supplying supplying most most other other circuits, circuits, as as shown shown in in Figure Figure1. 1. High-voltage High-voltage DMOS DMOS transistors transistors werewere usedused as the power in the preregulator and wherever high voltage existed in the circuit design. All other devices employed were either normal CMOS transistors,transistors, for the purposes of easier control, better matching matching,, and and lower lower quiescent quiescent current current,, or or bipo bipolarlar transistors transistors in the in the output output stage stage of the of thelinear linear regulator regulator for supporting for supporting high high voltage voltage and delivering and delivering a higher a higher power power with witha smaller a smaller chip area. chip area.A high A-precision high-precision bandgap bandgap reference reference was used was to used provide to provide reference reference voltage voltage for the forpreregulator the preregulator circuit circuit[16,17]. [ 16The,17 OTP]. The and OTP OCP and circuits OCP circuits can be canused be to used safeguard to safeguard regulator regulator operation operation [18]. At [18 an]. Atinput an inputvoltage voltage ranging ranging from from3.9 to 3.9 10 to V, 10 the V, thedesign design adopted adopted a 0. a 0.25 25µmµm 5 5V VCMOS CMOS process process combined combined with 20 V DMOSDMOS/bipolar/bipolar devices to implement the circuit. To avoid interference between the preregulator and thethe corecore linearlinear regulator, regulator, the the preregulator preregulator featured featured an activean active low-pass low-pass filter filter to provide to provide a low-noise, a low- high-precisionnoise, high-precision reference reference voltage voltage (Vref 1) ( toVref the1) linearto the regulatorlinear regulator core, as core, shown as inshown Figure in1 Fig. Theure typical 1. The outputtypical voltageoutput voltage of the proposed of the proposed HV linear HV regulator linear regulator was 2.5 was V. 2.5 V.

Vin

Resistor Vdd Bandgap Vref Pre- network network reference Vref1 Linear Vout regulator regulator core Votp OCP OTP Vocp

Figure 1. The configuration configuration of the proposed design.

3. Implementation of the P Proposedroposed HV Linear RegulatorRegulator

3.1. The Preregulator Featuring an Active Low-Pass Filter 3.1. The Preregulator Featuring an Active Low-Pass Filter Figure2 shows the preregulator consisting of an error amplifier, a start-up circuit, a resistor Figure 2 shows the preregulator consisting of an error , a start-up circuit, a resistor network circuit, and the active, low-pass filter. The start-up and resistor network circuits that operate at network circuit, and the active, low-pass filter. The start-up and resistor network circuits that operate high input were implemented by DMOS transistors (DM1–DM5). The start-up circuit ensured at high input voltages were implemented by DMOS transistors (DM1–DM5). The start-up circuit that the preregulator attained the desired operating conditions. As shown in Figure2, when Vin is ensured that the preregulator attained the desired operating conditions. As shown in Figure 2, when applied with , resistor R1, with proper resistance, forces node Vout1 to increase with Vin. Vin is applied with power supply, resistor R1, with proper resistance, forces node Vout1 to increase

Electronics 2019, 8, 1143 3 of 14

Then, a current is generated in DM1, DM3, and R3, which ensures that other components quickly recover. Finally, a negative feedback loop consisting of the error amplifier, DM1–DM3, and R2–R4 forces the preregulator to work in a stable condition. In addition, -connected transistors DM4 and DM5 were used to reduce fluctuation at node Vout1. With deliberately selected resistance for the resistor network circuit, a 3 V internal power voltage (Vdd) was obtained, and a low-noise, high-precision reference voltage (Vref 1) for the linear regulator core was generated after the active filter. Given the high (DC) gain of the error amplifier, Vref 1 and Vref are ideally identical. The internal power supply voltage Vdd can be expressed as

R2 + R4 Vdd Vre f + V , (1) ≈ R4 ∗ GS,M1 where transistors M1 and M2 work in the subthreshold region, and the drain current ID can be expressed by [19] ! W VGS VTH Electronics 2019, 8, x FOR PEER REVIEW ID I0exp − ,3 of (2)14 ≈ L ηVT 2 wherewith VinI0. =ThenµC,ox a( ηcurrent1)V is, andgeneratedµ, VTH in, V DM1,T, η, andDM3C,ox andrepresent R3, which the ensures carrier mobility,that other the components threshold − T quicklyvoltage recover. of the transistor, Finally, a thenegative thermal feedback voltage, loop the consisting subthreshold of the slopeerror factor,amplifier, and DM1 the– gate-oxideDM3, and R2capacitance,–R4 forces respectively.the preregulatorW and to workL are in width a stable and condition. length of theIn a transistor,ddition, diode respectively.-connected The transistors value of DM4the resistor and DM5Req inwere M2 used is dictated to reduce by the fluctuation current flowing at node in Vout1 transistor. WithM2 deliberately (ID,M2) and selected the drain-source resistance forvoltage the resistor thereof (networkVref 1 Vfbcircuit,), as follows:a 3 V internal power voltage (Vdd) was obtained, and a low-noise, − high-precision reference voltage (Vref1) for the linear regulator core was generated after the active Vre f 1 V f b filter. Given the high direct current R (DC)= gain of− the errorR5. amplifier, Vref1 and Vref are ideally (3) eq I identical. The internal power supply voltage VddD can,M2 be expressed− as

Vin

I1 I2 DM1 DM2 R1 Vdd Isub Vref R2 Vout1 DM3 Error amplifier M1

R5 Vref1 DM4 R3 M2 Vfb C1 Proposed DM5 R4 low-pass filter Start-up Resistor circuit network

Figure 2. PreregulatorPreregulator with with an an active active low low-pass-pass filter. filter.

Thus, an active RC low-pass filter implemented푅2+푅4 using a mirror circuit (NMOS transistors M1 and 푉푑푑 ≈ ∗ 푉푟푒푓 + 푉 , (1) M2) is included, as shown in Figure2. It can e 푅ff4ectively reduce퐺푆,푀 noise1 with significantly reduced chip wherearea when transistors compared M1 to and a real M2 resistive work in polyresistor the subthreshold with similar region, resistance, and the and drain the cut-o currentff frequency 퐼퐷 can befc expressedof the active by RC [19] low-pass filter is

푊 푉퐺푆−푉푇퐻 1 퐼퐷 ≈ 퐼0푒푥푝 ( 1 ), (2) fc = =퐿  휂푉푇  , (4) 2πRout, f C1 2 2π Rout1 + R5 + Req C1 where 퐼0 = 휇퐶표푥(휂 − 1)푉푇 , and μ, 푉푇퐻, 푉푇, η, and C표푥 represent the carrier mobility, the threshold voltage of the transistor, the thermal voltage, the subthreshold slope factor, and the gate-oxide capacitance, respectively. W and L are width and length of the transistor, respectively. The value of the resistor 푅푒푞 in M2 is dictated by the current flowing in transistor M2 (퐼퐷,푀2) and the drain-source voltage thereof (Vref1 – Vfb), as follows: 푉푟푒푓1−푉푓푏 푅푒푞 = − 푅5. (3) 퐼퐷,푀2 Thus, an active RC low-pass filter implemented using a mirror circuit (NMOS transistors M1 and M2) is included, as shown in Figure 2. It can effectively reduce noise with significantly reduced chip area when compared to a real resistive polyresistor with similar resistance, and the cut-off frequency 푓푐 of the active RC low-pass filter is 1 1 푓푐 = = , (4) 2휋푅표푢푡,푓퐶1 2휋(푅표푢푡1+푅5+푅푒푞)퐶1 where 푅표푢푡1 is the output resistance viewed at point Vfb. Therefore, the final output reference voltage Vref1(f) is: 푉푟푒푓1(0) 푉푟푒푓1(푓) = 푓 , 1+푗 (5) 푓푐 where Vref1(0) is approximately equal to Vfb. To ensure an appropriate cut-off frequency, the equivalent resistance of 푅푒푞 is controlled by a simple mirror circuit consisting of NMOS transistors M1 and M2, as shown in Figure 2. Given the M2:M1 (width/length) ratio of 1:4000, the M2 current (

Electronics 2019, 8, 1143 4 of 14

where Rout1 is the output resistance viewed at point Vfb. Therefore, the final output reference voltage Vref 1(f) is: Vre f 1(0) Vre f 1( f ) = , (5) f 1 + j fc where Vref 1(0) is approximately equal to Vfb. To ensure an appropriate cut-off frequency, the equivalent resistance of Req is controlled by a simple mirror circuit consisting of NMOS transistors M1 and M2, as shown in Figure2. Given the M2:M1 (width /length) ratio of 1:4000, the M2 current (ID) is low. ElectronicsIn other words,2019, 8, x high-frequency FOR PEER REVIEW noise is well filtered from the output reference voltage. Table1 lists4 of the 14 size of components used in the preregulator, and the simulated spectral density of noise at the output 퐼reference퐷) is low. node In other (Vref 1)words, versus high frequency-frequency is shown noise in is Figure well filtered3, where from an approximately the output reference 625 nV/ voltage.√Hz of Tablenoise density1 lists the at 100size Hzof components is obtained. used in the preregulator, and the simulated spectral density of noise at the output reference node (Vref1) versus frequency is shown in Figure 3, where an approximately 625 nV/√Hz ofTable noise 1. densityComponent at 100 sizes Hz of is the obtained. preregulator.

ComponentsTable 1. Value Component sizes Componentsof the preregulator. Value DM1(W/L) 40 µm/0.4 µm M1(W/L) 200 µm/0.5 µm Components Value Components Value DM1(DM2(W / L)W /L)40 µm 600 /µ 0.4m/ 0.4µmµ mM1 M2((W /W L)/ L)200 1 µ µmm/10 / 0.5µm µm DM2(DM3W / L) ( W/L)600 20µmµ m/ 0.4/0.45 µmµ m M2(C1W /(pF) L) 1 µm 5.3 / 10 µm DM3DM4, (W / DM5( L) W/L)20 µm 20 / µ0.45m/5 µmµm R1/R2C1/R3 (pF/R4) /R5 (kΩ) 1800/3205.3/1/400 /75 DM4, DM5(W / L) 20 µm / 5 µm R1/R2/R3/R4/R5 (kΩ) 1800/320/1/400/75

Figure 3. SSimulatedimulated noise noise of of VrefVref11 versus versus increasing increasing freque frequency.ncy.

As shown shown in in Figure Figure 2,2, drain drain currents currents II1퐼I 1andand II2 퐼I2 flowflow throughthrough DM1 and DM2, DM2, respectively, respectively, 1 1 2 2 and Isub 퐼Isub is the supply current for other subsequent circuits. So（(I2 Isub）)((퐼 I2− 퐼Isub)) is the current and Isub 푠푢푏 is the supply current for other subsequent circuits. So I2−- Isub 2 − 푠푢푏 is the current flowing through network (R2, R5, and R4). Since DM1 and DM2 are matched in a current flowing through network resistors (R2, R5, and R4). Since DM1 and DM2 are matched in a current mirror, and I2 (W/L)DM2/(W/L)DM1I1 I2 (W/L)DM2/(W/L)DM1I1, the total current consumption mirror, and I≈2  (W / L)DM 2 /(W / L)DM1 I1 퐼2 ≈≈(푊⁄퐿)퐷푀2/(푊⁄퐿)퐷푀1퐼1, the total current consumption of the resistor network can, therefore, be calculated as (I1 + I2 Isub) (I1 + I2 Isub). − ( − ) of the resistor network can, therefore, be calculated as (I1  I 2  I sub ) 퐼1 + 퐼2 − 퐼푠푢푏 . 3.2. The Core Linear Regulator 3.2. The Core Linear Regulator Figure4 shows the linear regulator core circuit featuring an error amplifier and a feedback resistor networkFigure circuit. 4 shows The the low-noise linear regulator reference core voltage circuitVref featuring1 is provided an error by the amplifier preregulator and a described feedback resistorin the previous network section. circuit. R Theload is low the-noise load resistor, reference and voltage a 22 µ VrefF off1-chip is provided by with the an preregulator equivalent describedseries resistance in the previous (ESR) of section. 10 mΩ was푅푙표푎푑 used is the to load ensure resistor, linear and regulator a 22 µF core off- stabilitychip capacitor and to with reduce an equivalentover-under-shoot series resistance voltage. (ESR)R4 and of R510 formmΩ was the used feedback to ensure resistor linear network, regulator and core DMOS stability transistors and to reduce(DM1–DM3) over- constituteunder-shoot the voltage.driver to R4 provide and theR5 baseform current the feedback for the power resistor transistor network Q1., and Supplied DMOS by transistorsthe preregulator, (DM1– theDM3) error constitute amplifier the with driver PMOS to provide/NMOS-input the base pairs current and for an the output power push–pull transistor stage Q1. Supplied by the preregulator, the error amplifier with PMOS/NMOS-input pairs and an output push– pull stage significantly improved the transient response speed of the linear regulator core. As shown in Figure 4, the tail current (M6) in the NMOS differential–input pair was biased by the current– mirror transistor M4 of the PMOS differential–input pair; this improved the speed of the linear regulator core as well. For supplying a maximum load current of 500 mA, a power DMOS transistor would require a significantly large area of silicon. Thus, we used a smaller-sized and high-voltage NPN bipolar transistor Q1 as the power transistor, which enhanced the driving ability of the linear regulator and improved areal efficiency. The width/length ratio k between DM2 and DM1 was set to 400 to ensure efficient driving of power transistor Q1 in this study. Table 2 lists the sizes of the main components of the linear regulator core.

Electronics 2019, 8, 1143 5 of 14 significantly improved the transient response speed of the linear regulator core. As shown in Figure4, the tail current (M6) in the NMOS differential–input pair was biased by the current–mirror transistor M4 of the PMOS differential–input pair; this improved the speed of the linear regulator core as well. For supplying a maximum load current of 500 mA, a power DMOS transistor would require a significantly large area of silicon. Thus, we used a smaller-sized and high-voltage NPN bipolar transistor Q1 as the power transistor, which enhanced the driving ability of the linear regulator and improved areal efficiency. The width/length ratio k between DM2 and DM1 was set to 400 to ensure efficient driving of power transistor Q1 in this study. Table2 lists the sizes of the main components of the linear regulatorElectronics 2019 core., 8, x FOR PEER REVIEW 5 of 14

Vin Vdd 1 : k DM1 DM2 M11 M16 M9 M10 DM3 R2 C2 Ibias M15Von M0 M1 R0 C0 Vout2 Q1 Vout1 Votp R 3 C3 M7 M8 M2 M3 Vout R1 C1 Vocp Vop M13 Off-chip R4 cap M6 M4 M5 Rload Vref1 M12 R6 Vfb1 Co M14 R5

NMOS-input pair PMOS-input pair Push-pull stage Feedback resistor network Figure 4. Implementation of the linear regulator core circuit.circuit.

Table 2. Main component sizes of the linear regulator core circuit. Table 2. Main component sizes of the linear regulator core circuit. C0,1/R2,3 R0,1/R2,3 DM1 DM3 Q1 Components C0,1/R2,3 R0,1/R2,3 DM1 k DM3 Q1 Components (pF) (kΩ) (Width/Length) k (Width/Length) (Number) (pF) (kΩ) (Width/length) (Width/length) (number) Value 1.3/3.0 45/22.5 40 µm/800 nm 400 400 µm/450 nm 984 (5 µm 5 µm) Value 1.3/3.0 45/22.5 40 µm/800 nm 400 400 µm/450 nm 984 (5 µ×m × 5 µm)

To ensure ensure the the stability stability of of the the linear linear regulatorregulator core core circuit,circuit, we we used used the the Miller Miller compensationcompensation technique in in the the design. design. As As can can be be seen seen from from Figure Figure4, 4C,0 퐶0C3−and퐶3 R 0andR 3푅0are− Miller푅3 capacitorsare Miller − − andcapacitors resistors, and respectively. resistors, respectively. Figure5a isFig aure small-signal 5a is a small model-signal of the model linear of regulatorthe linear core.regulator Both core the. PMOSBoth the and PMOS NMOS and inputNMOS pairs input could pairs be could taken be astaken separate, as separate single-stage, single-stage operational operational amplifiers and, thus,and, thus exhibited, exhibit singleed single dominant dominant poles poles at output at output nodes nodesVop and 푉표푝V andon, respectively. 푉표푛, respectively.Rop and 푅표푝Ron andare 푅 the표푛 equivalentare the equivalent output output resistances resistances of the PMOSof the PMOS and NMOS and NMOS input pairs,input respectively.pairs, respectively.Cop and 퐶표푝Con andare the퐶표푛 equivalentare the equivalent output parasiticoutput parasitic capacitances capacitances of the PMOS of the and PMOS NMOS and inputNMOS pairs, input respectively. pairs, respectively.Cop was derived퐶표푝 was principallyderived principally from the fromCGS ofthe M12, 퐶퐺푆 whereasof M12, whereasCon was 퐶 attributable표푛 was attributable mainly tomainly the C GSto ofthe M11. 퐶퐺푆 Givenof M11. the Given small the sizes small of transistorssizes of transistors M11 and M11 M12, andCop M12,and C퐶on표푝 hadand minimal퐶표푛 had capacitances.minimal capacitances.Gmp and G퐺푚푝mn areand the 퐺푚푛 transconductances are the transconductances of PMOS and of NMOSPMOS andinput NMOS pairs, respectively,input pairs, where respectively,Gmp = wheregmp2,3 and퐺푚푝 G=mn푔푚푝=2,g3mn and7,8 [16퐺푚푛]. g=mp푔2,3푚푛is7,8 the[16]. transconductance 푔푚푝2,3 is the transconductance of M2 and M3 (assumingof M2 and that M3 M2(assuming and M3 that are matched),M2 and M3 and areg matched)mn7,8 is the, and transconductance 푔푚푛7,8 is the transconductance of M7 and M8 (assuming of M7 and that M8 M7 (assuming and M8 are that matched), M7 and asM8 shown are matched), in Figure as4 shown. At an in appropriate Figure 4. At bias an appropriate current, correct bias sizescurrent, of thecorrect PMOS size ands of the NMOS PMOS input and pairsNMOS ensured input that pairsg mpensuredand g mnthatwere 푔푚푝 equivalent: and 푔푚푛 Gweremp,n =equivalent:gmp,n = g mp퐺2,3푚푝,=푛 =gmn푔푚푝7,8,.푛 C=p1푔is푚푝 the2,3 = parasitic푔푚푛7,8 . capacitance퐶푝1 is the parasitic of the push–pull capacitance stage of the output, push– attributablepull stage output, principally attributable to CGS ofprincipally DM3. to 퐶퐺푆 of DM3.

Electronics 2019, 8, 1143 6 of 14 Electronics 2019, 8, x FOR PEER REVIEW 6 of 14

R3 C3 - gmp G Vop mp R1 C1 Cop Rop Vin Vout1 Vout2 rq1 Vout - gdmn - kgdmp gmQ 1 R0 C0 R4 Rload Von gdmp G rop ron Cp1 Cp3 Cp2 req Co rq1 mn Vfb1 Con Ron - g mn R5 R2 C2

(a)

R3 C3 - gmp

R1 C1 G m  VinGmp,n Vop,n Vout1 Vout2 rq1 Vout kgdmn gdmp gmQ

1 p s Rop//Ron R4 Rload R0 C0 rop ron Cp1 Cp2 req Co rq1 Vfb1 Cop+Con - g mn R5 R2 C2

(b)

FigureFigure 5.5. ((a)a) Small-signalSmall-signal model model of of the the proposed proposed linear linear regulator regulator core; core (b; )(b simplified) simplified small-signal small-signal model. model. As the DMOS transistor DM3 (width = 400 µm, length = 450 nm) was large, the capacitance of Cp1 was greaterAs the DMOS than that transistor of both DM3Cop and(widthCon =. The400 µm transconductances, length = 450 nm of) was M11 large, and the M12 capacitance are gmp and of gmn, respectively.퐶푝1 was greatergdmn thanis the that transconductance of both 퐶표푝 and of퐶표푛 DM3,. The whereastransconductances DM2 and DM1of M11 generate and M12 a transconductanceare 푔푚푝 and of푔푚푛kg,dmp respectively.due to their 푔푑푚푛 width is / thelength transconductance ratio of k. 1/ g ofdmp DM3,and C whereasp3 are the DM2 equivalent and DM1 output generate resistance a andtransconductance the parasitic of capacitance 푘푔 due of to the their mirror width/length node between ratio of k. DM1 1⁄푔 and DM2,and 퐶 respectively. are the equivalent Therefore, 푑푚푝 푑푚푝 푝3   theoutput DM1–DM3 resistance combination and the couldparasitic be considered capacitance to of exhibit the mirror a large nodeGm = betweenkgdmn gdmp DM1/ 1 + andωp , DM2, as shown inrespectively. the simplified Therefore, small-signal the DM1 model–DM3 of Figure combination5b. The frequencycould be considered of ωp was highto exhibit given a its large low resistance퐺푚 = (푘푔1/푑푚푛gdmp푔)푑푚푝 and/(1 capacitance+ 휔푝), as shown (Cp3); thus,in the it simplified did not a ffsmallect the-signal loop model stability of ofFig theure linear 5b. The regulator frequency core. of gmQ ⁄ is휔푝 the was transconductance high given its low of Q1;resistancerq1 is the (1 equivalent푔푑푚푝) and capacitance output resistance (퐶푝3); thus viewed, it did at thenot emitteraffect the node loop of Q1; 푔 푟 Cstabilityo is the oofff the-chip linear capacitor; regulator and coreRload. is푚푄 the is loadthe transconductance resistor. As shown of inQ1; Figure 푞1 is5 ,theVop equivalentand Von of output Figure 5a 퐶 푅 canresistance be merged viewed into at the the single emitter node nodeVop , ofn of Q1; Figure 표 is5b, the where off-chipRop // capacitor;Ron and andCop +푙표푎푑Con areis the the load lumped resistanceresistor. As and shown capacitance. in Figure Thus,5, 푉표푝 theand DC 푉표푛 gain of Fig ofure the 5 corea can linear be merged regulator into the is: single node 푉표푝,푛 of Figure 5b, where 푅 //푅 and 퐶 + 퐶 are the lumped resistance and capacitance. Thus, the DC 표푝 h표푛 표푝 표푛i h  i     gain of the core linearAv regulatorGmp,nR is:op //Ron gmp,n rop//ron Gmreq g Rout , (6) ≈ × × × mQ 퐴푣 ≈ [퐺푚푝,푛푅표푝//푅표푛] × [푔푚푝,푛(푟표푝//푟표푛)] × (퐺푚푟푒푞) × (푔푚푄푅표푢푡), (6) where the equivalent output resistor Rout = rq1//Rload//(R4 R5) Obviously, four principal poles 푅 = 푟 //푅 //(R4 − 푅5 ) werewhere produced the equivalent at nodes outputVop,n ( resistorωp1), V out표푢푡1 (ωp4),푞1Vout푙표푎푑2 (ωp3), and Vout (ω pObviously,2) of the stability four principal loop. Miller poles were produced at nodes 푉 (휔 ), 푉 (휔 ), 푉 (휔 ), and 푉 (휔 ) of the stability C0 and C1 with identical표푝,푛 capacitances푝1 표푢푡1 (C푝0,4 1) split표푢푡2 the푝3 poles between표푢푡 푝 nodes2 Vout1 and Vop,n; theloop. two Miller poles capacitors can be expressed 퐶0 and as 퐶 [116] with identical capacitances (C0,1 ) split the poles between nodes 푉표푢푡1 and 푉표푝,푛 ; the two poles can be expressed as [16] 11 ωpM휔1푝푀1 ≈ h , i, (1⁄푔푚푝,푛)[퐶푝1+퐶0,1 ] ≈ 1/gmp,n Cp1 + C0, 1 1 (7) (7) 휔 = . 푝푀2 (푅 //푅 )퐶0,1 푔 1[푟 //푟 ] ωpM2 = 표푝 표푛  푚푝,푛 표푝 표푛h i. Rop//Ron C0, 1gmp,n rop//ron Similarly, Miller capacitors 퐶2 and 퐶3 with identical capacitances 퐶2,3 split the poles

between nodes 푉표푢푡2 and 푉표푝,푛 ; the two poles can be expressed as [16]

Electronics 2019, 8, 1143 7 of 14

Similarly, Miller capacitors C2 and C3 with identical capacitances C2, 3 split the poles between nodes Vout2 and Vop,n; the two poles can be expressed as [16]

1 ωpM3  h i, ≈ 1/gmQ Cp2 + C2, 3 (8) 1 ωpM4   h i . ≈ Rop//Ron C2, 3gmp,n rop//ron Gmreq

A low-frequency pole developed at node Vop,n given the chosen Miller compensation; this is the dominant pole ωp1 of the stability loop, expressed as:

1 ωp1 , (9) ≈ coutp,nroutp,n where the equivalent capacitor coutp,n and the resistor routp,n at node Vop,n can be expressed as:     coutp,n C0, 1gmp,n rop//ron + C2, 3gmp,n rop//ron Gmreq, (10) ≈

routp,n Rop//Ron. (11) ≈ The equivalent capacitor coutp,n was amplified by the inter amplifiers of the stability loop. As transistor DM3 had a smaller parasitic capacitor than that of power transistor Q1, the pole at node Vout1 was of higher frequency than the pole at node Vout2 (ωp4 = ωpM2 > ωp3 = ωpM3). As the off-chip capacitor Co had a capacitance of 22 µF, a second dominant pole was generated at output node Vout, given by 1 1 ωp2 h i. (12) ≈ c R ≈ o out co rq1//Rload//(R4 + R5)

Thus, the four poles may be ordered as ωp4 > ωp3 > ωp2 > ωp1. Also, two left half-plane (LHP) zeros, ωz1 and ωz2, featuring appropriate resistors and capacitors, were used to compensate for phase shifts caused by the poles of the stability loop [16]. The external ESR and output off-chip capacitor (Co) generated a third LHP zero to compensate for the negative phase shift caused by the low-frequency nondominant pole [20]. Consequently, four poles and three LHP zeros were generated in the loop of the linear regulator core. Appropriate sizing of the compensation resistors and capacitors ensured that the linear regulator core was stable in various operating conditions. Figure6 shows the simulated loop response results at di fferent current loads (0, 10, 100, 250, and 500 mA) under different input supply voltages (3.9 and 10 V). As the current load changes, the output equivalent resistor values vary, slightly affecting the DC gain of the linear regulator core loop. Figure7 shows the simulated phase margins (PMs) and unity gain frequencies versus load current under various conditions of different input voltages (3.9 and 10 V), process corners (TT, SS, and FF), and temperatures ( 40 to 85 C). It is clearly seen that the PMs were over 30 in all simulated cases. In most − ◦ ◦ cases, the PMs were over 50◦, ensuring linear regulator core stability over large input voltage and current load ranges. Electronics 2019, 8, x FOR PEER REVIEW 8 of 14 Electronics 2019, 8, 1143 8 of 14 Electronics 2019, 8, x FOR PEER REVIEW 8 of 14

500 mA 250mA 150000m mAA 1205m0mAA 100m0AmA 10mA 0mA

(a) (a)

(b)

(b) Figure 6. Simulated loop response results of the linear regulator core with different current loads; (a) FiguresupplyFigure 6.voltage6. Simulated of 3.9 loop loopV; (b response) response supply voltageresults results ofof of the10 the V.linear linear regulator regulator core core with with different different current current loads loads;; (a) (asupply) supply voltage voltage of of3.9 3.9 V; V;(b ()b supply) supply voltage voltage of of10 10 V. V.

(a) (b)

Figure 7. The simulated( phasea) margins (PMs) and unity gain frequency with(b di) fferent cases; (a) PMs; Figure 7. The simulated phase margins (PMs) and unity gain frequency with different cases; (a) PMs; (b) unity gain frequency. (bFigure) unity 7. gain The frequencysimulated. phase margins (PMs) and unity gain frequency with different cases; (a) PMs; 3.3. Bandgap(b) unity and gain Protection frequency Circuits. 3.3. Bandgap and Protection Circuits Figure8a shows the bandgap core circuit in this study, which provided reference voltages and bias 3.3. Bandgap and Protection Circuits currentsFigure for 8 othera shows subsequent the bandgap circuits. core The circuit operational in this study, amplifier which forced provided nodes referenceVp and Vnvoltageson virtual and ,bias currentsFigure and 8 theafor shows resistorother the subsequentR4 bandgapand the corecircuits. capacitor circuit The C1in operational thisformed study, a low-pass whichamplifier provided filter forced for referencenodes the output Vp voltages and reference Vn andon virtual ground, and the resistor R4 and the capacitor C1 formed a low-pass filter for the output voltage.bias currents The outputfor other reference subsequent voltage circuits.Vre f Theln (operationalN)∆VBER1, amplifier3/R2 + V BEforced, where nodesR1, 3Vp= andR1 =VnR on3, ≈ 푉푟푒푓 ≈ 푙푛(푁)∆푉 푅1 3⁄푅2 + 푉 푅1,3 = andreferencevirtualVref ground, has voltage. a low-temperature and The the output resistor reference coe R4ffi andcient voltage the (TC). capacitor The simulated C1 formed temperature퐵퐸 a low, -pass coe filterffi퐵퐸cient, wherefor (TC) the output of the 푅1 = 푅3, and Vref has a low-temperature coefficient (TC). The simulated temperature coefficient (TC) reference voltage. The output reference voltage 푉푟푒푓 ≈ 푙푛(푁)∆푉퐵퐸푅1, 3⁄푅2 + 푉퐵퐸 , where 푅1,3 = 푅1 = 푅3, and Vref has a low-temperature coefficient (TC). The simulated temperature coefficient (TC)

Electronics 2019, 8, x FOR PEER REVIEW 9 of 14 Electronics 2019, 8, 1143 9 of 14 Electronicsof the bandgap 2019, 8, x reference FOR PEER REVIEWvoltage is shown in Figure 8b, where an approximate 3.4 ppm/°C TC under9 of 14 different CMOS processes over temperatures ranging from –40 to 85 °C was achieved. ofbandgap the bandgap reference reference voltage voltage is shown is shown in Figure in8 Figureb, where 8b an, where approximate an approximate 3.4 ppm /3.4◦C ppm/ TC under°C TC di ffundererent differentCMOS processes CMOS process overVdd temperatureses over temperature rangings from ranging40 from to 85 –◦40C wasto 85 achieved. °C was achieved. − M3 M6 M12 Vdd M3 M6 M12 M1 M4 M7 M13 R4 M1 M4 M7 M13 Vref R1 RR34

M8 M9 Vn Vref R1 R3 Vp M8 M9 Vn C1 VRp2 M10 M11 N : 1 C1 M2 M5 R2Q1 Q2 M10 M11 N : 1 M2 OpeMr5ational amplifier Q1 Q2

Operational amplifier (a) (b) (a) (b) Figure 8. (a) Bandgap core circuit; (b) simulated temperature coefficient of Vref. Figure 8. (a) Bandgap core circuit; (b) simulated temperature coefficient of Vref. Figure 9 showsFigure 8.protection (a) Bandgap circuits core circuit including; (b) simulated an OCP temperature circuit and coefficient an OTP ofcircuit. Vref. As shown in FigureFigure 9a, Vref9 shows was provided protection by circuitsthe bandgap including circuit, an the OCP operational circuit and amplifier an OTP (OP) circuit. with As R1 shown, and M1 in– Figure 9 shows protection circuits including an OCP circuit and an OTP circuit. As shown in M3Figure produce9a, Vrefd awas low provided TC bias bycurrent the bandgap for M4. circuit, Transistors the operational M4–M7 with amplifier the same (OP) sizes with wereR1, and in M1–M3current Figure 9a, Vref was provided by the bandgap circuit, the (OP) with R1, and M1– mirror.produced DMOS a low transistors TC bias current DM1– forDM3 M4. were Transistors used to M4–M7 avoid damage with the to same transistors sizes were M5 in–M7, current due mirror.to the M3 produced a low TC bias current for M4. Transistors M4–M7 with the same sizes were in current highDMOS supply transistors voltage DM1–DM3 Vin. Bipolar were usedtransistor to avoid Q0 damage mirrored to withtransistors Q1 was M5–M7, adopted due to the sense high the supply load mirror. DMOS transistors DM1–DM3 were used to avoid damage to transistors M5–M7, due to the current,voltage Vinwhere. Bipolar Q1 with transistor R4 and Q0 R5 mirroredwas a part with of linear Q1 was regulator adopted core to sense, and the the ratio load current,of Q0 and where Q1 was Q1 high supply voltage Vin. Bipolar transistor Q0 mirrored with Q1 was adopted to sense the load with1/984.R4 Whenand R5 thewas load a part current of linear was regulatortoo high core,(in an and over the-current ratio of condition), Q0 and Q1 the was mirrored 1/984. When current the current, where Q1 with R4 and R5 was a part of linear regulator core, and the ratio of Q0 and Q1 was flowingload current Q0 generated was too high a larger (in an voltage over-current difference condition), on R6. In the this mirrored case, the current drain flowingcurrent Q0in DM5 generated will be a 1/984. When the load current was too high (in an over-current condition), the mirrored current smallerlarger voltage than the di ffdrainerence current on R6 in. In DM4, this case,so that the M7 drain with current the same in DM5 size of will M6 be is smaller forced to than work the in drain the flowing Q0 generated a larger voltage difference on R6. In this case, the drain current in DM5 will be linearcurrent region. in DM4, In soother that words, M7 with an theover same-current size signal of M6 Vocp is forced was togenerated, work in theand linear it was region. used to In low otherer smaller than the drain current in DM4, so that M7 with the same size of M6 is forced to work in the words,the base an current over-current for both signal Q0 Vocpand Q1,was leading generated, to a and reduced it was output used to current lower theand base, thus current, over- forcurrent both linear region. In other words, an over-current signal Vocp was generated, and it was used to lower protection.Q0 and Q1, leading to a reduced output current and, thus, over-current protection. the base current for both Q0 and Q1, leading to a reduced output current and, thus, over-current protection. Q0:Q1=1:984 Vin Vdd R3 R6 M9 M10 M11 Vdd Vout2 Q0:Q1=1:984 Vin Vdd M2 M3 DM4R3 DM5 R6 Q0 Q1 M9 M10 M11 Vdd Ib Vout2 Vref DM1 DM2 Vtemp Vout Bandgap Ibias Comp OP M2 M1 M3 DM4 DDMM35 R2 R4 V1 Votp Ib Q0 Q1 Vref Vocp Vtemp DM1 DM2 M8 R5 R7 Vout Bandgap Ibias Comp OP M1 M4 M5 M6 DMM73 R2 R4 V1 Votp Part of Core Q2 R8 R1 Vocp M12 M8 RReg5ulator R7 M4 M5 M6 M7 Part of Core （a） Q（2 bR）8 M12 R1 Regulator Figure 9. Protection circuits; (a) over-current protection (OCP) circuit; (b) over-temperature protection Figure 9. Protection circuits;（ a(）a) over-current protection (OCP) circuit; (b（) b）over-temperature protection(OTP) circuit. (OTP) circuit. Figure 9. Protection circuits; (a) over-current protection (OCP) circuit; (b) over-temperature Figure9b presents the OTP circuit, where the bias current Ibias is provided by the bandgap protectionFigure 9b ( OTPpresents) circuit. the OTP circuit, where the bias current 퐼푏푖푎푠 is provided by the bandgap circuit. The base-emitter voltage of Q2 (VBE,Q2 = Vtemp) was applied to the positive input node of the circuit. The base-emitter voltage of Q2 (푉퐵퐸,푄2 = 푉푡푒푚푝) was applied to the positive input node of the comparatorFigure 9 (Comp),b presents while the aOTP reference circuit, voltage whereV1 thegenerated bias current by M11,퐼푏푖푎푠R7 is, andprovidedR8 was by applied the bandgap to the comparator (Comp), while a reference voltage V1 generated by M11, R7, and R8 was applied to the circuit.negative The input base node-emitter of thevoltage comparator. of Q2 (푉 By selecting= 푉 ) awas proper appliedV1, theto the comparator positive input can keepnode aof high the negative input node of the comparator. 퐵퐸By,푄 2selecting푡푒푚푝 a proper V1, the comparator can keep a high comparatoroutput (Votp (Comp),) in a wide while temperature a reference range. voltage As the V1 base-emittergenerated by voltage M11, R7 of,Q2 and (V R8temp was) decreased applied versusto the output (Votp) in a wide temperature range. As the base-emitter voltage of Q2 (푉푡푒푚푝) decreased versus negativean increasing input temperature, node of the Vcomparator.temp became By lower selecting than V1a properat a high V1, temperature the comparator “T1”, can which keep was a high the an increasing temperature, 푉푡푒푚푝 became lower than V1 at a high temperature “T1”, which was the outputcritical ( temperature.Votp) in a wide The temperature comparator range. produced As the a base low-output-emitter Votpvoltage, which of Q2 turned (푉푡푒푚푝 o) ffdecreasedthe versus M12, critical temperature. The comparator produced a low-output Votp, which turned off the switch M12, anand increasing a higher voltage temperature,V1 was 푉 generated. became The low linearer than regulator V1 at corea high circuit temperature will be shut “T1” down, which by the was signal the and a higher voltage V1 was푡푒푚푝 generated. The linear regulator core circuit will be shut down by the criticalof Votp .temperature. Until the temperature The comparator drops toproduced a certain a valuelow-output “T2”, aVotp high, whichVotp enables turned theoff the linear switch regulator M12, and a higher voltage V1 was generated. The linear regulator core circuit will be shut down by the

ElectronicsElectronics 20192019,, 88,, 1143xx FORFOR PEERPEER REVIEWREVIEW 101010 ofof of 14 14 signalsignal ofof Votp.. UntilUntil thethe temperaturetemperature dropsdrops toto aa certaincertain valuevalue “T2”,“T2”, aa highhigh Votp enablesenables thethe linearlinear regulatorcoreregulator again. corecore “T1 again.T2” is “T1−T2” the temperature is the temperature window, which window can,, bewhich well can defined be well by selectingdefined by proper selecting M11, − properR7, and M11,R8. The R7, temperature, and R8.. The The window temperature temperature can eff ectively window window avoid can can e eaffff constantlyectiveectivelyly avoid avoid changing a a constantly constantly condition changing changing near the conditioncriticalcondition temperature. nearnear thethe criticalcritical temperature.temperature.

4. Measurements Measurements FigFigureure 1010 shows showsshows the the the layout layout layout of ofof the the the linear linear linear regulator regulator regulator circuit circuit circuit fabricated fabricated fabricated via a standardvia via a a standard standard 0.25 µ m 0.25 0.25CMOS µm CMOSprocess process with 20 with V DMOS 20 V and DMOS bipolar and devices. bipolar Thedevices. CMOS The transistors CMOS transistors operated atoper a supplyated at voltage a supply of voltage5 V, and of the 5 V, DMOS and the devices DMOS could devices correctly couldcould work correctlycorrectly at a maximum workwork atat aa drain-source maximummaximum draindrain voltage--sourcesource of 20 voltagevoltage V. The ofof total 2020 2 V.chip The area total including chip area the including BGR, OCP, the BGR, and OTP OCP, circuits and OTP (and circuits all pads) ((and was all pads approximately)) was approximately 1.67 mm (1140 148522 µm). To minimize process mismatching, we used the common-centroid technique to 1.67 mm× (1140(1140 × 1485 µm). To minimize process mismatching, we used the common--centroidcentroid techniquelayouttechnique the to activeto layoutlayout MOS thethe and activeactive bipolar MOSMOS transistors andand bipolarbipolar of thetransistorstransistors bandgap ofof circuit. thethe bandgap Additionally, circuit. we Additionally, added dummy we addedtransistors dummy to improve transistors matching. to improve As the matching. load current As the was load large, current two pads was were large,large, employed two two pads pads for were the employedconnectionemployed forfor of thethe Q1 connection toconnection the output ofof toQ1Q1 reduce toto thethe outputoutput the parasitic toto reducereduce resistance thethe parasiticparasitic in the resistance currentresistance paths. inin thethe currentcurrent paths.paths.

14651465mm m m   1140 1140

Figure 10. LayoutLayout of of the the proposed proposed regulator with pads.

FigFigureure 1111 shows showsshows the the the measured measured measured output output output voltages voltages voltages as the as as input the the input supply input supply supply voltage voltage voltage increased increased increased under di ff under undererent diloads.fffferenterent Figure loads. loads. 11 Fig Figa showsure 11 thea shows output the voltages output at voltages different at current difffferenterent loads current current (0–500 loads loads mA), (0 (0 and–500 Figure mA), and11b Figshowsure the11b outputshows voltagesthe output at voltages different at resistance difffferenterent loads resistanceresistance (0–100 loadsloads kΩ). (0(0 The–100 regulator kΩ). The operated regulator well operated as the wellsupply as voltagethe supply varied voltage from varied 3.9 to 10fromfrom V with 3.93.9 toto a fixed 1010 VV outputwithwith aa voltagefixedfixed outputoutput of 2.5 voltage V.voltage Figure ofof 12 2.52.5 shows V.V. FigFig theure line 12 showstransientshows thethe performance; lineline transienttransient Figure performance;performance; 12a shows FigFig thature 1 the2a shows output that voltage the output was 2.5 voltage V under was a load 2.5 V current under of a 10loadload mA currentcurrent and an ofof input 1010 mAmA supply andand an voltagean inputinput ranging supplysupply from voltage 4 to ranging 10 V. Figure from 12 4 bto shows 10 V. theFigure results 12b with shows a load the resultscurrentresults withwith of 50 aa mA loadload and cucurrentrrent an input ofof 5050 supply mAmA andand voltage anan inputinput ranging supplysupply from voltage 6 to 10 ranging V. In two from cases, 6 to overshoot10 V. In two voltages cases, wereovershoot 100 and voltages 60 mV, were respectively. 100 and 60 mV, respectively.

((aa)) ((b))

Figure 11. Measured output voltage versus input input supply supply voltage voltage (( aa)) with with different different current current loads loads and and ((b)) withwithith didifferentfferent resistanceresistanceresistance loads.loads.loads.

ElectronicsElectronics2019 2019, 8,, 11438, x FOR PEER REVIEW 11 of11 14 of 14

Electronics 2019, 8, x FOR PEER REVIEW 11 of 14

100mV 2.5V 60mV

10V 10V 100mV 2.5V 60mV 4V 6V 10V 10V 4V (a) (b6V)

Figure 12. Measured transient line performance of the proposed linear regulator. (a) load current is Figure 12. Measured transient line performance of the proposed linear regulator. (a) load current is 1010 mA; mA (b; )(b load) load current current( isa is) 50 50 mA. mA. (b) Figure 13 shows the transient load performance of the output voltage. Figure 13a demonstrates FigureFigure 12.13 Measuredshows the transient transient line load performance performance of the of proposed the output linear voltage. regulator Fig. ure(a) load 13a currentdemonstrates is thethe measured measured10 mA; (b results) resultsload current under under is transient 50transient mA. loadsloads fromfrom 0 to 400 400 mA, mA, and and Fig Figureure 1 313b bpresents presents the the results results underunder transient transient loads loads from from 0 0 to to 100 100 mAmA atat aa supply voltage of of 4 4 V. V. Fig Figureure 1 144 gives gives further further details details on on transienttransientFig loadure load 13 performance. performance.shows the transient Figure Figure load 1 144aa showsperformance shows the the results results of the as outputthe as thetransient voltage. transient load Fig loadchangedure 1 changed3a demonstratesfrom 0 from to 450 0 to 450themA, mA, measured and and Fig Figureure results 14 14b bshowsunder shows thetransient the results results loads as asthe from the transient transient 0 to 400 load mA, load varied and varied Figfrom fromure 0 1 to3 0b to200presents 200 mA mA at the ata supplyresults a supply voltageundervoltage oftransient of 6 V.6 V. A A figureloads figure from of of merit merit0 to 100FOM FOM mA11was atwas a supplyadoptedadopted voltage to compare of 4 V. the theFig transienture transient 14 gives response response further of details ofdiff dierentff erenton regulators,transientregulators, andload and itperformance. it is is defined defined as asFigure [ 6[6]] 14a shows the results as the transient load changed from 0 to 450 mA, and Figure 14b shows the results as the transient load varied from 0 to 200 mA at a supply 1 ∆푉표푢푡 퐼푞 1퐹푂푀 = 퐶퐿 × I , (13) voltage of 6 V. A figure of merit FOM was1 adopted∆Vout퐼퐿,푚푎푥 to compare퐼퐿,푚푎푥q the transient response of different FOM = CL , (13) regulators, and it is defined as [6] IL,max × IL,max where 퐶퐿 is the load capacitor, ∆푉표푢푡 is the maximum transient output-voltage variation, 퐼푞 is the 1 ∆푉표푢푡 퐼푞 wherequiescentC is thecurrent, load and capacitor, 퐼퐿,푚푎푥 ∆isVout the maximumis퐹푂푀 the maximum= 퐶 퐿 load current.× transient , Considering output-voltage the transient variation, responseI (13)is the L 퐼퐿,푚푎푥 퐼퐿,푚푎푥 q induced by input supply voltage variation, a new figure of merit (FOM2) was defined to express the quiescent current, and IL,max is the maximum load current. Considering the transient response induced where 퐶 is the load capacitor, ∆푉표푢푡 is the maximum transient output-voltage variation, 퐼 is the byperformance input supply퐿 of voltage different variation, regulators, a new and figure it is given of merit by (FOM2) was defined to express the performance푞 quiescent current, and 퐼퐿,푚푎푥 is the maximum load current. Considering the transient response of different regulators, and it is given by 퐹푂푀2 = 퐹푂푀1 × 퐿푖푛푒푅, (14) induced by input supply voltage variation, a new figure of merit (FOM2) was defined to express the performancewhere 퐿푖푛푒푅 ofis dilinefferent regulation regulators, [21]. andTable it 3is summarizes given by the performance of the proposed regulator; FOM2 = FOM1 LineR, (14) the results were compared to those of other studies. At× a quiescent current of 350 µA and a supply 퐹푂푀2 = 퐹푂푀1 × 퐿푖푛푒푅, (14) wherevoltageLineR of is 3.9 line to regulation10 V, our proposed [21]. Table linear3 summarizes regulator theincluding performance bandgap of and the proposed protection regulator; circuits wheredelivered 퐿푖푛푒푅 a maximum is line regulation current [21]. of 500 Table mA. 3 summarizes The proposed the linear performance regulator of withoutthe proposed voltage regulator; ripples the results were compared to those of other studies. At a quiescent current of 350 µA and a supply theachieved results competitive were compared load regulation,to those of lineother regulation, studies. At current a quiescent efficiency, current FOM of1 ,350 and µA FOM and2. a supply voltage of 3.9 to 10 V, our proposed linear regulator including bandgap and protection circuits delivered voltage of 3.9 to 10 V, our proposed linear regulator including bandgap and protection circuits a maximumdelivered a current maximum of 500 current mA. of The 500 proposed mA. The proposedlinear regulator linear regulator without without voltage voltageripples ripplesachieved 1 2 competitiveachieved competitive load regulation, load regulation, line regulation, line regulation, current effi currentciency, effiFOMciency,, and FOMFOM1, and. FOM2.

2.5V 2.495V 95mV 2.5V 2.5V 60mV 400mA 100mA 2.5V 2.495V 95mV 2.5V 2.5V 60mV 0mA 400mA 0mA 100mA 0mA 0mA (a) (b)

Figure 13. Measured transient load performance of the proposed linear regulator with supply voltage of 4 V. (a) Load current(a) step is from 0 to 400 mA; (b) load current step is from(b 0) to 100 mA.

Figure 13. Measured transient load performance of the proposed linear regulator with supply voltage Figure 13. Measured transient load performance of the proposed linear regulator with supply voltage ofof 4 V.4 V (a.) (a Load) Load current current step step is is from from 0 0 to to 400 400 mA; mA; ((bb)) loadload current step is is from from 0 0 to to 100 100 mA. mA.

ElectronicsElectronics 20192019,, 88,, x 1143 FOR PEER REVIEW 1212 of of 14 14

2.5V 2.49V 110mV 2.5V 80mV 450mA 200mA 0mA 0mA

(a) (b)

Figure 14. Measured load transient performance of the proposed linear regulator with supply voltage Figure 14. Measured load transient performance of the proposed linear regulator with supply voltage of 6 V. (a) Load current step is from 0 to 450 mA; (b) load current step is from 0 to 200 mA. of 6 V. (a) Load current step is from 0 to 450 mA; (b) load current step is from 0 to 200 mA. Table 3. Performance summary and comparisons of other studies. Table 3. Performance summary and comparisons of other studies. Research. Ref. [3] Ref. [6] Ref. [12] Ref. [13] Ref. [15] Ref. [22] This Work InputResearch voltage. Ref. [3] Ref. [6] Ref. [12] Ref. [13] Ref. [15] Ref. [22] This Work 6–18 1.4–1.8 1.8–2.2 4–40 3.5–24 1.2–1.8 3.9–10 Inputrange voltage Vin (V) 6–18 1.4–1.8 1.8–2.2 4–40 3.5–24 1.2–1.8 3.9–10 Typical output range Vin (V) 1.8–3.3 1.2 1.6 2.5–5 3 1.0 2.5 voltage Vout (V) Typical output Dropout voltage 1.8–3.3 1.2 1.6 2.5–5 3 1.0 2.5 - 200 200 >200 >200 200 >200 voltage(mV) Vout (V) DropoutQuiescent voltage 350 (Including BGR, -- 1.6–200200 71–101200 >200 8 >200 3.7 135.1200 >200 current(mV) (µ A) OCP and OTP) Load Regulation 350 - 0.1 - 5.3 0.067 0.075 0.0328 @ (0-450 mA) Quiescent(mV/mA) current (Including Line Regulation - 1.6–200 71–101 8 3.7 135.1 (μA) - 5.5 131 10 0.88 @ 5 V 22.7 0.2 @BGR, (5–10 OCP V) (mV/V) and OTP) Max. load Load Regulation 450 50 100 30 150 1000.0328 500 @ (0- current (mA) - 0.1 - 5.3 0.067 0.075 (mV/mA)Current 450 mA) - 99.6 99.9 99.9 99.9 99.8 99.9 LineEffi Regulationciency (%) 0.2 @ (5–10 - 5.5 131 10 0.88 @ 5 V 22.7 FOM(mV/V)1 (ns) - 1.92 0.21 0.182 0.592 0.439 3.388V) Max. FOMload2 (ns)current - 10.56 27.51 1.82 0.521 0.935 0.6776 450 50 100 30 150 100 500 (mA) DC–DC Two-module linear Topology LDO LDO HV-LDO HV-LDO LDO Current converter+LDO regulator - 99.6 99.9 99.9 99.9 99.8 99.9 EfficiencySystem ripple (%) 10 mV no no no no no no 1 0.6 µm CMOS FOM (ns) 0.35 µm- HV 0.181.92µm 0.180.21µm 0.182 0.350.592µm 0.18 µ0.439m 0.25 µm CMOS3.388 with Technology with DMOS 2 CMOS CMOS CMOS Bi-CMOS CMOS DMOS device FOM (ns) - 10.56 27.51 device1.82 0.521 0.935 0.6776 DC–DC 0.7912 1.67Two (including-module 6.4 (including 0.3 (including Chip area (mm2) 0.0285 0.033 (including 0.024 pads, BGR, OCP Topology BGRconverter+ and pads) LDO LDO HVpads)-LDO HV-LDO LDO linear LDO BGR pads) andregulator OTP) SystemCMOS—complementary ripple 10 mVmetal-oxide no semiconductor;no FOM—figureno ofno merit; HV-LDO—high-voltage,no no low-dropout regulator. 0.6 µm 0.25 µm 0.35 µm 0.18 CMOS 0.18 µm 0.35 µm Bi- 0.18 µm CMOS with 5. ConclusionsTechnology HV µm with CMOS CMOS CMOS DMOS CMOS CMOS DMOS We designed a linear regulator for battery systems; the input voltage ranged from 3.9device to 10 V, and the maximum load current was 500 mA. The regulatordevice featured a preregulator and a linear regulator 1.67 core for minimizing power6.4 dissipation and maximizing operation stability. The error amplifiers with 0.3 0.7912 (including the Miller compensation(including technique were adopted to ensure the stability of both the preregulator and Chip area (mm2) 0.0285 0.033 (includin (including 0.024 pads, BGR, BGR and µ the linear regulator core circuit. The circuit was implementedg pads) inBGR a 0.25pads) m 5 V CMOS processOCP and with pads) 2 20 V DMOS devices, and the total silicon area was 1.67 mm . The linear regulator was able toOTP) afford a stableCMOS output—complementary voltage of 2.5metal V- underoxide semiconductor; a maximum load FOM current—figure of of 500 merit; mA HV over-LDO a supply—high-voltage, voltage low range- dropout regulator;

Electronics 2019, 8, 1143 13 of 14 of 3.9–10 V. Measurements showed that a load regulation of 0.0328 mV/mA and a line regulation of 0.2 mV/V were obtained. FOM1 and FOM2 were 3.388 and 0.6776 ns, respectively.

Author Contributions: Conceptualization, S.H.; Formal analysis, Q.D.; Funding acquisition, Q.D., Y.D. and K.S.; Investigation, W.L.; Project administration, S.H.; Software, Z.M.; Supervision, Y.D.; Writing – original draft, Q.D.; Writing – review & editing, S.H. Funding: This research was supported in part by National Natural Science Foundation of China under Grant (61904124 and 61702369) and was supported in part by the Tianjin Municipal Science and Technology Commission under Grant (18JCQNJC70700 and 15JCQNJC00500). Conflicts of Interest: The authors declare no conflicts of interest.

References

1. Affanni, A.; Bellini, A.; Franceshini, G.; Guglielmi, P.; Tassoni, C. Battery choice and management for new-generation electric vehicles. IEEE Trans. Ind. Electron. 2005, 52, 1343–1349. [CrossRef] 2. AS1117 Datasheet, ALPHA Semiconductor Excellence in Analog Power Products. Available online: https://www.alldatasheet.com/view.jsp?Searchword=AS1117R-3-3/TR (accessed on 6 July 2019). 3. Avalur, K.K.G.; Azeemuddin, S. A 6–18 V hybrid power management IC with adaptive dropout for improved

system efficiency up to 150 ◦C. IEEE J. Emerg. Sel. Top. Power Electron. 2018, 6, 477–484. [CrossRef] 4. Shen, Z.H.; Min, H. Combination method of DC-DC converter and LDO to improve efficiency and load regulation. Electron. Lett. 2011, 47, 615–617. [CrossRef] 5. Yodwong, B.; Guilbert, D.; Kaewmanee, W.; Phattanasak, M. Energy efficiency based control strategy of a three-level interleaved DC-DC supplying a proton exchange membrane electrolyzer. Electronics 2019, 8, 933. [CrossRef] 6. Maity, A.; Patra, A. A hybrid-mode operational transconductance amplifier for an adaptively biased low dropout regulator. IEEE Trans. Power Electron. 2017, 32, 1245–1254. [CrossRef] 7. Javed, K.; Yeo, J.; Lee, J.; Roh, J. Fast-transient DC-DC converter using a high-performance error amplifier with a rapid output-voltage control technique. Int. J. Circuit Theory Appl. 2017, 45, 1431–1438. [CrossRef] 8. Saberkari, A.; Qaraqanabadi, F.; Shirmohammadli, V.; Martnez, H.; Alarcon, E. Output capacitorless segmented low dropout voltage regulator with controlled pass transistors. Int. J. Circuit Theory Appl. 2016, 44, 460–475. [CrossRef] 9. Tang, J.; Lee, J.; Roh, J. Low-power fast-transient capacitor-less LDO regulator with high slew-rate class-AB amplifier. IEEE Trans. Circuits Syst. Express Briefs 2019, 66, 462–466. [CrossRef] 10. Vaisband, I.; Friedman, E.G. Stability of distributed power delivery systems with multiple parallel on-chip LDO regulators. IEEE Trans. Power Electron. 2016, 31, 5625–5634. [CrossRef] 11. Rincon-Mora, G.A.; Allen, P.E. A low-voltage, low quiescent current, low drop-out regulator. IEEE J. Solid-State Circuits 1998, 33, 36–44. [CrossRef] 12. Yun, S.J.; Kim, J.S.; Kim, Y.S. Capless LDO Regulator Achieving -76 dB PSR and 96.3 fs FOM. IEEE Trans. Circuits Syst. Express Briefs 2017, 64, 1147–1151. [CrossRef] 13. Du, H.; Lai, X.; Chi, Y. A high voltage LDO with dynamic compensation network. Analog Integr. Circuit Signal Process. 2014, 80, 233–241. [CrossRef] 14. Liu, Z.; Jin, X.; Jin, N.; He, Y.; Cheng, Y. Design of wide power supply, high performance voltage regulator with BCD process. In Proceedings of the 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai, China, 22–24 September 2010. 15. Yang, X. A low-quiescent current low-dropout regulator with wide input range. Int. J. Electron. Electr. Eng. 2015, 3, 182–186. [CrossRef] 16. Razavi, B. Design of Analog CMOS Integrated Circuits; Mc Graw-Hill: New York, NY, USA, 2005. 17. Andreou, M.; Koudounas, S.; Georgiou, J. A novel wide-temperature-range, 3.9-ppm/°C CMOS bandgap reference circuit. IEEE J. Solid-State Circuits 2012, 45, 574–581. [CrossRef] 18. Ivanov, V.V.; Filanovsky, I.M. Operational Amplifier Speed and Accuracy Improvement: Analog Circuit Design with Structural Methodology; Springer Science & Business Media: Berlin, Germany, 2006. 19. Liang, Y.; Zhu, Z. A 0.6 V 31 nW 25 ppm/°C MOSFET-only sub-threshold voltage reference. Microelectron. J. 2017, 66, 25–30. [CrossRef] Electronics 2019, 8, 1143 14 of 14

20. Huang, S.; Duan, Q.; Guo, T.; Cheng, Y.; Yin, J.; Ding, Y. A 300 mA load CMOS low-dropout regulator without an external capacitor for SOC and embedded applications. Int. J. Circuit Theory Appl. 2017, 45, 2281–2289. [CrossRef] 21. Leung, N.; Mok, P.K.T. A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation. IEEE J. Solid-State Circuits 2003, 38, 1691–1702. [CrossRef] 22. Ho, M.; Guo, J.; Mak, K.; Goh, W.; Bu, S.; Zheng, Y.; Tang, X.; Leung, K. A CMOS low-dropout regulator with dominant-pole substitution. IEEE Trans. Power Electron. 2016, 31, 6362–6371. [CrossRef]

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).