Power Supply Solutions for Modern Fpgas Master Thesis

Power Supply Solutions for Modern FPGAs

Master Thesis

Presented in Fulfillment of the Requirements for the Degree of Master of Science in the Graduate School of The Ohio State University

Amal Hassan, B.S.

Graduate Program in Electrical and Computer Engineering

The Ohio State University

2012

Master Thesis Committee:

Professor Joanne Degroat

Professor Yuan Zheng

Abstract

Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signal processing, medical imaging, and high-performance computing. This thesis outlines the issues related to powering FPGAs.

Supplying and conditioning power are the most fundamental functions of an electrical system. A loading application, be it an FPGA, cannot sustain itself without energy, and cannot fully perform its functions without a stable supply. The fact is transformers, generators, batteries, and other offline supplies incur substantial voltage and current variations across time and over a wide range of operating conditions. They are normally noisy and jittery not only because of their inherent nature but also because high power switching circuits like central processing units (CPUs) and digital signal processing (DSP) circuits usually load it. These rapidly changing loads cause transient excursions in the supposedly noise free supply, the end results of which are undesired voltage droops and frequency spurs where only a dc component should exist. The main component of a power supply is a voltage regulator. The role of the voltage regulator is to convert these unpredictable and noisy supplies to stable, constant, accurate, and load independent voltages, attenuating these ill fated fluctuations to lower and more acceptable levels. Linear or switching regulators based power supplies will be proposed and simulated.

Today’s FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, power-on, and soft start requirements can result in unreliable power-up or potential damage to FPGAs.

Acknowledgement

First and foremost, I would like to thank my advisor Professor Degroat for all her help to accomplish this goal. I am grateful for her abundant help and her prolific suggestions.

Secondly, I would like to thank the personnel of the office of financial aid for providing me with the loans, the office of Electrical and Computer Engineering for a helpful orientation during both my master and bachelor, and finally the office of Graduate School of assisting me in the various class additions.

Finally, I would like to thank myself for a successful education at Ohio State University while being treated with bipolar disorder. In addition, coming back to college after a long interruption and succeeding so well in spite of the illness was an achievement for me.

Table of Contents Abstract ...... i Acknowledgement ...... ii The List of Figures ...... v The List of Tables ...... vii Declaration ...... viii I- Introduction ...... 1 II- Linear versus Switching Regulators ...... 3 III- FPGA Overview ...... 6 IV- Requirements of modern FPGAs...... 7 a. Output Voltage Requirements ...... 7 i. Output Capacitance and Transient Considerations ...... 8 ii. Transient Response Optimizations ...... 9 iii. AUX Voltage Considerations ...... 9 b. Sequencing Requirements ...... 9 c. Startup / Power-on Requirements ...... 11 d. Soft-start Requirements...... 13 e. Synchronizing to an External Clock Requirements ...... 14 f. Multiphase Operation Requirements ...... 14 g. Remote Sensing Requirements ...... 15 V- Power Supply Examples ...... 16 a. Description of the first design based on a switch regulator LM20333: ...... 16 i. Schematic overview: ...... 16 ii. Design description: ...... 17 b. Description of the second design based on a switch regulator LM22677: ...... 28 i. Schematic overview: ...... 28 ii. Design description: ...... 28 iii

c. Description of the third design based on a linear regulator LP2951: ...... 37 i. Schematic overview: ...... 37 ii. Design description: ...... 38 d. Design of the digital control with DS1809 and Launchpad: ...... 42 VI- Conclusion ...... 46 VII- References ...... 48 Appendix A: Design Report for Design 1 ...... 49 Appendix B: Design Report for Design 2 ...... 52 Appendix C: Launchpad C Program ...... 55

The List of Figures

Figure 1: Linear Regulator Functional Diagram………………………………………………………………………….3 Figure 2: Switching Regulator Functional Diagram…………………………………………………………………….4 Figure 3: Nonisolated DC–DC Converters………………………………………………………………………………….5 Figure 4: A typical FPGA application block diagram………………………………………………………………….6 Figure 5: Simplified Buck Converter Schematic……………………………………………………………………….10 Figure 6: Startup voltage tracking……………………………………………………………………………………………..10 Figure 7: Typical voltage tracking configuration………………………………………………………………………11 Figure 8: Pre-biased startup of the LM3743………………………………………………………………………………12 Figure 9: Multiphase regulator block diagram…………………………………………………………………………..15 Figure 10: Remote-sensing block diagram…………………………………………………………………………………15 Figure 11: Power supply design 1……………………………………………………………………………………………..16 Figure 12: Duty cycle and Efficiency plots……………………………………………………………………………….18 Figure 13: Temperature and Frequency chart……………………………………………………………………………22 Figure 14: Power dissipation and Efficiency charts……………………………………………………………………23 Figure 15: Startup simulation…………………………………………………………………………………………………….24 Figure 16: Steady State chart…………………………………………………………………………………………………….25 Figure 17: Buck DC-DC converter schematic……………………………………………………………………………25 Figure 18: Gain and phase chart………………………………………………………………………………………………..26 Figure 19: Load transient response……………………………………………………………………………………………27 Figure 20: Power supply design 2……………………………………………………………………………………………..28

Figure 21: Duty Cycle and Efficiency versus IOUT……………………………………………………………………..29 Figure 22: Temperature, Efficiency and Power Dissipated………………………………………………………..30 Figure 23: Startup time……………………………………………………………………………………………………………..31 Figure 24: Switching Frequency versus RT/SYNC Resistance…………………………………………………32 Figure 25: Bode plot simulation………………………………………………………………………………………………..35 Figure 26: Steady state of the circuit…………………………………………………………………………………………36 Figure 27: Load transient of the circuit……………………………………………………………………………………..37 Figure 28: Third design of a power supply………………………………………………………………………………..38 Figure 29: Simulation voltage from 1.8V to 5V…………………………………………………………………………40 Figure 30: LDO based power supply breadboard simulation……………………………………………………..41 Figure 31: Output noise of the LDO………………………………………………………………………………………….42 Figure 32: Block diagram of a DS1809 digital potentiometer……………………………………………………43 Figure 33: Feedback digitally controlled for variable voltage……………………………………………………44 v

Figure 34: Single pulse input…………………………………………………………………………………………………….44 Figure 35: Launchpad microcontroller……………………………………………………………………………………..45

The List of Tables

Table 1: Voltage Requirements for Common Modern FPGAs……...…….……………7

Table 2: Required Startup/Soft-start Times…………………………….……………….13

Table 3: Suggested Values for RFB1 and RFB2………………………….………………..19

vii

“Productivity is never an accident. It is always the result of a commitment to excellence, intelligent planning, and focused effort.” Paul J. Meyer American entrepreneur and author

Declaration Herewith I affirm that I have written this thesis on my own. I did not enlist unlawful assistance of someone else. Cited sources of literature are perceptibly marked and listed at the end of this thesis. The work was not submitted previously in same or similar form to another examination committee and was not yet published.

Ohio, June 2012

viii

I- Introduction

Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, and they have been gaining market share over ASICs due to their excellent design flexibility and low engineering costs. Power-supply design and management for FPGAs is an important part of the overall application.

By their nature, FPGAs are power hungry devices with complex power delivery requirements and multiple voltage rails. A single chip commonly consumes multiple watts of power while operating from 1.8 V, 2.5 V and 3.3 V rails. Activating high speed on-chip SERDES can increase power consumption by several watts and complicate the power delivery strategy. When FPGA power consumption increases, performance requirements on sensitive analog and mixed-signal subsystems also increase. Chief among these are the clocking subsystems that provide low jitter timing references for the FPGA and other board-level components.

Power hungry systems cannot be free of power supply noise. In general, system designers try to use low noise linear power supplies whenever possible. However, excessive power dissipation usually prevents the use of linear regulators. When using a linear device, regulating from 3.3 V input to 1.8 V output is only 54% efficient regardless of the load current. Low conversion efficiency burns power in the regulator instead of the load and makes linear devices unsuitable for many high performance applications. A more practical way to increase efficiency and maintain regulation over a wide load current range is with the use of switching regulators. The high 85 to 95 % efficiency of switching regulators often makes them the only power conversion alternative for FPGAs.

The aim of this thesis is to design a variable power supply that powers a FPGA. The power supply will deliver a variable voltage which varies by 50mV steps up and

down. The variation of the voltage will be regulated by a digital potentiometer which will be commanded by a microcontroller. The proposed designs should consider the output voltage, sequencing, power-on, and soft start requirements. Designing a power supply with a high efficiency and low noise dissipation is the goal of this thesis. This thesis’s report discusses ways to overcome some of the power supply design challenges and explains the trade-offs between cost, size, and efficiency.

II- Linear versus Switching Regulators

A voltage regulator is normally a buffered reference: a bias voltage cascaded with a noninverting op-amp capable of driving large load currents in shunt-feedback configuration. Bearing in mind the broad range of load currents possible, regulators are, on a basic level, generally classified as linear or switching.

Linear regulators, also called series regulators, linearly modulate the conductance of a series pass switch connected between an input dc supply and the regulated output to ensure the output voltage is a predetermined ratio of its bias reference voltage, as illustrated in Figure 1. The term “series” refers to the pass element (or switch device) that is in series with the unregulated supply and the load. Since the current flow and its control are continuous in time, the circuit is linear and analog in nature, and because it can only supply power through a linearly controlled series switch, its output voltage cannot exceed its unregulated input supply (i.e., VOUT < VIN).

Figure 1: Linear Regulator Functional Diagram A switching regulator is the counterpart to the linear solution, and because of its switching nature, it can accommodate both alternating current (ac) and direct-current (dc)

input and output voltages, which is why it can support ac-ac, ac-dc, dc-ac, and dc-dc converter functions. Within the context of ICs, however, dc-dc converters predominate because the ICs derive power from available dc batteries and off-line ac-dc converters, and most loading applications in the IC and outside of it demand dc supplies to operate. Nevertheless, given its ac-dc converting capabilities, switching regulators are also termed switching converters, even if only dc-dc functions are performed (Figure 2).

Figure 2: Switching Regulator Functional Diagram The inverter configurations used in today’s switchers actually evolved from the buck and boost circuits shown in Figures 3a and 3b. In each case the regulating means and loop analysis will remain the same but a transformer is added in order to provide electrical isolation between the line and load. The forward converter family which includes the push–pull and half bridge circuits evolved from the buck regulator (Figure 3a). And the newest switcher, the flyback converter, actually evolved from the boost regulator. The buck circuit interrupts the line and provides a variable pulse width square wave to a simple averaging LC filter. In this case, the first order approximation of the output voltage is

Vout = Vin × duty cycle and regulation is accomplished by simply varying the duty cycle. This is satisfactory for most analysis work and only the transformer turns ratio will

have to be adjusted slightly to compensate for IR drops, diode drops, and transistor saturation voltages. Operation of the boost circuit is more subtle in that it first stores energy in a choke and then delivers this energy plus the input line to the load. However, the flyback regulators which evolved from this configuration deliver only the energy stored in the choke to the load. This method of operation is actually based on the buck boost model shown in Figure 3c. Here, when the switch is opened, only the stored inductive energy is delivered to the load.

Figure 3: Nonisolated DC–DC Converters In the following section, we will study the power supply designs requirements of FPGAs.

III- FPGA Overview

FPGAs are programmable devices consisting of an array of configurable logic blocks (CLBs) connected through programmable interconnects. These CLBs typically comprise various digital logic components, such as lookup tables, flip flops, multiplexers, etc. Other components of an FPGA include input/output pin driver circuits (I/Os), memory, and digital clock management (DCM) circuits. Modern FPGAs integrate features that include FIFO and error correction code (ECC) logic, DSP blocks, PCI Express controllers, Ethernet MAC blocks, and high-speed gigabit transceivers (Figure 4).

Figure 4: A typical FPGA application block diagram

IV- Requirements of modern FPGAs

a. Output Voltage Requirements

The first criteria to consider when designing power supplies for FPGAs are the voltage requirements for the different supply rails. Most FPGAs have specifications for the CORE and IO voltage rails and many require additional auxiliary rails that may power internal clocks, phase-lock loops or transceivers. Table 1 provides the voltage levels and tolerances for some of the newest FPGAs.

Table 1: Voltage Requirements for Common Modern FPGAs

* Some values may differ slightly from those listed. Please consult your FPGA’s associated documentation for details.

Since FPGAs generally specify several permissible voltage levels for the IO, the voltage selected is dictated by the external digital circuitry. To provide flexibility, FPGAs will generally provide multiple IO banks that can be powered separately, allowing FPGAs to interface with various logic families. For simplicity, the solutions illustrated in this report

will assume all IO banks are powered off of a single power supply rail. The core voltage supplies the internal logic configuration blocks of FPGAs and is where many of the internal digital path processes occur. As such, the current demanded by the core will vary greatly depending on the percent utilization of FPGAs. Vendors of the FPGAs described herein provide design tools that estimate core current requirements based on the internal blocks utilized. Overtime, the voltages used to power the core have steadily dropped. Modern cores utilize 65 nm, 45 nm or even 40 nm geometry silicon processes and may operate from voltages as low as 0.9V. These lower voltages are valuable to reduce power dissipation in FPGAs. The trade off, however, is that keeping within the voltage tolerance requirements becomes more challenging for the power supply designer.

i. Output Capacitance and Transient Considerations

A good power supply design will keep the core voltage within tolerance at all times. Most of the power supply transient concerns can be managed by properly selecting the bypass and bulk capacitances for the power supply. In general, every core ball or pin connection should be bypassed directly under FPGAs with high-quality X5R or X7R ceramic capacitors. The values recommended for each of these capacitors range from 1μF to 10μF and will generally be specified by FPGA manufacturers. These capacitors provide a charge when FPGAs need to rapidly draw large spikes of current during high speed operations. Likewise, the bulk capacitance should be selected to provide charge during large steps of current, which tend to occur during power-on, application-start, or a change in application state. Before increasing the amount of output capacitance to solve transient droop issues, changes to the power supply should be made that do not involve an increase in PCB area or component count. The response to a load transient is dictated by the large signal response time that consists of ramping the inductor current to the correct operating level and the small signal response of the control loop.

ii. Transient Response Optimizations

To optimize the transient response, ensure the supply is switching at the highest possible frequency. This will allow use of a small inductor and reduce the large signal response time. Typical high performance power supply solutions can be designed to have crossover frequencies as high as one-tenth to one-fifth the switching frequency. Pushing the crossover frequency too high may result in ringing at the output during a load transient indicating poor phase margin. Any ringing in the output should be avoided as this may result in instability with external component variation or when operating at temperature extremes.

iii. AUX Voltage Considerations

Many FPGAs require a third power supply commonly referred to as the auxiliary rail or AUX. Since the AUX rail may power internal clocks, phase-lock loops, or transceivers, the amount of output voltage ripple on this rail should be minimized. In some cases, additional ferrite beads and capacitors filtering may be needed to meet the application or FPGA noise requirements. In applications where noise is extremely important, a low noise, high power supply ripple rejection (PSRR) low-dropout (LDO) regulator, like the LP3878, should be considered instead of a switching converter.

b. Sequencing Requirements

The sequencing requirements vary depending on the particular FPGA being used and many newer FPGAs specify that no sequencing is required. While this is technically true for the FPGA, it is not the optimal way to design a power solution. The LM3880, offered by National Semiconductor, is designed to address sequential sequencing of multiple supply rails. This device is available in a small SOT-23 package and can sequence up to 9

three supply rails. Many options are available to control the up and down, three flag outputs sequencing timing. National also provides devices to support customized flag order and timing. Figure 5 illustrates a typical application circuit for the LM3880.

Figure 5: Simplified Buck Converter Schematic Voltage tracking is another method of sequencing power supplies applicable to FPGAs and many processors. The most common and generally recommended method to power up FPGAs and other processors is to have the CORE voltage track the I/O voltage during startup as shown in Figure 6.

Figure 6: Startup voltage tracking 10

This power-up technique is known as simultaneous startup, and its primary advantage is that it avoids turning on any parasitic conduction paths that may exist between the CORE and IO supply rails. Turning on a parasitic conduction path may lead to unreliable startup or even damage to FPGAs or DSPs. Some of National Semiconductor’s devices that feature voltage tracking include the LMZ14203 and LMZ10504 SIMPLE SWITCHER Power Modules, the LM20k family of high performance synchronous DC/DC converters, as well as the LM3743 controller. Figure7 illustrates a typical voltage tracking configuration for these devices.

Figure 7: Typical voltage tracking configuration

c. Startup / Power-on Requirements

When sequential sequencing is used in systems with multiple voltage rails, as is the case with many FPGA solutions, it is likely that an output of one of the power supplies could be pre-biased through various parasitic conduction paths. In this situation, how the power supply handles this pre-biased state can have an impact on long term system

reliability, or even the ability of the power supply or FPGAs to start successfully. To avoid the pitfalls associated with a pre-biased startup, the power supply should not pull the output low if a pre-biased condition exists. Figure 8 illustrates how a pre-biased condition should be handled when the output is pre-biased to three different voltage levels. All power solutions featured in this report are capable of properly handling a pre- biased start up. Power supplies used to power both the CORE and IO must be monotonic during power-on to avoid FPGA startup problems. A monotonic startup continuously increases until the output reaches the final value.

Figure 8: Pre-biased startup of the LM3743 The critical area for monitonicity for most modern core voltage rails occurs between 0.5V to 0.9V. This is when FPGAs initialize the internal logic blocks to valid operating states.

d. Soft-start Requirements

Using soft-start is highly recommended, even if not specified by the FPGA manufacturer. Slowly ramping the input voltage reduces the inrush currents seen in some FPGAs. Using soft-start also reduces the current needed to charge the output capacitance of the power supply and will decrease the voltage droop on the input bus during startup. The startup or soft-start requirements for several FPGAs are summarized in Table 2.

Table 2: Required Startup/Soft-start Times

A startup time of 10 ms generally limits the capacitive inrush currents to an acceptable level while meeting the requirements for most FPGAs and DSPs.

e. Synchronizing to an External Clock Requirements

FPGAs applications usually require the power regulators to synchronize to a common clock. Many “point-of-load” regulators (POLs) provide an external SYNC pin to allow the system designer to synchronize one or multiple regulators to a common system clock.

f. Multiphase Operation Requirements

Multiphase regulators are essentially multiple regulators operating in parallel with their switching frequencies synchronized and phase shifted by 360/n degrees, where n identifies each phase. The advantages of designing with multiphase regulators (Figure 9) become apparent as load currents rise above 20A to 30A. These advantages include:

1. A reduced input-ripple current, thus significantly decreasing the required input capacitance. 2. A reduced output-ripple voltage due to an effective multiplication of the ripple frequency. 3. A reduced component temperature, achieved by distributing the losses over more components.

Figure 9: Multiphase regulator block diagram

g. Remote Sensing Requirements

There can be a significant voltage drop between the power-supply output and the FPGA power-supply pins. This occurs particularly in applications where the load current is high and it is not possible to place the regulator circuit very close to the FPGA power pins. Remote sensing resolves this issue by using a dedicated pair of traces to accurately measure the voltage at the FPGA's power-supply pins (Figure 10). Remote sensing is also recommended for voltage rails with very tight tolerances (≤ 3%).

Figure 10: Remote-sensing block diagram 15

V- Power Supply Examples

During this section, we will design three power supplies. Two designs switching regulators based using WEBENCH, a web based power design software from Texas Instruments, and a LDO based one using Pspice will be discussed. All three designs’ simulations will be described and their efficiency will be compared to choose the best design.

a. Description of the first design based on a switch regulator LM20333:

i. Schematic overview:

The first design proposed is a LM20333 switch regulator based power supply. The schematic generated by WEBENCH is found in the Figure 11.

Figure 11: Power supply design 1 16

ii. Design description:

This section walks the reader through the process of designing this power supply and how the choice of the components has been made. The first equation to calculate for any buck converter is duty cycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated by:

(1)

The figure below (Figure 12) shows the duty cycle as well as the efficiency of this circuit. To calculate the efficiency, the formula below can be used:

η = PLOAD / PTOTAL = PLOAD / (PLOAD+PD) (2)

Figure 12: Duty cycle and Efficiency plots

As VOUT increases, the duty cycle rises. At the opposite, as the power dissipated increases, the efficiency decreases ending at 91% at IOUT equal to 3A

Next, the value of L1 is calculated using the following formula:

(3)

The inductor value is determined based on the operating frequency, load current, ripple current and duty cycle. Using the values in the appendix A, the value of L1 is calculated as follows:

L1min = ((6 - 5) x 0.90251) / (889.883 x 200) = 5.1µH

To optimize the performance and the stability of the control loop, the value of L1 is

10µH. The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. Good quality input capacitor is necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as it provides both a low impedance and small footprint. The input capacitor CIN should be placed as close as possible to the VIN and GND pins on both sides of the device. To set output voltage, the resistors RFB1 and RFB2 are selected to set the output voltage for the device. Table 3 provides suggestions for RFB1 and RFB2, and for common output voltages.

Table 3: Suggested Values for RFB1 and RFB2

If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to

49.9 kΩ and RFB1 can be calculated using the equation below:

(4)

RC1 and CC1 form the loop compensation entity in the circuit. The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining

adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load and the device itself. To calculate the values of the two components, the loop transfer function should be analyzed to optimize the loop compensation. The overall loop transfer function is the product of the power stage and the feedback network transfer functions. A good starting value for CC1 for most applications is 3 nF. Once the value of

CC1 is chosen the value of RC should be approximated using the equation below:

(5)

The LM20333 integrates an N-channel buck switch and associated floating high voltage level shift / gate driver. This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1μF ceramic capacitor CBOOT, connected with short traces between the BOOT pin and SW pin, is recommended. During the off- time of the buck switch, the SW pin voltage is approximately 0V and the bootstrap capacitor is charged from VCC through the internal bootstrap diode. The capacitor at the

VCC pin provides noise filtering for the internal sub-regulator. The recommended value of Cext should be no smaller than 0.1μF and no greater than 1μF. In our design, it is 1μF. The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will reach the final regulated value. Larger values for CSS will result in longer startup times. In our case, CSS equals 7nF and the startup engendered is 1ms. The equation below is used to calculate the startup:

(6)

As shown above, the startup time is influenced by the value of the soft-start capacitor CSS and the 4.5μA soft-start pin current ISS. Finally, the thermal characteristics of the 20

LM20333 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependent on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship:

(7) and

(8)

Where : TJ is the junction temperature in °C. PIN is the input power in Watts (PIN = VIN x

IIN). θJA is the junction to ambient thermal resistance for the LM20333. TA is the ambient temperature in °C. IOUT is the output load current. DCR is the inductor series resistance. It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the junction temperature exceeds 170°C the device will cycle in and out of thermal shutdown. If thermal shutdown occurs it is a sign of inadequate heat sinking or excessive power dissipation in the device. The following figure (Figure 13) is showing the TJ and fSW in versus the output voltage VOUT.

Figure 13: Temperature and Frequency chart

The temperature starts at 69.75°C for VOUT=0V and ends at 69.65°C for VOUT=5V. The temperature is max at 3V and 1V at 69.75. At those two voltages, the power dissipated is maximum as shown in the figure (Figure 14) below along with the footprint and the efficiency. The higher the power dissipated, the lower the efficiency.

Figure 14: Power dissipation and Efficiency charts

The next simulation chart (Figure 15) is showing VIN and VOUT versus time. The monotonic startup of 1ms, moment VOUT reaches 5V which is the final value, can be seen on the curve of VOUT.

Figure 15: Startup simulation

The steady state chart (Figure 16) of VIN and VOUT show a slight variation around their operation point of 6V and 5V.

Figure 16: Steady State chart Next, the stability of the circuit is studied by looking at the bode plot generated by WEBENCH. The Figure 17 shows the building block of a buck DC-DC converter. The transfer function is calculated using the formula (9) below.

Figure 17: Buck DC-DC converter schematic

(9)

By simulation with WEBENCH, we obtain the following gain and phase plot (Figure 18).

Figure 18: Gain and phase chart The cut-off frequency, frequency at -3dB, is 3KHz. A gain of -21dB at the switch frequency of 200KHz is observed. The gain curve starts and stays at zero until 50Hz, then descends @-40dB/decade until 3KHz, after that it decreases another -20dB/decade until 100KHz, to finally decrease @-40dB/decade. The transfer function can be deducted from the gain curve as follows: H(s) = 12/((1+s/50)^2(1+s/3e/3)(1+s/100e3)^2) (10)

The system is stable because the coefficients of the denominator are all positive.

As shown in appendix A, the phase margin of the circuit is around 42.8 degrees. For systems with monotonically decreasing gain, the difference, between the actual phase and 180 degrees when the gain reaches unity, is known as the phase margin. On the Bode plot in Figure 18, the phase margin is 180- 125 = 55 degrees. The difference, between the actual gain (below unity) and 0dB (unity) when the phase reaches 180 degrees, is known as the gain margin. GM is | -35dB | / 20 or 1.75. A well designed Feedback control ◦ ◦ system will have: 1.7 ≤ GM ≤ 2.0 ; 30 ≤ PM ≤ 45

Thus, our circuit is well design by WEBENCH as the phase margin of 42.8 degrees, and the gain margin of 1.75 fall into the margins. Finally, the load transient chart shown in Figure 19 will be described.

Figure 19: Load transient response

VIN is a voltage pulse which has a period of 0.6ms and amplitude that varies between a maximum of 6V and a minimum of 5.97V. VOUT curve is reflecting the charge and the 27

discharge of COUT which follows the behavior of VIN. When VIN rises, VOUT rises until

VIN stops rising and stabilizes. At that point, COUT discharges through the load as showed by VOUT. When VIN descends, VOUT decreases; COUT starts charging when VIN stabilizes again. The process repeats for the next VIN voltage pulse.

b. Description of the second design based on a switch regulator LM22677:

i. Schematic overview:

The second design proposed is a LM22677 switch regulator based power supply. The schematic generated by WEBENCH is found in the Figure 20.

Figure 20: Power supply design 2

ii. Design description:

The duty cycle, expressed previously, will be the first chart to be discussed. As seen in

Figure 21, the duty cycle rises as VOUT rises.

Figure 21: Duty Cycle and Efficiency versus IOUT The higher the value of the power dissipated, the lower the efficiency of the circuit. There is a high temperature drop in the circuit from the start until when the VOUT reaches the regulated voltage of 5V. The temperature drop of 0.7 degrees engender a higher power dissipated, thus a higher efficiency. At 5V, the efficiency of this circuit is 91.55% comparing to 91% for the first design.

Figure 22: Temperature, Efficiency and Power Dissipated The soft-start feature allows the regulator to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. The soft-start is fixed to 1.1ms (typical) start-up time (Figure 23).

Figure 23: Startup time To set and synchronize the switching frequency, there are three different modes for the RT/SYNC pin. It can be left floating for a 500 kHz switching frequency. A resistor from the RT/SYNC pin to ground can be used to adjust the switching frequency between 200 kHz and 1 MHz. An external synchronization pulse can be applied to the RT/SYNC pin for switching frequencies up to 1 MHz. The synchronizing frequency must be greater than the internal switching frequency for proper operation. In our case, the switching frequency is 250KHz giving us a resistor of 191KΩ as shown in the graph below.

Figure 24: Switching Frequency versus RT/SYNC Resistance A 0.01μF ceramic capacitor connected with short traces between the BOOT pin and the SW pin is recommended to effectively drive the internal FET switch. During the off-time of the switch, the SW voltage is approximately -0.5V and the external bootstrap capacitor is charged from the internal supply through the internal bootstrap diode. When operating with a high PWM duty-cycle, the buck switch will be forced off each cycle to ensure that the bootstrap capacitor is recharged. The inductor value is determined based on the load current, ripple current, and the minimum and maximum input voltage. To keep the application in continuous current conduction mode (CCM), the maximum ripple current,

IRIPPLE, should be less than twice the minimum load current. Using this value of ripple current, the value of inductor, L, is calculated using the following formula:

(11) 32

Increasing the inductance will generally slow down the transient response but reduce the output voltage ripple amplitude. Reducing the inductance will generally improve the transient response but increase the output voltage ripple. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during on-time. When the switch turns on, the current into the VIN pin steps to the peak value, and then drops to zero at turnoff. The average current into VIN during switch on-time is the load current. The input capacitance should be selected for RMS current,

IRMS, and minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2. The output capacitor can limit the output ripple voltage and provide a source of charge for transient loading conditions. Multiple capacitors can be placed in parallel. Very low ESR capacitors such as ceramic capacitors reduce the output ripple voltage and noise spikes, while higher value capacitors in parallel provide large bulk capacitance for transient loading and unloading. The bootstrap capacitor between the BOOT pin and the SW pin supplies the gate current to turn on the N-channel MOSFET. The recommended value of this capacitor is 10 nF and should be a good quality, low ESR ceramic capacitor. The resistor divider has two options: 5.0 V and

ADJ. The two resistors RFB1 and RFB2 form the resistor divider system. For the -ADJ option no resistor divider is required for 1.285V output voltage. The output voltage should be directly connected to the FB pin. Other output voltages can use the –ADJ option with a resistor divider. The resistor values can be determined by the following equations:

-ADJ option:

(12) 33

Where VFB = 1.285V typical for the -ADJ option.

A Schottky type re-circulating diode is required for all LM22677 applications. Ultra-fast diodes which are not Schottky diodes are not recommended and may result in damage to the IC due to reverse recovery current transients. The near ideal reverse recovery characteristics and low forward voltage drop of Schottky diodes are particularly important diode characteristics for high input voltage and low output voltage applications common to the LM22677. The reverse recovery characteristic determines how long the current surge lasts each cycle when the N-channel MOSFET is turned on. The reverse recovery characteristics of Schottky diodes minimize the peak instantaneous power in the switch occurring during turn-on for each cycle. The resulting switching losses are significantly reduced when using a Schottky diode. The reverse breakdown rating should be selected for the maximum VIN, plus some safety margin. A rule of thumb is to select a diode with the reverse voltage rating of 1.3 times the maximum input voltage. The two highest power dissipating components are the re-circulating diode and the LM22677 regulator IC. The easiest method to determine the power dissipation within the LM22677 is to measure the total conversion losses (Pin – Pout) then subtract the power losses in the Schottky diode and output inductor. An approximation for the Schottky diode loss is:

(13)

An approximation for the output inductor power is:

(14)

Where R is the DC resistance of the inductor and the 1.1 factor is an approximation for the AC losses.

Next, the Bode plot of the circuit will be discussed (Figure 25). The cut-off frequency is 300KHz. The phase margin is 106.3 degrees and the gain margin is 0.5 (appendix B). These values are out of the range acceptable for a good feedback control system.

Figure 25: Bode plot simulation The transfer function of this circuit is:

H(s) = 178/((1+s/100)(1+s/5e3)(1+s/30e3)^(1/2)) (15)

The system is stable since all its coefficients are positive.

Then, the steady state chart is shown below (Figure 26). VIN and VOUT slightly vary around their values of 6V and 4.425V.

Figure 26: Steady state of the circuit

The last chart is the load transient response (Figure 27). VOUT rises when VIN rises and drop when VIN drops. The behavior of VOUT is the same than the one of the charge and discharge of COUT.

Figure 27: Load transient of the circuit Even though the efficiency of this circuit is better than the one of the first circuit, the gain and the phase margins are out of the range of the acceptable values. Both circuits are stable. The first circuit is obviously the best design because it has a good efficiency, in- range gain and phase margins.

c. Description of the third design based on a linear regulator LP2951:

i. Schematic overview:

The third design proposed is a LP2951 linear regulator based power supply. The schematic selected from an IEEE paper and reworked is shown below in the Figure 28.

D1 2 1

1N4500

8 1 Vout VIN VOUT 5V - 1.8V 7 5 C1 2 FB ERR 6 C3 .1uF 3 SENSE VTAP C2 R1 10uF V1 SHDN 0.01uF 50k 9Vdc

LP2951 1 D2 1N4500

Rh Vdd STR 2 C4 V2 10uF 5Vdc Rw UC Q1 Rdcp NPN_BCE Rl DC GND Q2 P1.0 - LED1

DS1809 NPN_BCE R2 P1.6 - LED2 20k 100k

Microcontrolller Launchpad

Figure 28: Third design of a power supply

ii. Design description:

This section will describe the above design. The circuit of the programmable precise low dropout regulator constituted by DS1809 and the low dropout regulator LP2951 is shown in Figure 28. DS1809 belongs to the sixty-four taps key-press mode nonvolatile digitally controlled potentiometer. LP2951 is the low dropout regulator protruded by America SIPEX Corporation, its output voltage is +5V, and its rated output current is 100mA, at fractional load time the pressure difference is only 50mV. The output end of the programmable precise low dropout regulator connects with a 9V battery. The output voltage VOUT = +1.8~5V, regulation range is 3.2V. The 3.2V is divided into sixty-four shares by the DS1809. And the stepping quantity is 50mV. The total resistance value of

DS1809 has three specifications. They are 10kΩ, 50kΩ and 100kΩ. R1 and R2 are the divider resistors; they together with the output resistance RDCP of DS1809 constitute the bleeder. The output end of the bleeder connects the feedback end (FB) of LP2951, setting up the resistance value of RDCP through the key-press is able to regulate the VOUT value precisely in the specialized range. At normal working, VOUT charges toward C4 through D2. At dump time, using the voltage supplied by the double end of C4 can realize that the DS1809 has enough time to memory the sliding end position. D2 adopts the Schottky Diode. The sliding end of DS1809 (RW) and the high end (RH) is shorted out mutually, and used as an adjustable resistor. The Q1 and Q2 are NPN transistors connected to a microcontroller Launchpad. When P1.0 is high, the output resistance value of DS1809 will increase by R/64, and VOUT reduced by 50mV. The action of Q2 is opposite to the former. The expression of the output voltage is:

Vout = Vref (1 + R_1/(R_dcp + R_2)) (16)

In the formulae, the VREF is the 1.235V reference voltage, which is connected with the feedback end interior voltage comparator. Using the formulae (2) and (3), the required values of R1 and R2 can be worked out.

5 = 1.235 (1 + R_1/R_2)

1.8 = 1.235 (1 + R_1/(100x10^3+R_2)) (17)

Let’s take an example to illustrate: when the total resistance value of DS1809 R=100kΩ and the sliding end moves to the low end position (RL), RDCP = 0, VOUT = VOUTMAX = 5V.

When the sliding end moves to the high end position (RH) and RDCP = R = 100kΩ, VOUT =

VOUTMIN = 1.8V. Through the simultaneous equations formed by the formula (2) and (3), we can work out that R1 = 55kΩ and R2 = 23kΩ. In practice, we will choose the nominal resistance of R1 = 50kΩ and R2 = 20kΩ, the resistance powers are both 0.125W.

6.0V

5.0V

4.0V

3.0V

2.0V

1.0V

0V 0V 1V 2V 3V 4V 5V 6V 7V 8V 9V 10V 11V 12V ... V(Vout) V_V1 Figure 29: Simulation voltage from 1.8V to 5V

For the low dropout regulator, PD is equal to:

-3 -3 PD = ((VIN − VOUT) × IL) + (VIN × IG) = ((9-5) x 100x10 ) + (9 x 177 x 10 ) = 1.993W

η = (0.4) / (1.593 + 1.993) = 28%

The efficiency of this circuit is really low comparing to the switch regulator design. This circuit was mounted on breadboard and simulated. Figure 30 shows the pictures taken from the station. Figure 30 shows the reading of the minimum voltage of 1.81V, the intermediate voltage of 2.98V and the maximum voltage of 4.53V.

Figure 30: LDO based power supply breadboard simulation In many applications using a low dropout regulator, it is desirable to reduce the noise present at the output. Reducing the regulator bandwidth by increasing the size of the output capacitor is the only method for reducing noise on the 3 lead LP2951. However, increasing the capacitor from 1.0 µF to 220 µF only decreases the noise from 430 µV to 160 µVrms for a 100 kHz bandwidth at the 5.0 V output. Noise can be reduced fourfold by a bypass capacitor across R1, since it reduces the high frequency gain from 4 to unity.

We will determine Cbypass as the following:

C_bypass = 1( 2πR_1 +200 Hz) (18)

or about 0.01 µF. When doing this, the output capacitor must be increased to 3.3 µF to maintain stability. These changes reduce the output noise from 430 µV to 126 µVrms for a 100 kHz bandwidth at 5.0 V output. With bypass capacitor added, noise no longer scales with output voltage so that improvements are more dramatic at higher output voltages. In Figure 31, the highest the value of CL, the lower the voltage noise.

Figure 31: Output noise of the LDO d. Design of the digital control with DS1809 and Launchpad:

The DS1809 Dallastat is a digitally controlled, nonvolatile potentiometer. A block diagram of the DS1809 is shown in Figure 32. The DS1809 is a linear potentiometer providing 64-uniform wiper positions over the entire resistor range including the end- terminals. All three potentiometer terminals of the device are accessible. These terminals include RH, RL, and RW. RH and RL are the end-terminals of the potentiometer. These terminals will have a constant resistance between them as defined by the potentiometer value chosen: 10KΩ, 50KΩ, or 100KΩ version. Functionally, RH and RL are 42

interchangeable. The wiper terminal, RW, is the multiplexed terminal and can be set to one of the 64 total positions that exist on the resistor ladder including the RH and RL terminals.

Figure 32: Block diagram of a DS1809 digital potentiometer

Control of the wiper (RW) position setting is accomplished via the two inputs UC and DC. The UC and DC control inputs, when active, determine the direction on the resistor array that the wiper position will move. The UC (up control) control input is used to move the wiper position towards the RH terminal. The DC (down control) control input is used to move wiper position towards the RL terminal. The control inputs UC and DC are active low inputs that interpret input pulse widths as the means of controlling wiper movement. Internally, these inputs are pulled up to VCC via a 100KΩ resistance. Using this potentiometer with a regulator, LDO or switching, should be done as illustrated by the Figure 33.

Vout

Rf b2

Feedback Rh Vdd STR

Rw UC

Rl DC GND

Rf b1 DS1809 100k

Figure 33: Feedback digitally controlled for variable voltage A transition from a high-to-low on these inputs is considered the beginning of pulse input activity.

Figure 34: Single pulse input A single pulse (Figure 34) on the UC or DC input is defined as being greater than 1 millisecond but lasting no longer that ½ second. This type pulse input will cause the wiper position of the Dallastat to move one position.

Two NPN transistors will be connected to the UC and DC inputs. The collectors of these transistors will be connected to the ground and the emitters to UC and DC. The bases of the NPN transistors will be connected to P1.0 and P1.6 pins of the Launchpad microcontroller. These two pins are commanding a green light and a red light and are being switched using a pushbutton. A pulse of signal, which will be characterized by a led going green or red, of max 5ms high and 30ms low, will be sent to the bases of the 44

NPN transistors. When Q1 gets that signal, the emitter will go from high-Z to ground and the resistance value of DS1809 will increase by R/64, and VOUT reduced by 50mV. The action of Q2 is opposite to the former. The image of the Launchpad microcontroller is shown on Figure 35.

Figure 35: Launchpad microcontroller The Launchpad pushbutton controls the up/down movement of the voltage in the digital potentiometer. During the simulation, a slight change has been induced in the circuit. The UC and DC pins of DS1809 are connected to a three positions switch. The switch is connected to an NPN voltage that is commanded by the pin P1.6 of the Launchpad. Flipping the switch left or right increases the voltage or decreases the voltage from 1.81V to 4.53V. Appendix C contains a reworked C program that came with the product. This application runs the simulation through the Launchpad.

VI- Conclusion

The digitally controlled potentiometer is a digital to analog composite signal process integrated circuit, which is made by CMOS process technology. It possesses many outstanding advantages: using agilely, high accuracy of regulation, non-contact, low noise, difficult of defiling, vibration proof, anti-jamming, compactness, long life or permanence and so on. It can substitute the mechanical potentiometers in many realms to form different kinds of programmable linear voltage regulator, thus realizing the optimum design of the digitally controlled voltage regulators. Paired with a switching regulator, the digital potentiometer can provide a highly accurate power supply with a high efficiency. Comparing to the linear regulator, the primary advantages of the first switching regulator based power supply are efficiency, size, and weight. Only the output voltage has been studied by simulation for the linear regulator power supply. The output noise, which is one of the advantages of the LDO, has not been determined for this design by simulation. The first design is also a more complex design, cannot meet some of the performance capabilities of linear supplies which generates a small amount of electrical noise. However switchers are being accepted in the industry, particularly where size and efficiency are of prime importance. Performance continues to improve and for most applications they are usually cost competitive down to the 20 W power levels. The performance based on the efficiency of the linear regulator is low comparing to the performance of the switch regulator. The choice for the power supply is the first design with LM20333 switch regulator. Many simulations aspects have been covered with that circuit. The remaining issues will be to study the output noise of the circuit by measuring the voltage noise versus the frequency of circuit. Noise can also cause problems if the two divider resistors are placed improperly. Placing the two resistors next to the controller's FB pin ensures that a relatively noise-free voltage is fed back to the

controller. Positioning the resistors that way minimizes the length of the trace leading from the mid-point of the resistor divider to the switching regulator's FB pin - a necessity because both the resistor divider and the input of the internal comparator at the FB pin are high impedances, and thus the trace connecting them is prone to picking up (primarily through capacitive coupling) the noise that switching regulators inevitably produce. You can, however, make the trace that runs from the regulator's output to the "top" of the resistor divider and the trace that runs from the "bottom" or ground side of the resistor divider to the ground side of the output capacitor relatively long; the low output impedance of the switching regulator reduces coupled noise on those traces. Also, the circuit has to be controlled digitally as described in Figure 33 to obtain a variable voltage of 0.8V to 5V. The next step will be to buy the component and simulate the power supply on breadboard. Afterwards, a layout should be design and a PCB should be printed. The components will be soldered and the card will be ready to be used after passing a final check to see if it meets the requirements. We could use this power supply to provide the different voltages of the FPGA which are VCORE, VAUX and VIO.

VII- References

[1] Semiconductor Components Industries, LLC LP2950, LP2951, “NCV2951 100 mA Low Dropout Voltage Regulators Datasheet”. March, 2003 - Rev. 102000.2 [2] DALLAS Semiconductors, “ DS1809 Z- 100k Dallastat Datasheet”. [3] An Guochen & Sha Zhanyou, “Programmable Voltage Regulator Design based on Digitally Controlled Potentiometer”, (Hebei University of Science & Technology, Shijiazhuang Hebei 050054, China). 2007. [4] Maxim, “Controlling a Variable Voltage Power Supply Using the DS1809 (Pushbutton Control)”. Mar 28, 2002 [5] On Semiconductor, “Linear & Switching Voltage Regulator Handbook”, Rev. 4, Feb- 2002 [6] Juan Conchas, Timing Marketing Manager, Silicon Labs, “Simplifying Power Supply Design in FPGA-based Systems”

[7] Dennis Hudgins, Low Voltage Applications Manages, Tucson Design Center, “Power Supply Design Considerations for Modern FPGAs”, 2010.

[8] Texas Instruments, LM20333 Datasheet, “LM20333 36V, 3A Synchronous Buck Regulator with Frequency Synchronization”, 2011.

[9] Texas Instruments, LM22677 Datasheet, “LM22677/LM22677Q 5A SIMPLE SWITCHER, Step-Down Voltage Regulator with Synchronization or Adjustable Switching Frequency”, 2011.

[10] The McGraw-Hill Companies, “Analog IC Design With Low Dropout Regulators”, 2009.

Appendix A: Design Report for Design 1

Appendix B: Design Report for Design 2

Appendix C: Launchpad C Program msp430g2xx3_lpm3_vlo.c program for Launchpad

// Master MSP430

// ------

// | P1.6|-->LED2

// | P1.0|-->LED1 ----->hardwired to P1.3 on the Slave MP430

// | |

#include void main(void)

{

WDTCTL = WDTPW + WDTHOLD;

P1DIR |= BIT0; // Set P1.0 to output direction (Red LED) // P1.0 low also triggers Slave MSP430 to run P1DIR |= BIT6; // Set P1.6 to output direction (Green LED)

volatile long i;

P1OUT = BIT0; // Start with RED LED ON, Green LED off on all Launchpads for (;;)

{ while ((P1IN & BIT3)); // Wait for button press on P1.3 to start // We also wired P1.3 (INPUT) to P1.0 (Red LED Output) // for the Slave MSP430. A low P1.0 triggers //the Slave MP430. 55

for (i=0; i<500; i++); // A little delay after the trigger

P1OUT = BIT0;

P1OUT ^= BIT0 + BIT6; // TOGGLE the two LEDs (Red LED off, Green LED on)

for (i=0; i<50; i++); // This brings P1.0 Low on the Master MSP430 and // triggers the Slave MSP430 via P1.3.

P1OUT ^= BIT0 + BIT6; // TOGGLE the two LEDs (Red LED on, Green LED off) // and wait for trigger.

} //endless loop // The little MSP430 never gets bored.

} //main