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Trends in Integrated Circuits Technology EE 311 Notes/Prof Saraswat Handout # 2 Trends in Integrated Circuits Technology Semiconductors have become increasingly more important part of world economy Silicon CMOS has become the pervasive technology 1 EE 311 Notes/Prof Saraswat Handout # 2 Minimum chip feature per lithographic bits size or ( µ m) Transistors Year Ref: A. I. Kingon et al., Nature 406, 1032 (2000). Year 1997 1999 2003 2006 2009 2012 Technology node 250 nm 180 nm 130 nm 100 nm 70 nm 50 nm (DRAM half pitch) Minimum Feature 180 nm 120 nm 70 nm 60 nm 40 30 Size DRAM Bits/Chip 256M 1G 4G 16G 64G 256G DRAM Chip Size 280 400 560 790 1120 1580 (mm2) Microprocessor 11M 21M 76M 200M 520M 1.40B Transistors/chip Maximum Wiring 6 6-7 7 7-8 8-9 9 Levels Minimum Mask 22 22/24 24 24/26 26/28 28 Count Minimum Supply 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 Voltage (volts) Future projections for silicon technology taken from the SIA ITRS 1999 2 EE 311 Notes/Prof Saraswat Handout # 2 Ref. H. komiya IEEE ISSCC 1993 Device structures are becoming increasingly more complex The scaling trends for Intel microprocessors. 3 EE 311 Notes/Prof Saraswat Handout # 2 MOS Device Scaling L xox X j Scaled MOS Transistor G N+ N a N+ S D N+ N+ l o P P Why do we scale MOS transistors? 1. Increase device packing density 1 2. Improve frequency response (transit time) α L 3. Improve current drive (transconductance gm) ∂ID gm = ∂VG VD = const W K ox ≈ µn VD for VD < VDSAT , linear region L tox W K ≈ µ ox V − V for V > V , saturation region n ( G T ) D DSAT L tox Decreasing the channel length and gate oxide thickness increases gm, i.e., the current drive of the transistor. Much of the scaling is therefore driven by decrease in L and tox. However if only these two parameters are scaled many problems are encountered, e.g., increased electric field. The most widely used scaling rule is to maintain the electric field in the device constant Device/Circuit Parameter Constant Field Scaling Factor Dimension : xox, L, W, Xj, 1/K Substrate doping : Na K Supply voltage : V 1/K Supply current : I 1/K Gate Capacitance : W L/xox 1/K Gate delay : C V / I 1/K Power dissipation : C V2 / delay 1/K2 Delay power product : 1/K3 4 € EE 311 Notes/Prof Saraswat Handout # 2 Speed increases as a result of scaling 109 the effect of better 108 microprocessor architectures Pentium Number of Instructions 107 per Second 486 speed doubles each 3-yr generation 386 106 80286 8080 105 Intel Microprocessors 4004 104 1965 1975 1985 1995 So Does the Cost of a Factory 10,000 2x every 4 years 1000 cost of a modern 2x every 3 years wafer fab 1.47x every 2 years 100 ($ million) 10 1 1960 1970 1980 1990 2000 5 EE 311 Notes/Prof Saraswat Handout # 2 In reality constant field scaling has not been observed strictly. Since the transistor current is proportional to the gate overdrive (VG-VT), high performance demands have dictated the use of higher supply voltage. However, higher supply voltage implies increased power dissipation (CV2f). In the recent past low power applications have become important and have required a scaling scenario with lower supply voltage. Ref: Davri, et al. Proc. IEEE, April 1995 In general the device scaling methodology does not take into account many other chip performance and reliability issues, e.g., interconnects, contacts, isolation, etc. These factors are now becoming an obstacle in the evolution of integrated circuits. How far can we continue to scale? (Source: J. Plummer) 6 EE 311 Notes/Prof Saraswat Handout # 2 Effect of Reducing Channel Length: Drain Induced Barrier Lowering Gate L N+ source Depletion N+ drain region L’ rj P-Si QB depleted QB depleted by source by drain In devices with long channel lengths, the gate is completely responsible for depleting the semiconductor (QB). In very short channel devices, part of the depletion is accomplished by the drain and source bias. Since less gate voltage is required to deplete QB, the barrier for electron injection from source to drain decreases Potential variation along the channel for MOS transistors with 2.5 and 0.5 µm channel lengths. The 0.5 µm device shows DIBL effect. The reduction in the barrier is known as “drain induced barrier lowering (DIBL)”. DIBL results in an increase in drain current at a given VG. Therefore VT↓ as L↓. Similarly, as 7 EE 311 Notes/Prof Saraswat Handout # 2 VD ↑, more QB is depleted by the drain bias, and hence ID↑ and VT↓. This is An approximate relation for threshold voltage due to DIBL is: Q 2 ⋅W r V = V − 2 ⋅φ − B ⋅ 1− 1 + −1 ⋅ j T FB F C r L ox j To minimize the effect of DIBL: • Cox should be increased, i.e., decrease gate oxide thickness. This results in increased control of the gate. • Decrease junction depth (rj) Scaling of gate oxide thickness and junction depth causes many other problems. Hot Carrier Effects For a reverse biased p-n junction discussion we remember that the maximum electric field intensity is near the junction itself and it increases with the reverse bias. 2qNa (φi − VD ) ξmax = εox In the case of MOS transistor the potential drop along the channel is not uniform with most of it across the reverse biased drain-substrate junction. Therefore the electric field intensity is also non-uniform with the maximum occurring near the drain junction. As the channel length is reduced the electric field intensity in the channel near the drain increases more rapidly in comparison to the long channel case, even if VD is scaled, as φi does not scale. 8 EE 311 Notes/Prof Saraswat Handout # 2 The free carriers passing through the high-field can gain sufficient energy to cause several hot-carrier effects. This can cause many serious problems for the device operation. Hot carriers can have sufficient energy to overcome the oxide-Si barrier. They are injected from channel to the gate oxide (process 1) and cause gate current to flow. Trapping of some of this charge can change VT permanently. Avalanching can take place producing electron-hole pairs (process 2). The holes produced by avalanching drift into the substrate and are collected by the substrate contact (process 3) causing Isub IR drop due to Isub(process 4) can cause substrate-source junction to be forward biased causing electrons to be injected from source into substrate (process 5). Some of the injected electrons are collected by the reversed biased drain and cause a parasitic bipolar action (process 5). 9 EE 311 Notes/Prof Saraswat Handout # 2 Scaling of MOS Gate Dielectric (Ref: S. Asai, Microelectronics Engg., Sept. 1996) By the end of this decade the MOS gate dielectric thickness will be well below 10 Å. K I ∝ g ∝ D m thickness • How far can we push MOS gate dielectric thickness? • How will we grow such a thin layer uniformly? • How long will such a thin dielectric live under electrical stress? • Can we improve the endurance of the dielectric by changing its structure? Problems in scaling gate oxide Polysilicon gate electrode Dopant Leakage current penetration gate oxide Reliability due to Defects and charge injection nonuniformity of film Dielectric breakdown Si substrate 10 EE 311 Notes/Prof Saraswat Handout # 2 Gate Dielectric Degradation and Breakdown Under high field electrons are injected in the SiO2 conduction band because of reduction in barrier height and thickness. Some electrons gain excess energy in the conduction band of the oxide. At the anode they lose kinetic and potential energy causing physical damage leading to traps generation. Further trapping of electrons and holes causes dielectric degradation. (1) Electron injection e (1) (2) Energy released by hot electron Cathode (3) Bond breaking at the interface - trap generation (4) Hot hole generation by impact ionization and injection (5) Energy released by hot hole - trap generation (3) (6) Hydrogen release - trap generation Oxide e (5) (2) Anode (6) h (3) e Hydrogen (4) h Ref: Apte & Saraswat IEEE Trans. Electron Dev., Sept 1994 We can improve the endurance of the dielectric by optimizing the process technology and changing its structure. For example incorporating nitrogen or fluorine instead of hydrogen strengthens the Si/SiO2 interface and increases the gate dielectric lifetime because Si-F and Si-N bonds are stronger than Si-H bonds. Poly-Si Gate Oxide N or F Si substrate 11 EE 311 Notes/Prof Saraswat Handout # 2 Problems caused by conduction in ultrathin gate oxide As we decrease the gate dielectric thickness, the conduction through the dielectric film becomes appreciable. This may increase power dissipation and cause problems for circuit stability. Increased leakage due to direct tunneling through the gate dielectric may make dynamic and static circuits unstable. Thin Oxide Thick Oxide Direct Tunneling Fowler-Nordheim Tunneling Oxide Si Si (Ref: From Y. Taur et al., Proc. IEEE, April 1997.) Gate Leakage Current Density Versus Gate Voltage for Various Oxide Thicknesses 12 EE 311 Notes/Prof Saraswat Handout # 2 1000 Ion m) µ 10 A/ µ ( 0.1 Ioff 0.001 Current Source G. Bersuker, et al. Sematech Igate 0.00001 50 70 100 130 180 Technology Generation (nm) Rather than scaling thickness of SiO2 perhaps we can scale the dielectric constant (K) to improve the performance. Alternatively for the same performance we can increase the dielectric thickness by increasing its K.
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