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EE 311 Notes/Prof Saraswat Handout # 2

Trends in Integrated Circuits

Semiconductors have become increasingly more important part of world

Silicon CMOS has become the pervasive technology

1 EE 311 Notes/Prof Saraswat Handout # 2 Minimum chip

per lithographic bits size or ( µ m)

Year

Ref: A. I. Kingon et al., 406, 1032 (2000).

Year 1997 1999 2003 2006 2009 2012 Technology node 250 nm 180 nm 130 nm 100 nm 70 nm 50 nm (DRAM half pitch) Minimum Feature 180 nm 120 nm 70 nm 60 nm 40 30 Size DRAM Bits/Chip 256M 1G 4G 16G 64G 256G DRAM Chip Size 280 400 560 790 1120 1580 (mm2) 11M 21M 76M 200M 520M 1.40B Transistors/chip Maximum Wiring 6 6-7 7 7-8 8-9 9 Levels Minimum Mask 22 22/24 24 24/26 26/28 28 Count Minimum Supply 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 (volts)

Future projections for technology taken from the SIA ITRS 1999

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Ref. H. komiya IEEE ISSCC 1993 Device structures are becoming increasingly more complex

The scaling trends for .

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MOS Device Scaling L xox X j Scaled MOS

G N+ N a N+ S D N+ N+ l o P P

Why do we scale MOS transistors? 1. Increase device packing density 1 2. Improve frequency response (transit time) α L

3. Improve current drive ( gm)

∂ID gm = ∂VG VD = const

W K ox ≈ µn VD for VD < VDSAT , linear region L tox W K ≈ µ ox V − V for V > V , saturation region n ( G T ) D DSAT L tox

Decreasing the channel length oxide thickness increases gm, i.e., the current drive

of the transistor. Much of the scaling is therefore driven by decrease in L and tox. However if only these two parameters are scaled many problems are encountered, e.g., increased .

The most widely used scaling rule is to maintain the electric field in the device constant

Device/Circuit Parameter Constant Field Scaling Factor Dimension : xox, L, W, Xj, 1/K Substrate doping : Na K Supply voltage : V 1/K Supply current : I 1/K Gate Capacitance : W L/xox 1/K Gate delay : C V / I 1/K Power dissipation : C V2 / delay 1/K2 Delay power product : 1/K3

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€ EE 311 Notes/Prof Saraswat Handout # 2

Speed increases as a result of scaling

109

the effect of better 108 microprocessor Pentium Number of Instructions 107 per Second 486 speed doubles each 3-yr generation 386 106 80286

8080 105 Intel Microprocessors 4004

104 1965 1975 1985 1995

So Does the Cost of a Factory

10,000

2x every 4 years

1000

cost of a modern 2x every 3 years fab 1.47x every 2 years 100 ($ million)

10

1 1960 1970 1980 1990 2000

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In reality constant field scaling has not been observed strictly. Since the transistor current is proportional to the gate overdrive (VG-VT), high performance demands have dictated the use of higher supply voltage. However, higher supply voltage implies increased power dissipation (CV2f). In the recent past low power applications have become important and have required a scaling scenario with lower supply voltage.

Ref: Davri, et al. Proc. IEEE, April 1995

In general the device scaling methodology does not take into account many other chip performance and reliability issues, e.g., interconnects, contacts, isolation, etc. These factors are now becoming an obstacle in the evolution of integrated circuits.

How far can we continue to scale?

(Source: J. Plummer)

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Effect of Reducing Channel Length: Drain Induced Barrier Lowering Gate

L N+ source Depletion N+ drain region L’ rj P-Si

QB depleted QB depleted by source by drain

In devices with long channel lengths, the gate is completely responsible for depleting the (QB). In very short channel devices, part of the depletion is accomplished by the drain and source bias. Since less gate voltage is required to deplete QB, the barrier for injection from source to drain decreases

Potential variation along the channel for MOS transistors with 2.5 and 0.5 µm channel lengths. The 0.5 µm device shows DIBL effect.

The reduction in the barrier is known as “drain induced barrier lowering (DIBL)”. DIBL results in an increase in drain current at a given VG. Therefore VT↓ as L↓. Similarly, as

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VD ↑, more QB is depleted by the drain bias, and hence ID↑ and VT↓. This is

An approximate relation for threshold voltage due to DIBL is:

Q   2 ⋅W  r  V = V − 2 ⋅φ − B ⋅ 1−  1 + −1 ⋅ j T FB F C  r L ox   j  

To minimize the effect of DIBL:

• Cox should be increased, i.e., decrease gate oxide thickness. This results in increased control of the gate.

• Decrease junction depth (rj)

Scaling of gate oxide thickness and junction depth causes many other problems.

Hot Carrier Effects

For a reverse biased p-n junction discussion we remember that the maximum electric field intensity is near the junction itself and it increases with the reverse bias.

2qNa (φi − VD ) ξmax = εox

In the case of MOS transistor the potential drop along the channel is not uniform with most of it across the reverse biased drain-substrate junction. Therefore the electric field intensity is also non-uniform with the maximum occurring near the drain junction. As the channel length is reduced the electric field intensity in the channel near the drain increases more rapidly in comparison to the long channel case, even if VD is scaled, as φi does not scale.

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The free carriers passing through the high-field can sufficient to cause several hot-carrier effects. This can cause many serious problems for the device operation.

Hot carriers can have sufficient energy to overcome the oxide-Si barrier. They are injected from channel to the gate oxide (process 1) and cause gate current to flow. Trapping of some of this charge can change VT permanently. Avalanching can take place producing electron- pairs (process 2). The holes produced by avalanching drift into the substrate and are collected by the substrate contact (process 3) causing Isub IR drop due to Isub(process 4) can cause substrate-source junction to be forward biased causing to be injected from source into substrate (process 5). Some of the injected electrons are collected by the reversed biased drain and cause a parasitic bipolar action (process 5).

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Scaling of MOS Gate Dielectric

(Ref: S. Asai, Engg., Sept. 1996)

By the end of this decade the MOS gate dielectric thickness will be below 10 Å. K I ∝ g ∝ D m thickness

• How far can we push MOS gate dielectric thickness? • How will we grow such a thin layer uniformly? • How long will such a thin dielectric live under electrical stress? • Can we improve the endurance of the dielectric by changing its structure?

Problems in scaling gate oxide

Polysilicon gate electrode

Dopant current penetration

gate oxide

Reliability due to Defects and charge injection nonuniformity of Dielectric breakdown Si substrate

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Gate Dielectric Degradation and Breakdown

Under high field electrons are injected in the SiO2 conduction band because of reduction in barrier height and thickness. Some electrons gain excess energy in the conduction band of the oxide. At the anode they lose kinetic and potential energy causing physical damage leading to traps generation. Further trapping of electrons and holes causes dielectric degradation.

(1) Electron injection e (1) (2) Energy released by hot electron (3) Bond breaking at the interface - trap generation (4) Hot hole generation by impact ionization and injection (5) Energy released by hot hole - trap generation (3) (6) Hydrogen release - trap generation

Oxide e (5) (2) Anode (6) h (3) e Hydrogen

(4) h Ref: Apte & Saraswat IEEE Trans. Electron Dev., Sept 1994

We can improve the endurance of the dielectric by optimizing the process technology and changing its structure. For example incorporating nitrogen or fluorine instead of hydrogen strengthens the Si/SiO2 interface and increases the gate dielectric lifetime because Si-F and Si-N bonds are stronger than Si-H bonds.

Poly-Si Gate

Oxide N or F

Si substrate

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Problems caused by conduction in ultrathin gate oxide

As we decrease the gate dielectric thickness, the conduction through the dielectric film becomes appreciable. This may increase power dissipation and cause problems for circuit stability. Increased leakage due to direct tunneling through the gate dielectric may make dynamic and static circuits unstable. Thin Oxide Thick Oxide Direct Tunneling Fowler-Nordheim Tunneling

Oxide Si Si

(Ref: From Y. Taur et al., Proc. IEEE, April 1997.) Gate Leakage Current Density Versus Gate Voltage for Various Oxide Thicknesses

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1000 Ion m) µ 10 A/ µ ( 0.1

Ioff 0.001 Current

Source G. Bersuker, et al. Sematech Igate 0.00001 50 70 100 130 180 Technology Generation (nm)

Rather than scaling thickness of SiO2 perhaps we can scale the dielectric constant (K) to improve the performance. Alternatively for the same performance we can increase the dielectric thickness by increasing its K. K I ∝ g ∝ D m thickness

high K > 20

100 Å Si3N4 K ≈ 8 SiO2 K ≈ 4 20 Å 40 Å Today Near Long term Near term and long term approaches for scaling the MOS gate dielectric.

However, replacing SiO2 by another dielectric is a very difficult task as it is one of the best dielectrics and is one of the main reasons of the success of Si technology.

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Scaling of Ohmic Contacts and Junctions

Silicide metal Rc Poly-Si

Rch Xj Rs Rs’ Rd’ Rd source drain

• Device scaling dictates shallow junctions. • How will we form such shallow junctions? • How will we make low resistance contacts to them? • What will be the impact of the resistance of the contacts and junctions?

ρC Rc

Source: Jasonn Woo, UCLA

Year 1997 1999 2003 2006 2009 2012 Min Feature Size 0.18µ 0.12µ 0.07µ 0.06µ 0.04µ 0.03µ Contact xj (nm) 100-200 70-140 50-100 40-80 15-30 10-20 xj at Channel (nm) 50-100 36-72 26-52 20-40 15-30 10-20

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Specific contact resistivity  *  2φ B εsm 2 ρc = ρ co exp  ohm − cm  qh N 

where φB is the barrier height and N is the doping density in the semiconductor.

Problem in scaling: • Contact resistance is a strong function of doping density at the metal/silicon interface • Sheet resistance of a junction is a strong function of doping density in the junction • However, the maximum doping density is limited by solubility and it does not scale !

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Solutions to Shallow Junction Problem

Shallow extension implants to minimize (DIBL)

Elevated source/ drain to minimize (DIBL)

Silicidation to junction minimize resistance

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Scaling of Device Isolation

Isolation pitch as a function of minimum dimension

2.5

2.0 16M

1.5 64M

1.0 1G

0.5

0.0 0.0 0.2 0.4 0.6 0.8 1.0 Minimum dimension [µm] P. Fazan, Micron, IEDM-93 LOCOS based isolation technologies have serious problems in loss of area due to bird’s beak.

Semi-recessed LOCOS Nitride Nitride Pad oxide

Field oxide

After field oxidation Fully recessed LOCOS

Nitride Pad oxide

After field oxidation

Large stresses can build up in LOCOS based isolation technologies.

F2

F3

F1

F4

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Shallow trench isolation

P-substrate N-well

Deep trench isolation

Trench isolation can minimize area loss, however, large stresses can build up in trench structures resulting in bandgap reduction and eventually if the stress is too much it can cause defects leading to increase in leakage and yield loss.

10-11 N+ P

10-12 Distance [µm]

10-13

-14 10 0 500 1000 1500 Compressive stress [MPa]

The stress is a function of process temperatures as at higher temperatures SiO2 has viscous flow which can relieve the stress. However, thermal budget demands low temperature processing. 103

900 ˚C

102

1000 ˚C

101 1100 ˚C

0 10 1 10 100 Active area pitch [ µm]

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Source: J. D. Meindl, , “Integration Limits on XXI Century Gigascale Integration”, IEEE Interconnect Technology Conf. Short Course, San Francisco, CA, May 31, 1998

1E8 Local Semiglobal Global 1E6

1E4 LSemi-global

1E2

2D 1E0 LLocal

3D 1E-2

1E-4

1 10 100 1000 Interconnect Length, l (gate pitches)

• Number of interconnects are increasing • Most of the interconnects are very short but a few are very long

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Impact of Scaling of Interconnections on Circuit Performance

• Chip area is increasing => length of the longest is increasing • Cross sectional dimensions of the interconnects are decreasing resulting in an increase in resistance and capacitance • Increased R and C results in higher propagation delay • 500 CAPACITANCE 400 Line To Ground Line To Line Total 300

200 Higher Packing Density ⇓

Capacitance 100 Decreased Space Between Interconnects 0 ⇓ 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Higher RC-Delay Space Width (µm) [=Line Width] (fF/mm)

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• Parasitic resistance and capacitance associated with interconnections and contacts are now begining to influence circuit performance and will be the primary factors in the evolutions of submicron ULSI technology. • Lower resistivity metals and lower dielectric constant insulators will reduce the R and C

1.0 Interconnect Delay

0.1 Delay (ns) Typical Gate Delay

0.01

60 80 100 120 140 160 180 Technology Generation (nm) .

Copper 6

Copper 5

Copper 4

Copper 3

Copper 2 Copper 1

Tungsten Local Interconnect Current Cu technology (Courtesy of IBM)

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global

semiglobal

local

By increasing the levels of interconnect problem can be minimized. Shorter (local) wires can be placed in thinner interconnects and longer (global) wires can be made with larger cross section to minimize R and C.

14 13

12 Al & SiO2 ( κ = 4) 11 Cu & SiO2 ( κ = 4) 10 9 8 7 6 5 4 Al & low-κ (κ = 2) 3 2 Cu & lo w- κ ( κ = 2) 1 0.09 0.13 0.18 0.25 0.35 µm 2007 2004 2001 1998 1995 Year Tec hnology Generation

Reduced resistivity and dielectric constant results in reduction in number of metal layers as more wires can by placed in lower levels of metal layers.

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Problems in Scaling of Interconnections Cu diffuses in most dielectrics readily and acts as a recombination center in Si. Hence a barrier is generally needed to enclose Cu line to avoid its diffusion in the dielectric. Barriers are generally highly resistive.

As λ decreases • Resistivity increases as grain size decreases • Resistivity increases as main conductor size decreases but not the surrounding film size

Surrounded Interconnect

Cu Barrier

ρav Layered Interconnect

Al Barrier

Al Pure Metal Interconnect Cu Minimum Feature Size (λ)

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Thermal Behavior • Energy dissipated (CV2f) is increasing as performance improves • Thermal conductivity of low-k insulators is poor • Average chip temperature is rising Thermal Conductivity 4 1.2

1 [ 3 W

0.8 / 2 0.6 mK

0.4 ] 1 0.2

Dielectric Constant 0 0 35 50 70 100 130 180 Technology Node [nm] ] 2

30 5 J

max 25 4

20 [ MA / cm 3 15 2 10 5 1

0 0 2 35 50 70 100 130 180 ]

Power Density [ W / cm Technology Node [nm]

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Electromigration

Electromigration due to electron wind induced diffusion of Al through grain boundaries

SEM of hillock and voids formation due to electromigration in an Al(Cu,Si) line

Mean time to failure due to electromigration is given by

A  E  MTF = exp a  r mJ n  kT 

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Summary: Technology Progression

MOS Transistor in 2010 Gate oxide thickness 10 Å Channel Length < 500 Å Junction depth < 500 Å Size of an atom ~ 5 Å

A Circuit in 2010 In integrated > 1 billion components > 10 interconnect layers

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