Memory Interface
CEN433 King Saud University Dr. Mohammed Amer Arafah
1 Address Decoding
MS (9 bits) LS (11 bits) Memory devices interfaced are usually Memory of smaller storage capacity than the BA0-19 19 11 10 0 chip full address space of the processor
For example, the 2716 is 2 K x 8 A10-A0 memory device has 11 (= 1 + 10) 9 Selector 11 Address address inputs (A0-A10). bits bits
When interfaced to a microprocessor 9 to 1 CS/ with 20 address signals there is a Decoder mismatch.
The extra 9 address pins (A11-A19) are decoded using a decoder such FFFFFH High that they select the memory device for 511 Memory a unique position in the memory map (ROM) of the processor. MS (9 bits) LS (11 bits) 510 9 9 Here the mP address space is 2 000000001 xxxxxxxxxxx . 2 = times the size of the memory chip . 512 times 00FFFH 211 = Decoding A11-A19 and using them for 1 2048 selecting the memory chip fixes the 00800H Low Memory position of the memory locations in the 0 mP address map 00000H (RAM) mP Memory Map
CEN433 - King Saud University 2 Mohammed Amer Arafah Example 1: Exhaustive Address Decoding (Simple NAND Gate Decoder)
Memory locations:FF800H-FFFFFH
CEN433 - King Saud University 3 Mohammed Amer Arafah Example 2: Exhaustive Address Decoding
CEN433 - King Saud University 4 Mohammed Amer Arafah Example 3: Exhaustive Address Decoding (Simple NAND Gate Decoder)
32 K x 8 memory device: 15 bit 15 address: 2 locations U2A
BA19 1 2 1 U1 Selector address: 20 – 15 = 5 bits 2 3 4 74LS04 8 CS/ If we want the memory locations to U2B 5 6 start at 10000H, What is the BA18 3 4 11 selector address to decode?: 12 74LS30 74LS04 Start Address U2C 00010000000000000000 = 10000H BA17 5 6
End address 74LS04 BA16 00010111111111111111 = 17FFFH U2C
BA15 5 6 Selector 5 bits: 00010 (Remain fixed) 74LS04
Check: These are 7FFF+1 = 8000H = 215 locations
CEN433 - King Saud University 5 Mohammed Amer Arafah Exhaustive Address Decoding (74LS138 – 74LS139)
CEN433 - King Saud University 6 Mohammed Amer Arafah Example 4: Exhaustive Address Decoding
Module 0: (74LS138) 1111 000X XXXX XXXX XXXX 1111 0000 0000 0000 0000 to 1111 0001 1111 1111 1111 . . . Module 7: 1111 111X XXXX XXXX XXXX 1111 1110 0000 0000 0000 to 1111 1111 1111 1111 1111
Memory locations:F0000H-FFFFFH
CEN433 - King Saud University 7 Mohammed Amer Arafah Example 5: Exhaustive Address Decoding (74LS138)
64 KB EPROM Starting at F0000H Answer: BA16 1 U1A BA17 2 F0000 – FFFFFH. 6 CS/ BA18 4 BA0-BA15: Location Addressing. BA19 5 74LS20 BA16-BA19: Space Addressing.
Assume that 64 KB EPROM is not found! We can replace it with 8 of 8KB EPROM.
Starting address is F0000H. U2 BA13 1 15 CS0/ BA14 2 A Y0 14 CS1/ Answer: BA15 3 B Y1 13 CS2/ BA16 1 U1A C Y2 12 CS3/ BA17 2 Y3 11 CS4/ BA16-BA19: Space Addressing. 6 6 Y4 10 CS5/ BA18 4 4 G1 Y5 9 CS6/ BA19 5 5 G2A Y6 7 CS7/ 8KB EPROM G2B Y7 74LS20 BA0-BA12: Location Addressing 74LS138 BA13-BA15: 8KB Module Addressing
CEN433 - King Saud University 8 Mohammed Amer Arafah Example 6: Exhaustive Address Decoding (74LS139)
64 KB EPROM Starting at F0000H Answer: BA16 1 U1A BA17 2 F0000 – FFFFFH. 6 CS/ BA18 4 BA0-BA15: Location Addressing. BA19 5 74LS20 BA16-BA19: Space Addressing.
Assume that 64 KB EPROM is not found! We can replace it with 4 of 16KB EPROM. Starting address is F0000H. U2A BA14 2 4 CS0/ A Y0 BA16 1 U1A BA15 3 5 CS1/ B Y1 Answer: BA17 2 6 CS2/ Y2 6 1 7 CS3/ BA18 4 G Y3 BA16-BA19: Space Addressing. BA19 5 74LS139 16KB EPROM 74LS20 BA0-BA13: Location Addressing BA14-BA15: 8KB Module Addressing
CEN433 - King Saud University 9 Mohammed Amer Arafah Exhaustive Address Decoding (PLD Decoders )
Many modern systems use programmable logic decoders in place of integrated decoders They give total freedom in decoding different addresses for individual memory devices Programmable logic devices have may be called: PLDs: Programmable logic devices PLAs: Programmable logic array PALs: Programmable array logic GALs: Gate Array Logic SPLDs: Simple programmable logic devices CPLDs: Complex programmable logic devices They are all programmable logic devices. Nowadays they can be programmed using VHDL (Verilog Hardware Definition Language) Some types are programmed only once (fused links), similar to PROMs Some types are erasable like EPROMs The next slide shows one of the most common low cost devices: the PAL16L8
CEN433 - King Saud University 10 Mohammed Amer Arafah PAL16L8
CEN433 - King Saud University 11 Mohammed Amer Arafah PAL16L8 x x y y z z xyz xyz
x x x F = (xyz)+(xyz) x x x
y
z
CEN433 - King Saud University 12 Mohammed Amer Arafah Example 7: Exhaustive Decoding
CEN433 - King Saud University 13 Mohammed Amer Arafah Example 7: Exhaustive Decoding
library ieee; use ieee.std_logic_1164.all; entity DECODER_10_17 is port ( BA19, BA18, BA17: in STD_LOGIC; Input declaration ROMCS/, RAMCS/ : out STD_LOGIC; output declaration ); end; architecture V1 of DECODER_10_17 is begin
ROMCS/ <= not BA19 or not BA18 or not BA17 ; ROMCS/ = 0 for BA19BA18BA17 = 111 RAMCS/ <= A17 or A18 or BA19 ; RAMCS/ = 0 for BA19BA18BA17 = 000 end V1;
CEN433 - King Saud University 14 Mohammed Amer Arafah Example 8: Exhaustive Decoding
A19 A18 A17 A16 A15 A19 A18 A17 A16 A15 A19 A18 A17 A16 A15 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1
32 K x 8 32 K x 8 32 K x 8
E8000-EFFFF F0000-F7FFF F8000-FFFFF
CEN433 - King Saud University 15 Mohammed Amer Arafah Interfacing EEPROM (Flash) Memories
Main Flash memory applications: Used when contents need to be changed only infrequently, e.g.: Storing system BIOS USB pen drives MP3 audio players
Similarities with SRAMs: Both need the 3 basic memory control inputs: CE, OE, and WE
Differences with SRAMs:
1. EEPROM needs an additional programming controls and programming (erasing) supply voltage. Used to be 25 or 12V, now 5 or even 3.3V.
1. EEPROM is much slower to write (erase) a byte: 0.4 s Versus 10ns for SRAM
CEN433 - King Saud University 16 Mohammed Amer Arafah Example 9: Interfacing EEPROM
Select Byte (not Word) operation
In Byte operation, 28F400 DQ15 is an input Flash accepting A0 Memory address bit. 512K x 8 (In the Byte In the word mode: Mode) 256 K x 16
18-bit address starting with A1
FFFFFH
80000H 7FFFFH Address: Start: 10000000000000000000 Enable Power down mode End: 11111111111111111111 00000H i.e. 80000H to FFFFFH Programming supply voltage Flash occupies the top Half of the memory map Additional controls for Flash memory. Used for programming (erasing)
CEN433 - King Saud University 17 Mohammed Amer Arafah Example 10: Exhaustive Decoding
Interface a 16KB RAM and a 64KB EPROM to an 8088 buffered system. Assume the starting address of the RAM is 0H and the starting address of the EPROM is F0000H. Use NAND gates, as needed, to generate the chip selects.
CEN433 - King Saud University 18 Mohammed Amer Arafah Solution of Example 10:
CEN433 - King Saud University 19 Mohammed Amer Arafah Example 11: Exhaustive Decoding
Interface a 4KB RAM and an 8KB EPROM to an 8088 buffered system. Assume the starting address of the RAM is 0H and the last address of the EPROM is FFFFFH. Use NAND gates, as needed, to generate the chip selects.
CEN433 - King Saud University 20 Mohammed Amer Arafah Solution of Example 11:
CEN433 - King Saud University 21 Mohammed Amer Arafah Example 1: Partial Decoding
Ignoring both BA18 and BA19
CEN433 - King Saud University 22 Mohammed Amer Arafah Example 2: Partial Decoding
Ignoring both BA17, BA18 and BA19
CEN433 - King Saud University 23 Mohammed Amer Arafah Example 3: Partial Decoding
Ignoring both BA17 and BA18
CEN433 - King Saud University 24 Mohammed Amer Arafah Example 4: Partial Decoding
Ignoring BA16, BA17 and A18
CEN433 - King Saud University 25 Mohammed Amer Arafah Example 5: Partial Decoding
Assume that the 1M memory space is divided into 16 blocks. One of these blocks is used, and the rest are ignored. The block is divided further into 4 segments. The first segment is used only by a 2KB RAM, the second and the third segment are left for future expansion, and the fourth segment is used only by an 8KB EPROM. Interface both 2KB RAM and 8KB EPROM to the 8088 system using partial decoding.
CEN433 - King Saud University 26 Mohammed Amer Arafah Solution of Example 5:
CEN433 - King Saud University 27 Mohammed Amer Arafah Interfacing 16-bit Memory to the 8086, 80286, and 80386SX
Main differences: 8086 from the 8088: The M/#IO replaces the IO/#M control signal
The data bus is now 16 bits not 8 bits
A new control output, BHE/ [Bus (byte) High Enable]
A0 has a special use as BLE/ [Bus (byte) Low Enable]
Main differences between 8086/186 and 80286/386SX: 80286/386SX has 24-bit address bus (A23-A0)
The M/#IO, RD/, WR/ are replaced with MRDC/, MWTC/, IORDC/ and IOWTC/- more specific signals
CEN433 - King Saud University 28 Mohammed Amer Arafah 16-Bit Wide Memory
16-bit wide memory is organized in two separate 8-bit wide memory banks: Low bank (even-numbered byte locations: 0, 2, 4, 6, …) low 8 bits of the data bus (D0-D7): LS Byte
High bank (odd-numbered byte locations: 1, 3, 5, 7, …) high 8 bits of the data bus (D8-D15): MS Byte
Processor must be able to access any 16 or 8 bit locations
Banks are selected by the microprocessor through bank selection (Bank Enable) signals
On the 8086, these byte selection signals are - The BLE/ (A0) signal selecting low bank - The BHE/ signal selecting high bank
Only with writes…. For Reads, the processor will take the byte it wants and no need to enforce byte (bank) selection
CEN433 - King Saud University 29 Mohammed Amer Arafah 16-Bit Wide Memory
FFFFF FFFFE FFFFD FFFFC FFFFB FFFFA ...... 00005 00004 00003 00002 00001 00000 High Bank Low Bank (Odd Bank) (Even Bank)
BBHE/ BA0 Function 0 0 Both banks enabled for a 16-bit transfer 0 1 High bank enabled for an 8-bit transfer 1 0 Low bank enabled for an 8-bit transfer 1 1 No banks enabled
CEN433 - King Saud University 30 Mohammed Amer Arafah 16-Bit Wide Memory
Encoding Separate Write Signals
Why consider this only with write access (not Reads)? Because the processor can choose only the byte(s) it wants to read from the full 16-bit data placed on the data bus by the 2 banks. So always enable both banks for READs.
CEN433 - King Saud University 31 Mohammed Amer Arafah Example 1: 16-Bit Wide Memory High bank data bits Low bank data bits
Note: A1 not A0 32K x 8 32K x 8
No bank selection for READs Common to both banks
Low Bank High Bank
Write Write Enable Enable Common CE for both banks for low for high Active Low (one decoder) bank bank
If start byte address is 060000, Last address is 06FFFFH SEL = A23 + A22 + A21 + A20 + A19 + #A18 + #A17 + A16 (active low)
CEN433 - King Saud University 32 Mohammed Amer Arafah Example 1: 16-Bit Wide Memory
library ieee; use ieee.std_logic_1164.all; entity DECODER_10_28 is port ( A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC: in STD_LOGIC; SEL, LWR, HWR: out STD_LOGIC ); end; architecture V1 of DECODER_10_28 is begin SEL <= A23 or A22 or A21 or A20 or A19 or (not A18) or (not A17) or A16; LWR <= A0 or MWTC; HWR <= BHE or MWTC; end V1;
CEN433 - King Saud University 33 Mohammed Amer Arafah Example 2: Memory Interface to 8086
We want to interface 64 KB RAM and 64KB EPROM chips to 8086 microprocessor according to the following assumptions: The starting address of the RAM is 0H. The last address of the EPROM is FFFFFH. Exhaustive decoding is used. The RAM and EPROM chips are organized as following:
CEN433 - King Saud University 34 Mohammed Amer Arafah Example 2: Memory Interface to 8086
CEN433 - King Saud University 35 Mohammed Amer Arafah Example 3: Memory Interface to 8086
We want to interface 64 KB RAM to 8086 microprocessor according to the following assumptions: The starting address of 64 KB RAM in the memory space is 0H. Exhaustive decoding is used. The RAM chips are organized as following:
CEN433 - King Saud University 36 Mohammed Amer Arafah Example 3: Memory Interface to 8086
BBHE/ = 0 BA0 = 0
00000 00000 8K × 8 BA1-13 RAM BD0-7 03FFF RAML1CS/ 04000 8K × 8 MEMR/ 32K × 8 LWR/ RAM 07FFF RAM BA1-15 BD8-15 08000 RAMHCS/ BA1-13 BD0-7 16K × 8 MEMR/ RAML2CS/ RAM HWR/ MEMR/ LWR/ 0FFFF 0FFFF
BA1-14 BD0-7 RAML3CS/ RAMHCS/ MEMR/ LWR/ BA14 A RAML1CS/ BA15 B RAML2CS/
G RAML3CS/
74LS139 CEN433 - King Saud University 37 Mohammed Amer Arafah