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Core Architectures Introduction Core Architectures Introduction Purpose • The intent of this module is to explain the advantages of the Hybrid Controller over traditional microcontrollers and DSPs, and to describe the natural progression from the 56800 core to the 56800E core. Objectives • Identify the benefits of the Hybrid Controller over microcontrollers and DSPs. • Identify the MCU and DSP features of the 56800 and 56800E cores. • Describe the enhancements of the 56800E core over the 56800 core. • Describe the underlying 56800E core architecture. Contents • 11 pages • 2 questions Learning Time • 20 minutes In this module, we will explain the advantages of the Hybrid Controller over traditional microcontrollers and Digital Signal Processors (DSPs), and describe the natural progression from the 56800 core to the 56800E core. We will describe the benefits of the Hybrid Controller over microcontrollers and DSPs. We will also outline the MCU and DSP features of the 56800 and 56800E cores. Finally, we will describe the enhancements of the 56800E core over the 56800 core, as well as the underlying core architecture of the 56800E. 1 Hybrid Controller Functionality Roll your mouse pointer over the Traditional Microcontroller and Traditional DSP Engine boxes to learn more. Traditional Traditional DSP Microcontroller Engine Positive Features: Positive Features: • Designed for controller code • Designed for DSP processing • Compact code size • Designed for matrix operations • Easy to program 56800/E Hybrid Controller Negative Features: Negative Features: • Difficult to program • Not efficient for DSP DSP + MCU • Not optimized for control • Instructions optimized for controller code, DSP, matrix operations • Compact assembly and “C” compiled code size • Easy to program • Improved processing power (MIPs) over traditional MCU • Extended addressing space Here, we can see the traditional microcontroller, the traditional DSP engine, and the 56800/E Hybrid Controller. Traditional MCUs and DSPs have both positive and negative features. However, the 56800/E resolves all of the negative features associated with the traditional MCUs and DSPs. Roll your mouse pointer over the Traditional Microcontroller and Traditional DSP Engine boxes to learn more. The 56800E provides a natural roadmap continuation of the first generation 56800 family. It features the unique combination of true DSP and controller functionality. It also has full source code compatibility with the original 56800 core. Its instructions are further optimized for controller code and DSP operations along with extended registers and data modes (byte and long) for compiler efficiency. The 56800/E is as flexible as an MCU and as powerful as a DSP. The core is easy to program and has features that support improved compiler efficiency. The core provides processing speeds up to 200MHz unheard of in the traditional MCU world. The address bus supports an extended addressing range of up to 4MB of program memory and 32MB of data memory providing additional application development flexibility. 2 56800E Features • 1.8V core voltage and lower (based on process migration) • 0.136 mA/MHz power consumption for the core • Single instruction 16x16-bit multiply with 36-bit accumulator • Nested DO loops • Efficient C complier and local variable support • Full scan based test methodology • Up to 200 MIPS/MHz (120 MIPS at 120MHz and beyond) • Supports byte, word, and long data types • Fully source compatible with first generation 56800 architecture • Instruction set that supports both DSP and controller functions • Fast interrupt capability for Level 2 interrupts • Vectored interrupt capability with five priority levels • Enhanced On-Chip Emulation (EOnCE) • Embedded low-cost processor with MCU and DSP functionality • 16-bit instructions (for optimal code density) • 32-bit buses and arithmetic units (for throughput) • 16x16 multiply-accumulator with 36-bit result • 24-bit addressing range for data • 21-bit addressing range for program This is a reference page for the previous page 3 56800/E MCU Functionality Roll your mouse pointer over each feature to learn more. • Efficient C programming True Software • Structured programming • Unlimited function calls Stack and Pointer • Local variable and parameter passing • Stack not limited in size or location by the hardware • Optimal code density 16-bit Program Word • Minimizes the amount of program memory • Any Data Arithmetic Logic Unit (ALU) register can be General Purpose Register Files used as source or destination for arithmetic operations. and Orthogonal Instructions to • Code efficiency Data and Address Register Files • Compiler efficiency • Programming flexibility 56800E: 8, 16, 32-bit Data Types • 56800E: 32-bit Core-global Data Bus (CDBR-CDBW) • 56800: 16-bit Core-global Data Bus (CDBR-CDBW) (supported by instruction set) • More data types give additional code flexibility for 56800: 16-bit Data Type increased programming efficiency. 19 Addressing Modes • Compact code size • Efficient compiler performance Atomic Read-Modify-Write Instructions • Programming ease and flexibility • Non-interruptible bit manipulation instructions Full Set of Bit Manipulation • Dedicated Bit manipulation unit in the core • Efficient control code and peripheral programming Instructions and 16- and • MCU functionality of Hybrid Controller 32-bit Shifting The advanced 56F800E architecture is the successful merger of several types of processors. When the 56800E core was created, it challenged world-class core designers to create a core that incorporated the best points of its 8-bit, 16-bit, and 32-bit MCU cores with the performance of its digital signal processing cores. The designers built on their 56800 core knowledge and succeeded with the 56800E. The result is a core that has the signal processing power of a DSP, the ease of programming of a 16- bit MCU, and 32-bit performance with 16-bit code density. Here, we can see the features that provide the MCU properties found in the 56800 and 56800E cores. 4 56800/E DSP Functionality Roll your mouse pointer over each property for more information. Multiplier - Accumulator (MAC) • Features DSP programmers Single and dual parallel move instructions • Demand for executing true signal processing algorithms No overhead hardware looping • Two hardware supported DO loops Nested looping capability that are also interruptible. • Supports traditional DSP Modulo arithmetic (for circular buffers) mathematical functions for executing Integer and fractional arithmetic support complicated computations 56800E: 5 levels of interrupt priorities • Gives the programmer more control HW Interrupt nesting in interrupt-driven applications Fast Interrupt support 56800: 2 levels of interrupt priorities SW Interrupt nesting Here, we can see the properties of the 56800 and 56800E cores that cause it to have the superior signal processing capability of a DSP. Parallel moves support highly efficient DSP operations. The sum of products used in filtering requires multiply and accumulate and dual parallel moves to fetch the next two vectors. This can be performed in a single instruction due to Harvard Architecture. This is highly efficient! There is a two-deep hardware stack and support for two hardware DO loops. These DO loops are also interruptible. Dedicated modulo registers support auto indexing to the top of circular buffers when the end of the buffer is reached. Integer and fractional arithmetic support by the core instruction set supports traditional DSP mathematical functions. With the 56800E, there are five user-assigned levels of interrupt priorities with hardware- supported nesting. Fast interrupts provide low-latency support for Level 2 interrupts. With the 56800, there are two user-assigned levels of interrupt priorities with software- supported nesting. 5 Question Complete the following sentence. The 56800E core has the signal processing power of a ____________ and the ease of programming of an ____________. • MCU • ALU • MAC • DO loop • DSP Here’s an opportunity to see if you can remember what you have learned so far about the 56800E core. The 56800E core has the signal processing power of a DSP and the ease of programming of an MCU. 6 Programming Model Comparison DATA ARITHMETIC LOGIC UNIT ADDRESS GENERATION UNIT DATA REGISTERS 23 15 0 35 32 31 16 15 0 R0 R0 ==> R0, R1, N, and M01 A A2 A1 A0 R1 R1 registers are shadowed. B B2 B1 B0 R2 15 0 C C2 C1 C0 R3 M01 D D2 D1 D0 R4 M01 R5 MODIFIER REGISTERS Y1 15 0 Y N Y0 N N3 X0 SP SECONDARY OFFSET REGISTER POINTER REGISTERS Here, we can see some of the enhancements of the 56800E core over the 56800 core. In the 56800E core, there are two additional Data registers (C and D), as well as two additional Pointer registers (R4 and R5). The Pointer registers are extended to 24 bits to support a larger memory map. There is also a secondary Offset register (N3). These additional registers increase compiler efficiency by reducing the number of function parameters and variable references that must be accessed from the software stack. 7 Programming Model Comparison PROGRAM CONTROL UNIT 20 15 0 PC PROGRAM COUNTER 15 0 ADDRESS GENERATION UNIT OMR 23 15 0 SR R0 R0 ==> R0, R1, N, and M01 OPERATING MODE and STATUS R1 R1 registers are shadowed. 23 15 0 R2 LA 15 0 LA2 R3 M01M01 LOOP ADDRESS R4 23 15 0 R5 MODIFIER REGISTERS HWS0 15 0 HWS1 N N N3 HARDWARE STACK 15 12 0 SP SECONDARY OFFSET REGISTER LC POINTER REGISTERS LC2 LOOP COUNTER 20 0 FIRA FAST INTERRUPT RETURN ADDRESS 12 0 FISR FAST INTERRUPT STATUS REGISTER Here, we can see more enhancements of the 56800E core over the 56800 core. In the 56800E core, there is a 21-bit Program Counter. There is also a secondary hardware DO loop feature that is supported by the Loop Address (LA2) register and the Loop Counter (LC2) register. The Fast Interrupt feature reduces ISR overhead and can be mapped to any level 2 interrupt vector. Registers dedicated to this feature include shadow registers (R0, R1, N, and M01), the Fast Interrupt Return Address (FIRA) register, and the Fast Interrupt Status Register (FISR). There is also a dedicated return from interrupt with delay instruction (FRTID) to provide the lowest latency and overhead.
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