Coresdlc V3.0 Handbook 3
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CoreSDLC v3.0 Handbook Actel Corporation, Mountain View, CA 94043 © 2010 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 50200269-0 Release: July 2010 No part of this document may be copied or reproduced in any form or by any means without prior written consent of Actel. Actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or fitness for a particular purpose. Information in this document is subject to change without notice. Actel assumes no responsibility for any errors that may appear in this document. This document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of Actel Corporation. Trademarks Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Table of Contents Introduction .............................................. 5 Key Features ..........................................................5 Supported Actel FPGA Families ............................................6 Core Version ..........................................................6 Supported Interfaces ....................................................6 Utilization and Performance ...............................................6 Design Description ........................................ 9 Verilog/VHDL Parameters ................................................9 I/O Signals ...........................................................9 Register Map and Descriptions .............................. 11 Design Details ........................................... 17 Interface Definitions ....................................................17 SDLC Protocol Overview ................................................17 Modes of Operation ....................................................21 General Description of the Transmitter ......................................23 General Description of Receiver ...........................................24 Tool Flows .............................................. 29 Licensing ...........................................................29 SmartDesign .........................................................29 Simulation Flows ......................................................30 Synthesis in Libero IDE .................................................31 Place-and-Route in Libero IDE ............................................31 Ordering Information ...................................... 33 Ordering Codes .......................................................33 Product Support ......................................... 35 Customer Service .....................................................35 Actel Technical Support .................................................35 CoreSDLC v3.0 Handbook 3 Introduction The CoreSDLC macro provides a high-speed synchronous serial communication controller that utilizes the synchronous data link control (SDLC) protocol. Operation of the controller is similar to that used in the Intel 8XC152 global serial channel (GSC) device working in SDLC mode under CPU control. Communication with a CPU is realized through the Advanced Peripheral Bus (APB) interface and three interrupt sources. This enables interfacing CoreSDLC easily with any APB master. CoreSDLC consists of three primary blocks, as shown in Figure 1. CoreSDLC Shift CRC Flag Bit Data PCLK Register Checker Detection Stripping Decoder PRDATA[7:0] PRESETN PSLVERR Recieve PADDR[5:0] Receive PREADY PWDATA[7:0] FIFO TXD PENABLE Address Receive Frame Clock Data Detection Sequencer Recovery TV PSEL RE PWRITE RV RXC Internal Signals PRE RXD APB Interface PRV TXC PTV Data Transmit Frame Sequencer RDN FIFO TDN Transmit DEN Shift CRC Bit Flag Data Register Generator Stuffing Insertion Encoder Figure 1 CoreSDLC Block Diagram Key Features Based on Intel's 8XC152 global serial channel working in SDLC mode Single and double-byte address recognition Address filtering enables multicast and broadcast addresses 16-bit (CRC-16) and 32-bit (CRC-32) frame check sequence NRZ and NRZI data encoding Automatic bit stuffing/stripping 3-byte deep internal receive and transmit FIFOs Full or half-duplex operation Variable BAUD rate External or internal transmit and receive clocks CoreSDLC v3.0 Handbook 5 Introduction Optional preamble generation Programmable interframe space Raw transmit and receive testing modes All major Actel device families supported Supported Actel FPGA Families IGLOO® IGLOOe IGLOO nano IGLOO PLUS ProASIC3E ProASIC3 ProASIC®3L SmartFusion Fusion ProASICPLUS® Axcelerator® RTAX-S SX-A RTSX-SU Core Version This handbook supports CoreSDLC version 3.0. Supported Interfaces CoreSDLC is available with an AMBA 3 APB slave interface. Utilization and Performance CoreSDLC has been implemented in several Actel devices. A summary of CoreSDLC utilization and performance for various devices is listed in Table 1. Table 1 CoreSDLC Device Utilization and Performance Cells or Tiles Utilization Family Performance Sequential Combinatorial Total Device Total Fusion 392 786 1178 AFS250 19% 128 MHz SmartFusion 392 795 1187 A2F200M3F 26% 120 MHz ProASIC3 392 788 1180 A3P250 19% 131 MHz ProASIC3E 392 788 1180 A3PE600 9% 124 MHz ProASIC3L 392 775 1167 A3P250L 19% 97 MHz 6 CoreSDLC v3.0 Handbook Introduction IGLOO 392 792 1184 AGL125V2 39% 51 MHz IGLOOe 392 792 1184 AGLE600V2 9% 54 MHz IGLOO PLUS 392 810 1202 AGLP125V2 39% 48 MHz ProASICPLUS 376 1112 1488 APA150 24% 80 MHz Axcelerator 410 601 1011 AX125 50% 150 MHz RTAX-S 410 600 1010 RTAX250S 24% 112 MHz SX-A 405 556 961 A54SX32A 34% 100 MHz RTSX-SU 405 556 961 RT54SX32S 34% 60 MHz Note: Data in this table were achieved using typical synthesis and layout settings. CoreSDLC v3.0 Handbook 7 Design Description Verilog/VHDL Parameters CoreSDLC has no parameters (Verilog) or generics (VHDL). I/O Signals The port signals for the CoreSDLC macro are shown in Figure 2 and defined in Table 2. PCLK PRDATA[7:0] PRESETN PSLVERR PADDR[5:0] PREADY PWDATA[7:0] TXD PENABLE TV PSEL RE PWRITE CoreSDLC RV PRE RXC PRV RXD PTV TXC RDN DEN TDN Figure 2 CoreSDLC I/O Signal Diagram Table 2 CoreSDLC I/O Signals Port Name Type Description PCLK In APB System clock – Reference clock for all internal logic. PRESETN In APB Active low asynchronous reset. PWDATA[7:0] In APB Write data. PRDATA[7:0] Out APB Read data. PADDR[5:0] In APB Address bus. This port is used to address internal CoreSDLC registers. PENABLE In APB Strobe – indicates the second cycle of an APB transfer. PSEL In APB Slave select – selects CoreSDLC for reads or writes on APB bus. PWRITE In APB Write/Read select signal – If high (logic 1), a write occurs when an APB transfer to CoreSDLC takes place. If low (logic 0), a read from CoreSDLC occurs. PREADY Out APB Ready signal - tied high. PSLVERR Out APB Transfer error signal - tied low. RV Out Receive valid interrupt. CoreSDLC v3.0 Handbook 9 Design Description Port Name Type Description RE Out Receive error interrupt. TV Out Transmit valid interrupt. PRV Out Receive valid interrupt priority. PRE Out Receive error interrupt priority. PTV Out Transmit valid interrupt priority. RXD In Receive input. TXD Out Transmit output. RXC In Receive clock. TXC In Transmit clock. DEN Out Active-low external driver enable. RDN Out Receive done interrupt. TDN Out Transmit done interrupt. Note: All signals are active High (logic 1) unless otherwise noted. 10 CoreSDLC v3.0 Handbook Register Map and Descriptions These sections and Table 4 through Table 25 detail the APB-accessible registers within CoreSDLC. Register Summary Values shown in the tables below are in hexadecimal format; type designations: R = Read only; W = Write only; R/W = Read/Write. Table 3 CoreSDLC Internal Register Address Map Address Register Name Type Width Reset Value Description 0x00 GMOD R/W 8 0x00 GSC Mode 0x04 TFIFO W 8 0xFF Transmit FIFO 0x08 PCON R/W 8 0x00 Power Control 0x0C BAUD R/W 8 0x00 Baud Rate 0x10 ADR0 R/W 8 0x00 Address Match 0 0x14 IFS R/W 8 0x00 Interframe Space 0x18 ADR1 R/W 8 0x00 Address Match 1 0x1C ADR2 R/W 8 0x00 Address Match 2 0x20 ADR3 R/W 8 0x00 Address Match 3 0x24 IEN1 R/W 8 0xC0 Interrupt Enable 0x28 AMSK0 R/W 8 0x00 Address Mask 0 0x2C TSTAT R/W 8 0x04 Transmit Status 0x30 AMSK1 R/W 8 0x00 Address Mask 1 0x34 RSTAT R/W 8 0x00 Receive Status 0x38 RFIFO R 8 0xFF Receive FIFO 0x3C IPN1 R/W 8 0xC0 Interrupt Priority GSC Mode Register (GMOD) Table 4 GSC Mode Register PADDR[6:0] Register Name Type Width Reset Value Description 0x00 GMOD R/W 8 0x00 GSC Mode Table 5 GSC Mode Register Bit Functions Bits Name Type Description 7 xtclk R/W External transmit clock 1 – External clock and NRZ encoding used by transmitter 0 – Internal clock generator and NRZI encoding used by transmitter CoreSDLC v3.0 Handbook 11 Register Map and Descriptions Bits Name Type Description 6:5 m1 R/W Mode select m0 00 – Normal 01 – Raw transmit 10 – Raw receive 11 – Not allowed 4 a1 R/W Address length 1 – 16-bit addressing is used 0 – 8-bit addressing is used 3 ct R/W The CRC type 1 – 32-bit CRC is used 0 – 16-bit CRC (CRC-CCITT) is used 2:1 pl1 R/W Preamble length pl0 00 – 0-bit 01 – 8-bits 10 – 32-bits 11 – 64-bits 0 – – Not used Transmit FIFO Register (TFIFO) Table 6 Transmit FIFO Register PADDR[6:0] Register Name Type Width Reset Value Brief Description 0x04 TFIFO W 8 0x00 Transmit FIFO The TFIFO register represents the