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Designing with Smartfusion Intelligent Mixed Signal Fpgas Webinar ™ Designing with SmartFusion Wendy Lockhart Sr. Manager, Design Solutions Agenda SmartFusion Overview SmartFusion Design Flows Embedded design FPGA design Analog design MSS Configurator and Embedded Example Ecosystem SmartFusion Design Hardware Actel Corporation © 2010 2 What is SmartFusion? Actel Corporation © 2010 3 SmartFusion: Innovative, Intelligent, Integration Proven FPGA fabric Complete ARM® Cortex™-M3 MCU subsystem...& it’s ‘hard’ Programmable analog In a flash-based device In production now! Actel Corporation © 2010 4 Why SmartFusion is a Smart Decision No-compromise integration Complete ARM Cortex-M3 subsystem running at 100 MHz Proven flash-based FPGA fabric Programmable high-voltage analog Full customization Design the exact system you need Hardware and software co-design IP protection FlashLock® technology with AES encryption Ease-of-use Optimized for hardware and software co-design Actel Corporation © 2010 5 No-Compromise FPGA Fabric Proven flash-based FPGA fabric 60,000 to 500,000 system gates 350 MHz system performance Embedded SRAMs and FIFOs Up to 128 FPGA I/Os Actel Corporation © 2010 6 No-Compromise Microcontroller Subsystem (MSS) 100 MHz 32-bit ARM Cortex-M3 processor Bus matrix with up to 16 Gbps throughput 10/100 Ethernet MAC SPI, I2C, UART, 32-bit Timers Up to 512 KB flash and 64 KB of SRAM External memory controller 8-channel DMA controller 32 GPIOs; Extendable via the FPGA Fabric Up to 41 MSS I/Os Actel Corporation © 2010 7 Programmable Analog Analog compute engine (ACE) offloads CPU from analog tasks Voltage, current and temp monitors 12-bit (SAR) ADCs @ up to 600 Ksps Sigma-Delta DACs Up to ten 50 ns high-speed comparators Up to 32 analog inputs and 3 outputs Actel Corporation © 2010 8 Innovative Intelligent Integration Actel Corporation © 2010 9 SmartFusion: New Level of Design SmartFusion is the combination of FPGA, hard ARM Cortex-M3 and Programmable Analog Therefore we address three types of design FPGA Design Embedded Design Analog Design The designers may be three individuals or more likely two Have to address expectations of each type Have to simplify analog usage for any user Have to provide full capabilities of each traditional design flow Actel Corporation © 2010 10 SmartFusion Design Flow Actel Corporation © 2010 11 Embedded Design - Design Entry C/C++, Drivers, Hard Peripherals Design Entry Providing source code, drivers and examples speed time to market Build Options Partners for Middleware and OS Support Build Configure device with MSS configurator Simulation Automatically generate firmware drivers and sample code Download Debug Actel Corporation © 2010 12 Embedded Design – Convert to Target Device Compiler, Builder, Linker Design Entry The quality of the compiler affects performance of the Build Options design and size of code space required Build SoftConsole includes GNU GCC Simulation Keil MDK includes RealView C/C++ Download IAR Workbench includes IAR ARM Compiler Debug Actel Corporation © 2010 13 Embedded Design - Verification and Debug Debugger, SW Breakpoints, Design Entry A large amount of time is spent in debug iterations, so ease of Build Options use is critical SoftConsole includes GNU GDB Build debug Simulation Keil includes μVision Debugger Download IAR includes C-SPY Debugger Debug Actel Corporation © 2010 14 FPGA Design - Design Entry RTL, IP Cores, Soft Peripherals Design Entry Graphical design entry helps integrate IP and RTL design blocks for ease of use Synthesis Select IP cores from catalog SmartDesign auto connects recognized ports Layout Verification Programming Debug Actel Corporation © 2010 15 FPGA Design - Convert to Target Device Synthesis, Place and Route Design Entry Using device specific features improves design efficiency and Synthesis performance Synplicity Synthesis from Layout Synopsys automatically instantiates standard features Verification Timing Driven Layout optimizes for performance Programming Power Driven Layout optimizes for power Debug Actel Corporation © 2010 16 FPGA Design - Verification and Debug Simulation, Testbench, Probe points Design Entry Verifying designs early in the flow helps reduce cycle time Use functional and post layout Synthesis Modelsim simulation from Mentor Graphics Perform timing analysis for clock Layout frequencies Reduce power consumption with power analysis and power driven Verification layout Programming Debug Actel Corporation © 2010 17 Simplifying Analog Design Configuring the Analog Compute Engine Voltage Monitor Current Monitor Temperature Monitor Sample Sequence Actel Corporation © 2010 18 SmartFusion Design Flow FPGA Design Use Actel traditional design tools evolved over many years and users Embedded Design Use Industry standard Embedded design tools and IP Analog Design Develop graphical analog configurators that are intuitive but provide full design flexibility Actel Corporation © 2010 19 MSS Configurator and Embedded Design Flow MSS Configurator Usage Provides a common method to configure MSS Allows sharing of MSS configuration between designers Allows Embedded designer to work without using FPGA design flow Actel Corporation © 2010 21 Relating the Device to the Configurator Actel Corporation © 2010 22 MSS Configurator Configure the MSS peripherals and I/Os Create or import hardware configuration Automatically generate drivers for peripherals Configure programmable analog components Enables connection of FPGA fabric designs MSS configurator enables and IP to MSS co-design between multiple users Actel Corporation © 2010 23 New Embedded Design Flow MSS Configurator Take the standard Code Entry Embedded Design Flow Compiler Add the ability to configure your peripherals Assembler Auto generate memory Linker map Simulation Auto generate sample code and drivers Load Debug Actel Corporation © 2010 24 MSS Configurator Launch from your Embedded Software IDE So far supports GNU (SoftConsole), Keil and IAR . Can be setup in each one as External tool Launch from software IDE or standalone Generate drivers for selected software IDE Generates sample code projects for selected software IDE Actel Corporation © 2010 25 Starting From Software IDE - SoftConsole Actel Corporation © 2010 26 Invoking MSS Configurator Actel Corporation © 2010 27 Replicates Device Block Diagram Actel Corporation © 2010 28 MSS Clock Configurator Actel Corporation © 2010 29 Analog Configuration Configuring the analog Compute Engine Voltage Monitor Current Monitor Temperature Monitor Actel Corporation © 2010 30 SmartFusion I/Os: Very Flexible 3 Types of I/Os Some I/Os are MUXed FPGA MSS Analog Actel Corporation © 2010 31 GPIO Configuration Dialog Actel Corporation © 2010 32 Re-use I/O from Unused Peripherals Actel Corporation © 2010 33 Control MSS I/O Options Directly Actel Corporation © 2010 34 Generate Drivers and Sample Code Actel Corporation © 2010 35 Program the Configuration to the Device Many device configurations do not require FPGA flow Only GPIO extension through the FPGA fabric The MSS Configurator also creates the System Boot Continue with Embedded design after device configuration Standard program and debug performed Through FlashPro for SoftConsole Through J-Link or U-Link interfaces for Keil and IAR Actel Corporation © 2010 36 Embedded Design Complete Once you have your device configured You can work directly with the Cortex-M3 But we have ignored the FPGA What if I now want to add 2 more UARTs to my system And a high performance timer Actel Corporation © 2010 37 FPGA Design Made Easy From the FPGA design side The Microcontroller subsystem is treated as block IP And APB3 bus can be used to connect the MSS to the FPGA Fabric Add peripherals such as UART, GPIO and Timers SmartDesign auto connects recognized signals Actel Corporation © 2010 38 Successful Integration Combining Hard ARM Cortex-M3 Processor Full set of peripherals On chip NVM and SRAM With full feature FPGA And Programmable Analog Actel Corporation © 2010 39 Leads to Easy to Use Design Flow Start Embedded design before FPGA completion Clear definition of MSS Boundaries and memory map Ability to use industry standard compile and debug Ability to port RTOS and middleware for Cortex-M3 Standard Program and Debug interfaces With the ability to add peripherals when need to the FPGA Actel Corporation © 2010 40 SmartFusion Software Stack and Ecosystem www.actel.com/products/smartfusion/ecosystem.aspx SmartFusion Software Stack Application Layer Customer Secret Sauce Middleware TCP/IP, HTTP, SMTP, DHCP, LCD OS/RTOS µC/OS-III, RTX, Unison, FreeRTOS Drivers C Driver 2 I SPI Driver Timer Driver Timer UART Driver UART eNVM Driver Ethernet Driver Hardware Abstraction Layer Actel CMSIS-based HAL Hardware Platform Actel SmartFusion SmartFusion stack accelerates application development Actel Corporation © 2010 42 Ecosystem Partners: Still Growing Actel HAL, drivers and IDE ARM Cortex-M3 processor Leverage ARM ecosystem RTOS GNU, Keil and IAR Compilers and debuggers Micrium, RoweBots OS and middleware Compile/ EDA Debug Mentor and Synopsys Synthesis, simulation and debug Actel Corporation © 2010 43 ARM Ecosystem Linked through our website Instruction Set documentation Design Examples Design recommendations ARM Cortex-M3 Training resources Both ARM or third party available IP for existing Cortex-M3 implementations Easy to port to our architecture Dependent on peripherals needed CMSIS Cortex Microcontroller Software Interface
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