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Introduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX

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Introduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX Outline ®Introduction ®Actel Logic Modules ®Xilinx LCA CPE 528: Session #12 ®Altera FLEX, Altera MAX ®Power Dissipation Department of Electrical and Computer Engineering University of Alabama in Huntsville 13/02/2003 UAH-CPE528 2 Introduction Actel ACT ® Basic internal structure ®Actel ACT basic logic cell – Logic Module ® PLB – Programmable Logic Blocks ® Actel ACT 1 uses just one type of ® PI – Programmable Interconnect Logic Module ® Types of basic logic cells ® Actel ACT 2 and 3 use two different types ® (1) multiplexer based of Logic Modules ® (2) look-up table based, and ® (3) programmable array logic 13/02/2003 UAH-CPE528 3 13/02/2003 UAH-CPE528 4 •1 ACTEL Act 1 Logic Module Shannon Expansion Theorem ® (a) Organization of the basic logic cells. (b)The ACT 1 ® Expansion Logic Module. (c) An implementation using pass F = F · 1 = F · (A + A’)= F · A + F · A‘ transistors (without any buffering). (d) An example logic ® Example: expand F with respect to A macro. (Source: Actel.) F = A' · B + A · B · C' + A' · B' · C = A · (B · C') + A' · (B + B' · C) ® cofactor F wrt A = B · C‘, cofactor F wrt A’ = B + B' · C ® F with respect to B F = B · (A' + A · C') + B' · (A' · C) ® We can continue to expand a function until we reach the canonical form – a unique representation that uses only minterms ® minterm is a product term that contains all the variables of F 13/02/2003 UAH-CPE528 5 13/02/2003 UAH-CPE528 6 An Example Multiplexer Logic as Function Generators ® F = (A · B) + (B' · C) + D ®Logic functions of 2 variables = (A · B) + (B' · C) + [D ·(B + B’)] = B·(A+D) + B’·(C+D) = B·F2 + B’·F1 ® F2 = A + D = A + D·(A + A’) = A + A’·D = A·1 + A’·D ® F1 = C + D = C + D·(C + C’) = C + C’·D = C·1 + C’·D ® Implementation ® A0 = D, A1 = 1, SA = C (F1) ® B0 = D, B1 = 1, SB = A (F2) ® S0 = 0, S1 = B ® 10 functions of these 16 can be implemented using just one 2:1 multiplexer (See Table 5.1 of the textbook) 13/02/2003 UAH-CPE528 7 13/02/2003 UAH-CPE528 8 •2 Multiplexer Logic as Function Generators (cont’d) Multiplexer Logic as Function Generators (cont’d) ®Useful functions ® INV. The MUX acts as an inverter for one input only. ® BUF. The MUX just passes one of the MUX inputs directly to the output. ® AND. A two-input AND. ® OR. A two-input OR. ® AND1-1. A two-input AND gate with inverted input, equivalent to an NOR-11. ® NOR1-1. A two-input NOR gate with inverted Figure 5.3 The ACT1 logic module as a boolean function generator. input, equivalent to an AND-11. (a) A 2:1 MUX viewed as a logic wheel. (b) The ACT1 logic module viewed as two function wheels. 13/02/2003 UAH-CPE528 9 13/02/2003 UAH-CPE528 10 An Example ACT 2 and ACT 3 Logic Modules ® F = NAND(A, B) Figure 5.4 The ACT2 and ® ACT3 logic modules. F = (A · B)’ = A’ + B' = A’ + B’·(A’ + A) (a) The C-module. = A’ + B’· A = 1·A’ + B’·A (b) The ACT2 S-module. (c) The ACT3 S -module. ® Implementation (d) The equivalent circuit of the SE. ® Wheel 1 => 1 (A0 = 1, A1 = 1, SA = 1) (e) The SE configured as ® Wheel 2 => B’ (B0 = 1, B1 = 0, SB = B) a positive edge-triggered D flip-flop. ® MUX (1, B’, A) => S0 = A, S1 = 0 ® Note: We do not have to worry how to use Logic Modules to construct combinational logic functions – e.g., we use NAND2 gate symbol and software takes care of connecting the inputs in the right way to the Logic Module 13/02/2003 UAH-CPE528 11 13/02/2003 UAH-CPE528 12 •3 Timing Model and Critical Path Worst-case timing ® Exact delay values in Actel ® FPGAs can not be determined Max delays in CMOS occur when until interconnect delay is known ® operating under minimum voltage – ® maximum temperature i.e., place and route are done ® slow-slow process conditions (process variation which results ® Critical path delay between in slow p-channel and slow n-channel transistors) registers is: t + t + t PD SUD CO ® Electronic Equipment classes ® There is also a hold time for ® Commercial. VDD = 5 V ± 5 %, T A (ambient) = 0 to +70 °C. the flip-flops - tH ® Industrial. VDD = 5 V ± 10 %, T A (ambient) = –40 to +85 °C. ® The combinational logic delay tPD is dependent on the logic function ® Military: VDD = 5 V ± 10 %, T C (case) = –55 to +125 °C. (which may take more than one ® Military: Standard MIL-STD-883C Class B. LM) and the wiring delays ® Military extended: Unmanned spacecraft. ® The flip-flop output delay t can CO ® Tj – junction temperature => also be influenced by the number of gates it drives (fanout ) temperature of the transistors on the chip ® to calculate this we need power dissipated and thermal properties of the package 13/02/2003 UAH-CPE528 13 13/02/2003 UAH-CPE528 14 Xilinx LCA XC3000 CLB ® Xilinix LCA (Logic Cell Array) Configurable Logic Blocks (CLBs) ® bigger and more complex than the Actel cells => coarse-grain architecture ® XC3000 CLB inputs ® five logic inputs (A-E) ® common clock input (K) ® asynchronous direct-reset input (RD) ® enable clock (EC) ® XC3000 CLB outputs ® X, Y ® Using programmable MUXes connected to the SRAM programming cells we can independently connect each of the two CLB outputs to the outputs of flip-flops (QX, QY) or to the output of the combinational logic (F, G) Figure 5.6 The XilinxXC3000 CLB (configurable logic block). 13/02/2003 UAH-CPE528 15 13/02/2003 UAH-CPE528 16 •4 XC3000 CLB (cont’d) XC3000 CLB (cont’d) ® LUT – Look-Up Table ® Combinational block inputs/outputs ® 32-bit LUT stored in 32 bits of SRAM ® CLB inputs (A-E) ® flip-flop outputs (QX, QY) ® Suppose we need to implement the function F, ® outputs from the LUT (F, G) F = A·B·C·D·E ® Using LUT ® set the content of LUT cell number 31 to 1 ® use five of seven inputs with the entire 32-bit LUT ® clear the content of all other LUT cells (0 – 30) => CLB outputs F and G are identical ® apply the input variables as an address to the SRAM ® ® only when ABCDE = ‘11111’ the output F will be ‘1’ split the 32-bit LUT in half to implement two functions (outputs F and G) of four variables each ® CLB propagation delay is fixed, equal to LUT access ® we can choose four input variables (A-E, QX, QY) time and does not depend on the function implemented ® we have to choose two from the five CLB inputs (A-E) ® split the 32-bit LUT in half, using one of seven input variables as a select input for a 2:1 MUX that switches between F and G 13/02/2003 UAH-CPE528 17 13/02/2003 UAH-CPE528 18 XC4000 Logic Block XC4000 Logic Block ® Two four-input LUTs that feed a three-input LUT ® Special fast carry logic hard-wired between CLBs ® MUX control logic maps four control inputs C1-C4 into the four inputs: ® LUT input (H1) ® direct in (DIN) ® enable clock (EC) ® set/reset control for flip-flops (S/R) ® Control inputs C1-C4 can also be used to control the use of the F’ and G’ LUTs as 32 bits of SRAM Figure 5.7 The XilinxXC4000 CLB (configurable logic block). 13/02/2003 UAH-CPE528 19 13/02/2003 UAH-CPE528 20 •5 XC5200 Logic Block Xilinx CLB Analysis ® Basic Cell is called a Logic Cell (LC) and is similar to, ® Using LUTs to implement combinational logic but simpler than, CLBs in other Xilinxfamilies ® Term CLB is used here to mean a group of 4 LCs (LC0-LC3) ® Disadvantage: an inverter is as slow as a five input NAND ® Advantage: simplifies timing Figure 5.8 The Xilinx XC5200 LC (logic cell) and CLB (configurable logic block). 13/02/2003 UAH-CPE528 21 13/02/2003 UAH-CPE528 22 Altera FLEX (8000) Altera MAX ® Basic Cell is called a Logic Element (LE) and ® Two-level logic resembles the Xilinx XC5200 LC architecture circuit (sum of ® Altera FLEX uses the same SRAM programming technology as Xilinx products) ® Using regular structure ® vector of buffers ® vector of AND gates Figure 5.10 The Altera FLEX architecture. (a) Chip floorplan . ® OR gates (b) LAB (Logic Array Block). (c) Details of the LE (logic element). 13/02/2003 UAH-CPE528 23 13/02/2003 UAH-CPE528 24 •6 Altera MAX (cont’d) Altera MAX (cont’d) ® (a) Two-level logic ® Programmed EPROM transistor has no effect circuit (sum of on the product-term products) line ® (c) Programmable ® Unprogrammed Array Logic (PAL) EPROM acts as a pull- down tran. ® Horizontal line: product term line (bit line) ® Vertical line: word line 13/02/2003 UAH-CPE528 25 13/02/2003 UAH-CPE528 26 Registered PAL Logic Expanders ® A logic expander is an output line of the AND array that feeds back as an input to the array itself ® Logic expanders can help implement functions that require more product terms than are available in a simple PAL ® Consider implementing this function in in a three-wide OR array: F = A’ · C · D + B’ · C · D + A · B + B · C’ ® This can be rewritten as a “sum of (products of products): F = (A’ + B’) · C · D + (A + C’) · B F = (A · B)’ (C · D) + (A’ · C)’ · B ® Logic expanders can be used to form the expander terms (A · B)’ and (A’ · C)’ Figure 5.12 A registered PAL with I inputs, j product terms, and k macrocells.
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