Actel Smartfusion Microcontroller Subsystem User's Guide

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Actel SmartFusion™ Microcontroller Subsystem User’s Guide Actel Corporation, Mountain View, CA 94043 © 2010 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 50200250-1 Release: May 2010 No part of this document may be copied or reproduced in any form or by any means without prior written consent of Actel. Actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or fitness for a particular purpose. Information in this document is subject to change without notice. Actel assumes no responsibility for any errors that may appear in this document. This document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of Actel Corporation. Trademarks Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel SmartFusion Microcontroller Subsystem User’s Guide Table of Contents SmartFusion Microcontroller Subsystem (MSS) User’s Guide 1 ARM Cortex-M3 Microcontroller . -7 Cortex-M3 SysTick Timer . 8 Interrupts . 10 2 AHB Bus Matrix. -15 Functional Description . 15 Arbitration . 17 System Memory Map . 19 The Boot Process . 23 AHB Bus Matrix Register Map . 24 3 Peripheral DMA (PDMA) . -35 PDMA Features . 35 Functional Description . 35 Ping-Pong Mode . 36 Posted APB Writes . 37 Memory to Memory Transfers . 37 Channel Priority . 37 System Dependencies . 38 PDMA Register Map . 39 4 Embedded Nonvolatile Memory (eNVM) Controller . -47 Memory Organization . 49 Read Next Operation . 53 Write Operations . 55 Reading/Writing to the Aux Block section(s) . 57 eNVM Block Protection . 57 eNVM Commands . 58 Programming Errors . 60 Clocks . 61 Resets . 61 Interrupts . 62 eNVM Controller Register Map . 62 5 SmartFusion Embedded FlashROM (eFROM) . -73 Architecture of the Embedded FlashROM (eFROM) . 73 Reading the eFROM Contents via the MSS . 74 6 Embedded SRAM (eSRAM) Memory Controllers . -79 Misaligned Addresses . 80 7 External Memory Controller . -81 Main Features . 81 Naming Convention . 81 Block Diagram . 82 Revision 1 Table of Contents Functional Description . 83 FCLK Cycles and EMC Phases . 85 EMC Memory Map . 86 External Memory Device Examples . 92 External Memory Controller Configuration . 95 Timing . 100 External Memory Controller I/Os . 107 8 PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators . -109 Functional Description . 109 Input Clock Selection . 111 PLL Configuration . 114 Glitchless MUX (NGMUX) . ..

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