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Quality Decision for Overcharged Li Ion Battery from Reliability and Safety Perspective
Quality Decision for Overcharged Li Ion Battery from reliability and safety perspective Feng Leng 1,2, Cher Ming Tan 1,2,*, Rachid Yazami 2,3, Kenza Maher 3, Robert Wang1 1 Nanyang Technological University, School of Electrical Electronics Engineering, Blk S2.1, 50 Nanyang Avenue, Singapore 639798, (Singapore) Email: [email protected] Email: [email protected] Email: [email protected] 2 TUM CREATE PTE LTD, 1 Create Way, #10-02 Create Tower, Singapore 138602, (Singapore) 3 Nanyang Technological University, School of Materials Science and Engineering and Research Institute at Nanyang (ERIAN), Research Techno Plaza, X-Frontier Blk, 50 Nanyang Drive, Singapore 637553, (Singapore) Email: YAZAMI [email protected] Email: Maher [email protected] Abstract During charging of Lithium-ion battery (LiB), the charging cut-off voltage (COV) may exceed the manufacturers’ specification because of incorrect monitoring of the charging control circuit, either due to the ageing of the control circuit or the design/manufacturing errors of the control circuit. In fact, it is found that overcharging LiB cell is a common abuse. This work shows the effect of excessive COV on cell’s discharging ability, and the use of a novel non-destructive method to evaluate if the damage made in the cell by the excessive COV is rendering the cell from further safe usage or it is still acceptable with minor degradation in reliability and safety, thus providing a basis for quality consideration of the cell. The method also enables battery manufacturers to identify the internal components for their cells that are most vulnerable to the excessive COV so that quality improvement of their batteries can be designed and produced. -
Mobility Enhancement of Strained Si Transistors by Transfer Printing on Plastic Substrates
OPEN NPG Asia Materials (2016) 8, e256; doi:10.1038/am.2016.31 www.nature.com/am ORIGINAL ARTICLE Mobility enhancement of strained Si transistors by transfer printing on plastic substrates Wonho Lee1, Yun Hwangbo2, Jae-Hyun Kim2 and Jong-Hyun Ahn1 Strain engineering has been utilized to overcome the limitation of geometric scaling in Si-based thin-film transistor (TFT) technology by significantly improving carrier mobility. However, current strain engineering methods have several drawbacks: they generate atomic defects in the interface between Si and strain inducers, they involve high-cost epitaxial depositions and they are difficult to apply to flexible electronics with plastic substrates. Here, we report the formation of a strained Si membrane with oxidation-induced residual strain by releasing a host Si substrate of a silicon-on-insulator (SOI) wafer. The construction of the suspended Si/SiO2 structures induces 40.5% tensile strain on the top Si membrane. The fabricated TFTs with strained Si channels are transferred onto plastics using a roll-based transfer technique, and they exhibit a mobility enhancement factor of 1.2–1.4 compared with an unstrained Si TFT. NPG Asia Materials (2016) 8, e256; doi:10.1038/am.2016.31; published online 25 March 2016 INTRODUCTION substrates. A strained Si nanomembrane is fabricated by releasing the A critical path in the development of advanced silicon electronics bilayer of Si and SiO2 from the host Si layer of a silicon-on-insulator involves a reduction in the dimensions of device geometries such as (SOI) wafer. The oxidation-induced compressive strain in the SiO2 the channel thickness, channel length and gate dielectric thickness to layer of the SOI wafer is activated by forming a suspended structure increase the operating speed with lower power consumption and via the etching of the host Si that leads to planar expansion of the 1–4 the density of integration in circuits. -
Stress Mapping in Strain-Engineered Silicon P-Type MOSFET Device: a Comparison Between Process Simulation and Experiments Christophe Krzeminski
Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments Christophe Krzeminski To cite this version: Christophe Krzeminski. Stress mapping in strain-engineered silicon p-type MOSFET device: A com- parison between process simulation and experiments. Journal of vaccum Science and Technology B, 2012, 30 (2), pp.022203-1. 10.1116/1.3683079. hal-00624131 HAL Id: hal-00624131 https://hal.archives-ouvertes.fr/hal-00624131 Submitted on 13 Feb 2012 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. APS/xxxxx Stress mapping in strain-engineered silicon pMOSFET device using process simulation C. Krzeminski1 Institut d’Electronique de Micro´electronique et de Nanotechnologie (IEMN-UMR CNRS 8520), D´epartement ISEN, Avenue Poincar´e, 59650 Villeneuve d’Ascqa) Strain engineering is the main technological booster used by semiconductor companies for the 65 and 45nm technology nodes to improve the channel mobility and the electrical performance of logic devices. For 32 and 22nm nodes, intense research work focuses on the integration and optimisation of these different techniques by cumulating the effects of different stressors. To estimate the level and the distribution of the stress field generated in the transistor channel by such multiple processing steps is a complex issue. -
Strain Engineering for Advanced Transistor Structure
STRAIN ENGINEERING FOR ADVANCED TRANSISTOR STRUCTURE TAN KIAN MING NATIONAL UNIVERSITY OF SINGAPORE 2008 STRAIN ENGINEERING FOR ADVANCED TRANSISTOR STRUCTURE TAN KIAN MING (B. ENG. (HONS.)), NUS (M. ENG.), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTING ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2008 Acknowledgements First and foremost, I would like to thank my supervisor, Dr. Yeo Yee-Chia who has provided much support and encouragement throughout the course of my Ph.D candidature. I have benefited a lot from the numerous discussions that we have. I would also like to thank all my co-supervisors, A/P Yoo Won Jong, Dr Lap Chan, Dr Narayanan Balasubramanian and Dr Patrick Lo who have always been generous in helping me in whatever ways they can. In addition, I will also like to thank A/P Ganesh S. Samudra for giving his advice and suggestions during our research group meetings. Special thanks to Dr Yang Mingchu for constantly provide the support and help, which we need in using the FCVA system. My work is mainly done in 2 laboratories in this period of time, Semiconductor Processing Technology (SPT) Lab at the Institute of Microelectronics (IME), and the Silicon Nano Device Lab (SNDL) at the National University of Singapore (NUS). I am very grateful to all the staffs in both laboratories as they have provided assistance in one way or another which made my work possible. I have also learnt a lot from the friends that I have made from Chartered, SNDL and IME. In particularly, I am extremely thankful that the development of FinFET process flow is done together with Tsung-Yang (Jason). -
Maximizing Uniaxial Tensile Strain in Large-Area Silicon-On-Insulator Islands on Compliant Substrates ͒ R
JOURNAL OF APPLIED PHYSICS 100, 023537 ͑2006͒ Maximizing uniaxial tensile strain in large-area silicon-on-insulator islands on compliant substrates ͒ R. L. Petersona Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 K. D. Hobart Naval Research Laboratory, Washington, DC 20375 H. Yin Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 F. J. Kub Naval Research Laboratory, Washington, DC 20375 J. C. Sturm Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 ͑Received 24 November 2005; accepted 3 May 2006; published online 31 July 2006; publisher error corrected 27 September 2006͒ Recently we have demonstrated a process for generating uniaxial tensile strain in silicon. In this work, we generate uniaxially strained silicon and anisotropically strained silicon germanium on insulator with strain in both ͗100͘ and ͗110͘ in-plane directions. The strain is uniform over fairly large areas, and relaxed silicon-germanium alloy buffers are not used. The magnitude of uniaxial strain generated by the process is very dependent on the in-plane crystal direction, and can be modeled accurately using the known mechanical properties of silicon and germanium. A maximum uniaxial silicon strain of 1.0% in the ͗100͘ direction is achieved. Numerical simulations of the dynamic strain generation process are used to identify process windows for achieving maximum uniaxial silicon strain for different structural geometries. -
Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes
Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes By Deborah Marie Paskiewicz A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Materials Science) at the UNIVERSITY OF WISCONSIN-MADISON 2012 Date of final oral examination: 11/14/12 The dissertation is approved by the following members of the Final Oral Committee: Max G. Lagally, Professor, Materials Science and Engineering Mark A. Eriksson, Professor, Physics Thomas F. Kuech, Professor, Chemical and Biological Engineering Paul G. Evans, Associate Professor, Materials Science and Engineering Irena Knezevic, Associate Professor, Electrical and Computer Engineering ©Copyright by Deborah Marie Paskiewicz 2012 All Rights Reserved i Abstract Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes Deborah M. Paskiewicz Under the supervision of Professor Max G. Lagally At the University of Wisconsin-Madison Strain in crystalline materials alters the atomic symmetry, thereby changing materials properties. Controlling the strain (its magnitude, direction, extent, periodicity, symmetry, and nature) allows tunability of these new properties. Elastic strain engineering in crystalline nanomembranes (NMs) provides ways to induce and relax strain in thin sheets of single- crystalline materials without exposing the material to the formation of extended defects. I use strain engineering in NMs in two ways: (1) elastic strain sharing between multiple layers using the crystalline symmetry of the layers to induce unique strain distributions, and (2) complete elastic relaxation of single-crystalline alloy NMs. In both cases, NM strain engineering methods enable the introduction of unique strain profiles or strain relaxation in ways not compatible with conventional bulk processing, where strain destroys the long-range crystallinity. -
UCLA Electronic Theses and Dissertations
UCLA UCLA Electronic Theses and Dissertations Title SnO2/Graphene Nanocomposites as High-Capacity Anode Materials for Lithium-Ion Batteries: Synthesis and Electrochemical Performance Permalink https://escholarship.org/uc/item/41g3q26f Author Zhu, Xiuming Publication Date 2018 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California UNIVERSITY OF CALIFORNIA Los Angeles SnO2/Graphene Nanocomposites as High-Capacity AnoDe Materials For Lithium-Ion Batteries: Synthesis anD Electrochemical Performance A thesis submitteD in partial satisfaction oF the requirements For the Degree Master oF Science in Materials Science anD Engineering by Xiuming Zhu 2018 © Copyright by Xiuming Zhu 2018 ABSTRACT OF THE DISSERTATION SnO2/Graphene Nanocomposites as High-Capacity AnoDe Materials For Lithium-Ion Batteries: Synthesis anD Electrochemical Performance by Xiuming Zhu Master oF Science in Materials Science anD Engineering University oF CaliFornia, Los Angeles, 2018 ProFessor Bruce S. Dunn, Chair Lithium ion batteries as a poWer source are the most commonly useD in the electronic Devices anD electric vehicles (EV) For griD-energy storage. AnoDe materials With high speciFic capacity For lithium ion batteries have been DevelopeD in recent years. SnO2 has also been consiDereD as a promising canDiDate to serve as the anoDe material For lithium ion batteries Due to its high theoretical capacity. But the volume expansion eFFect results in the DegraDation oF active material anD limits the complete realization oF theoretical capacity. Graphene has recently become one oF the most promising matrices For high-capacity anode materials, due to gooD electrical conDuctivity, outstanDing mechanical Flexibility and high theoretical capacity. In this paper, the nanocomposites of SnO2 and graphene as anoDe materials For lithium ion batteries Were Facilely synthesizeD through hydrothermal methoD. -
A Survey on Multi Gate MOSFETS
ISSN (Online) : 2319 - 8753 ISSN (Print) : 2347 - 6710 International Journal of Innovative Research in Science, Engineering and Technology Volume 3, Special Issue 3, March 2014 2014 International Conference on Innovations in Engineering and Technology (ICIET’14) 21st & 22nd March Organized by K.L.N. College of Engineering, Madurai, Tamil Nadu, India A Survey on Multi Gate MOSFETS B.Buvaneswari Department Of CSE , K.L.N College of engineering ,Madurai, , India (small MOSFETs demonstrate higher outflow currents, ABSTRACT— This paper presents the various device and lower output resistance). A multigate device or structure of MOSFETs like SOI-MOSFET, Double gate multiple gate junction transistor (MuGFET) refers to a Mosfet, Trigate mosfet, Multigate mosfet ,Nanowire MOSFET (metal–oxide–semiconductor field-effect Mosfets,High-K Mosfets& their deserves. To grasp transistor) which includes quite one gate into a sole during a easy means, mathematical ideas of device device. The multiple gates could also be controlled by physics skipped. one gate.conductor, whereby the multiple gate surfaces act electrically as one gate, or by freelance gate INDEX TERMS-DG-MOSFET, GAA, MuG electrodes. A multigate device using freelance gate MOSFETS. electrodes is usually referred to as a Multiple Insulated Gate Field impact electronic transistor (MIGFET). Multigate transistors square measure one in every of I.INTRODUCTION quite an few ways being developed by CMOS semiconductor makers to form ever-smaller Over the past decades, the Metal oxide Semiconductor microprocessors and memory cells, conversationally (MOSFET) has repeatedly been scaled down in size[1]; spoken as extending Moore's Law.[1]Development classic MOSFET channel lengths were once many efforts into multigate transistors are reported by AMD, micrometers, however fashionable integrated circuits Hitachi, IBM, Infineon Technologies, Intel Corporation, square measure incorporating MOSFETs with channel TSMC, Free scale Semiconductor, University of lengths of tens of nanometers. -
Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain
coatings Article Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain Eunjung Ko 1,2, Juhee Lee 1,2, Seung-Wook Ryu 2, Hyunsu Shin 1, Seran Park 1 and Dae-Hong Ko 1,* 1 Department of Material Science and Engineering, Yonsei University, Seoul 03722, Korea; [email protected] (E.K.); [email protected] (J.L.); [email protected] (H.S.); [email protected] (S.P.) 2 R&D Division, SK Hynix Inc., Icheon-si 17336, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-2-2123-2853; Fax: +82-2-312-5375 Abstract: Silicon german ium (SiGe) has attracted significant attention for applications in the source/drain (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs). However, in SiGe, as the Ge concentration increases, high-density defects are generated, which limit its applications. Therefore, several techniques have been developed to minimize defects; however, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. This study examined the effect of Ge concentration on the embedded SiGe source/drain region of a logic p-MOSFET. The strain was calculated through nano-beam diffraction and predictions through a simulation were compared to understand the effects of stress relaxation on the change in strain applied to the Si channel. When the device performance was evaluated, the drain saturation current was approximately 710 µA/µm at an off current of 100 nA/µm with a drain voltage of 1 V, indicating that the current was enhanced by 58% when the Ge concentration was optimized. -
Annual Report
2014 Annual Report NATIONAL ACADEMY OF ENGINEERING ENGINEERING THE FUTURE 1 Letter from the President 3 In Service to the Nation 3 Mission Statement 4 NAE 50th Anniversary Initiatives 5 Program Reports 5 Engineering Education Frontiers of Engineering Education (FOEE) 2- and 4-Year Engineering and Engineering Technology Transfer Student Pilot Barriers and Opportunities in Completing Two- and Four-Year STEM Degrees Engagement of Professional Engineering Societies in Undergraduate Engineering Education Understanding the Engineering Education–Workforce Continuum Engineering Technology Education 8 Technological Literacy LinkEngineering Website 8 Public Understanding of Engineering Media Relations Public Relations Grand Challenges for Engineering 10 Center for Engineering, Ethics, and Society (CEES) Online Ethics Center Expansion Ethics and Sustainability in Engineering Educational Partnership on Climate Change, Engineered Systems, and Society 11 Diversity of the Engineering Workforce EngineerGirl Website 11 Frontiers of Engineering Armstrong Endowment for Young Engineers—Gilbreth Lectures 14 Manufacturing, Design, and Innovation NAE Conference on Value Creation and Opportunity in the United States Making Value for America: Embracing the Future of Manufacturing, Technology, and Work 15 Technology, Science, and Peacebuilding 16 2014 NAE Awards Recipients 18 2014 New Members and Foreign Members 20 NAE Anniversary Members 25 2014 Private Contributions 28 Catalyst Society 28 Rosette Society 29 Challenge Society 29 Charter Society 31 Other Individual -
Ieee-Level Awards
IEEE-LEVEL AWARDS The IEEE currently bestows a Medal of Honor, fifteen Medals, thirty-three Technical Field Awards, two IEEE Service Awards, two Corporate Recognitions, two Prize Paper Awards, Honorary Memberships, one Scholarship, one Fellowship, and a Staff Award. The awards and their past recipients are listed below. Citations are available via the “Award Recipients with Citations” links within the information below. Nomination information for each award can be found by visiting the IEEE Awards Web page www.ieee.org/awards or by clicking on the award names below. Links are also available via the Recipient/Citation documents. MEDAL OF HONOR Ernst A. Guillemin 1961 Edward V. Appleton 1962 Award Recipients with Citations (PDF, 26 KB) John H. Hammond, Jr. 1963 George C. Southworth 1963 The IEEE Medal of Honor is the highest IEEE Harold A. Wheeler 1964 award. The Medal was established in 1917 and Claude E. Shannon 1966 Charles H. Townes 1967 is awarded for an exceptional contribution or an Gordon K. Teal 1968 extraordinary career in the IEEE fields of Edward L. Ginzton 1969 interest. The IEEE Medal of Honor is the highest Dennis Gabor 1970 IEEE award. The candidate need not be a John Bardeen 1971 Jay W. Forrester 1972 member of the IEEE. The IEEE Medal of Honor Rudolf Kompfner 1973 is sponsored by the IEEE Foundation. Rudolf E. Kalman 1974 John R. Pierce 1975 E. H. Armstrong 1917 H. Earle Vaughan 1977 E. F. W. Alexanderson 1919 Robert N. Noyce 1978 Guglielmo Marconi 1920 Richard Bellman 1979 R. A. Fessenden 1921 William Shockley 1980 Lee deforest 1922 Sidney Darlington 1981 John Stone-Stone 1923 John Wilder Tukey 1982 M. -
Lithium-Ion Batteries: Can New Technologies Open up New Horizons? 21 Yoshio Nishi 1
Contents Contributors xv Preface xix 1. Development of the Lithium-Ion Battery and Recent Technological Trends 1 Akira Yoshino 1. Introduction 2 2. Development of the Practical LIB 3 3. Development of Cathode Materials 7 4. Development of Anode Materials 11 5. Development of Electrolyte Solutions 13 6. Separator Technology 15 7. Conclusion 19 2. Past, Present and Future of Lithium-Ion Batteries: Can New Technologies Open up New Horizons? 21 Yoshio Nishi 1. Introduction 22 2. How LIB was Born? 22 3. Performance that Users Expect from LIB 25 4. Improvement of LIB 26 5. Can New Battery Technologies Open up Novel Horizons for LIB? 34 6. Conclusion 38 Nomenclature 38 3. Fast Charging (up to 6C) of Lithium-Ion Cells and Modules: Electrical and Thermal Response and Life Cycle Tests 41 Andrew Burke 1. Introduction 41 v vi Contents 2. General Considerations and Requirements 42 3. Fast Charging Characteristics of Various Lithium Battery Chemistries 44 4. Fast Charging Tests of 50-Ah LTO Cells and Modules 47 4. Nanostructured Electrode Materials for Lithium-Ion Batteries 57 Nicholas S. Hudak 1. Introduction 57 2. Nanoscale Effects in Intercalation-Based Electrode Materials 58 3. Nanostructured Lithium Metal Phosphates for Positive Electrodes 61 4. Titanium-Based Nanomaterials for Negative Electrodes 63 5. Conversion Electrodes 64 6. Lithium Alloys for Negative Electrodes 68 7. Carbon Nanostructures as Active Materials in Negative Electrodes 71 8. Carbon-Based Nanocomposites 75 9. Conclusion 76 5. EVs and HEVs: The Need and Potential Functions of Batteries for Future Systems 83 Hideaki Horie 1. Introduction 83 2.