Microprocessor Theory and Applications with 68000/68020 and Pentium

Total Page:16

File Type:pdf, Size:1020Kb

Microprocessor Theory and Applications with 68000/68020 and Pentium Microprocessor Theory and Applications with 68000/68020 and Pentium M. RAFIQUZZAMAN, Ph.D. Professor California State Polytechnic University Pomona, California and President Rafi Systems, Inc. WILEY A JOHNWILEY & SONS, INC., PUBLICATION This Page Intentionally Left Blank Microprocessor Theory and Applications with 68000/68020 and Pentium This Page Intentionally Left Blank Microprocessor Theory and Applications with 68000/68020 and Pentium M. RAFIQUZZAMAN, Ph.D. Professor California State Polytechnic University Pomona, California and President Rafi Systems, Inc. WILEY A JOHNWILEY & SONS, INC., PUBLICATION Copyright 0 2008 by John Wiley & Sons, Inc. All rights reserved. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 11 1 River Street, Hoboken, NJ 07030, (201) 748-601 1, fax (201) 748- 6008, or online at http://www.wiley.comlgo/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572- 3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic format. For information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data: Rafiquzzaman, Mohamed. Microprocessor theory and applications with 68000/68020 and Pentium / M. Rafiquzzaman. p. cm. Includes bibliographical references and index. ISBN 978-0-470-3803 1-4 (cloth) 1. Motorola 68000 series microprocessors. 2. Pentium (Microprocessor) I. Title. QA76XM6895R34 2008 004.1654~22 2008011009 Printed in the United States of America. 10 9 8 7 6 5 4 3 2 1 To my wge, Kusum; my son, Tito; and my brothel; Elan This Page Intentionally Left Blank CONTENTS PREFACE XI11 CREDITS XV 1. INTRODUCTION TO MICROPROCESSORS 1 1.1 Explanation of Terms 2 1.2 Microprocessor Data Types 4 1.2.1 Unsigned and Signed Binary Numbers 5 1.2.2 ASCII and EBCDIC Codes 7 1.2.3 Unpacked and Packed Binary-Coded-Decimal Numbers 7 1.2.4 Floating-point Numbers 8 1.3 Evolution of the Microprocessor 9 1.4 Typical Features of 32-bit and 64-bit Microprocessors 15 1.5 Microprocessor-based System Design Concepts 16 1.6 Typical Microprocessor Applications 19 1.6.1 A Simple Microprocessor Application 20 1.6.2 Examples of Typical Microprocessor Applications 21 2. MICROCOMPUTER ARCHITECTURE 23 2.1 Basic Blocks of a Microcomputer 23 2.2 Typical Microcomputer Architecture 24 2.2.1 System Bus 24 2.2.2 Clock Signals 25 2.3 Single-Chip Microprocessor 26 2.3.1 Register Section 26 2.3.2 Control Unit 30 2.3.3 Arithmetic-Logic Unit 32 2.3.4 Functional Representations of Simple and Typical Microprocessors 32 2.3.5 Simplified Explanation of Control Unit design 34 2.4 Program Execution by Conventional Microprocessors 38 2.5 Program Execution by typical 32-bit Microprocessors 38 2.5.1 Pipelining 39 2.5.2 Branch Prediction Feature 44 2.6 Scalar and Superscalar Microprocessors 45 2.7 RISC vs. CISC 45 Questions and Problems 47 vii ... Vlll Contents 3. MICROPROCESSOR MEMORY ORGANIZATION 49 3.1 Introduction 49 3.2 Main memory 50 3.2.1 Read-only Memory 51 3.2.2 Random-Access Memory 52 3.2.3 READ and WRITE Timing Diagrams 52 3.2.4 Main Memory Organization 54 3.2.5 Main Memory Array Design 55 3.3 Microprocessor on-chip memory management unit and cache 58 3.3.1 Memory Management Concepts 58 3.3.2 Cache Memory Organization 63 Questions and Problems 68 4. MICROPROCESSOR INPUT/OUTPUT 71 4.1 Introduction 71 4.2 Simple I/O Devices 72 4.3 Programmed I/O 74 4.4 Unconditional and Conditional Programmed I/O 76 4.5 Interrupt I/O 78 4.5.1 Interrupt Types 80 4.5.2 Interrupt Address Vector 80 4.5.3 Saving the Microprocessor Registers 81 4.5.4 Interrupt Priorities 81 4.6 Direct Memory Access (DMA) 84 4.7 Summary of I/O 86 Questions and Problems 87 5. MICROPROCESSOR PROGRAMMING CONCEPTS 89 5.1 Microcomputer Programming Languages 89 5.2 Machine Language 90 5.3 Assembly Language 90 5.3.1 Types of Assemblers 91 5.3.2 Assembler Delimiters 92 5.3.3 Specifying Numbers by Typical Assemblers 93 5.3.4 Assembler Directives or Pseudoinstructions 93 5.3.5 Assembly Language Instruction Formats 95 5.3.6 Instruction Set Architecture (ISA) 97 5.3.7 Typical Instruction Set 98 5.3.8 Typical Addressing Modes 102 5.3.9 Subroutine Calls in Assembly Language 104 5.4 High-Level Language 104 5.5 Choosing a programming language 105 5.6 Flowcharts 106 Questions and Problems 107 6. ASSEMBLY LANGUAGE PROGRAMMING WITH THE 68000 109 6.1 Introduction 109 6.2 68000 Registers 111 6.3 68000 Memory Addressing 112 6.4 Assembly Language Programming with the 68000 113 Contents ix 6.5 68000 Addressing Modes 117 6.5.1 Register Direct Addressing 117 6.5.2 Address Register Indirect Addressing 118 6.5.3 Absolute Addressing 122 6.5.4 Program Counter Relative Addressing 123 6.5.5 Immediate Data Addressing 124 6.5.6 Implied Addressing 125 6.6 68000 Instruction Set 125 6.6.1 Data Movement Instructions 128 6.6.2 Arithmetic Instructions 134 6.6.3 Logic Instructions 150 6.6.4 Shift and Rotate Instructions 152 6.6.5 Bit Manipulation Instructions 156 6.6.6 Binary-Coded-Decimal Instructions 157 6.6.7 Program Control Instructions 160 6.6.8 System Control Instructions 163 6.6.9 68000 Stack 166 6.7 68000 Delay Routine 168 Questions and Problems 170 7. 68000 HARDWARE AND INTERFACING 175 7.1 68000 Pins And Signals 175 7.1.1 Synchronous and Asynchronous Control Lines 177 7.1.2 System Control Lines 179 7.1.3 Interrupt Control Lines 181 7.1.4 DMA Control Lines 181 7.1.5 Status Lines 181 7.2 68000 Clock and Reset Signals 181 7.2.1 68000 Clock Signals 181 7.2.2 68000 Reset Circuit 182 7.3 68000 Read and Write Cycle Timing Diagrams 185 7.4 68000 Memory Interface 188 7.5 68000 I10 192 7.5.1 68000 Programmed I10 192 7.5.2 68000 Interrupt System 201 7.5.3 68000 DMA 206 7.6 68000 Exception Handling 207 7.7 68000/2732/6116/682 1-Based Microcomputer 208 7.8 Multiprocessing with the 68000 Using the TAS Instruction and the AS Signal 212 Questions and Problems 217 8. ASSEMBLY LANGUAGE PROGRAMMING WITH THE 68020 221 8.1 Introduction 22 1 8.2 68020 Functional Characteristics 222 8.3 68020 Registers 225 8.4 68020 Data Types, Organization, and CPU Space Cycle 227 8.5 68020 Addressing Modes 22 8 8.5.1 Address Register Indirect (AM) with Index and 8-Bit Displacement 23 1 8.5.2 ARI with Index (Base Displacement, bd: Value 0 or 16 Bits or 32 Bits) 232 X Contents 8.5.3 Memory Indirect 232 8.5.4 Memory Indirect with PC 233 8.6 68020 Instructions 237 8.6.1 68020 New Privileged Move Instructions 238 8.6.2 Return and Delocate Instruction 238 8.6.3 CHK/CHK2 and CMP/CMP2 Instructions 239 8.6.4 Trap-on-Condition Instructions 243 8.6.5 Bit Field Instructions 245 8.6.6 PACK and UNPK Instructions 247 8.6.7 Multiplication and Division Instructions 250 8.6.8 68000 Enhanced Instructions 254 8.6.9 68020 Subroutines 254 Questions and Problems 256 9. 68020 HARDWARE AND INTERFACING 261 9.1 Introduction 26 1 9.1.1 68020 Pins and Signals 26 1 9.1.2 68020 Dynamic Bus Sizing 265 9.1.3 68020 Timing Diagrams 27 1 9.2 68020 System Design 274 9.2.1 Memory Decode Logic for Memory and VO 275 9.2.2 68020-27C256 Interface 276 9.2.3 68020- 2256C/CH (SRAM) Interface 277 9.2.4 68020 Programmed I/O 279 9.3 68020 Exception processing 282 9.4 68020-based Voltmeter 283 9.4.1 Voltmeter Design Using Programmed I/O 285 9.4.2 Voltmeter Design Using Interrupt I/O 289 9.5 Interfacing a 68020-Based Microcomputer to a Hexadecimal Keyboard and a Seven-Segment Display 293 9.5.1 Basics of Keyboard and Display Interface to a Microcomputer 294 9.5.2 68020 Interface to a Hexadecimal Keyboard and a Seven- Segment Display 296 Questions and Problems 302 10.
Recommended publications
  • Operating RISC: UNIX Standards in the 1990S
    Operating RISC: UNIX Standards in the 1990s This case was written by Will Mitchell and Paul Kritikos at the University of Michigan. The case is based on public sources. Some figures are based on case-writers' estimates. We appreciate comments from David Girouard, Robert E. Thomas and Michael Wolff. The note "Product Standards and Competitive Advantage" (Mitchell 1992) supplements this case. The latest International Computerquest Corporation analysis of the market for UNIX- based computers landed on three desks on the same morning. Noel Sharp, founder, chief executive officer, chief engineer and chief bottle washer for the Superbly Quick Architecture Workstation Company (SQAWC) in Mountain View, California hoped to see strong growth predicted for the market for systems designed to help architects improve their designs. In New York, Bo Thomas, senior strategist for the UNIX systems division of A Big Computer Company (ABCC), hoped that general commercial markets for UNIX-based computer systems would show strong growth, but feared that the company's traditional mainframe and mini-computer sales would suffer as a result. Airborne in the middle of the Atlantic, Jean-Helmut Morini-Stokes, senior engineer for the UNIX division of European Electronic National Industry (EENI), immediately looked to see if European companies would finally have an impact on the American market for UNIX-based systems. After looking for analysis concerning their own companies, all three managers checked the outlook for the alliances competing to establish a UNIX operating system standard. Although their companies were alike only in being fictional, the three managers faced the same product standards issues. How could they hasten the adoption of a UNIX standard? The market simply would not grow until computer buyers and application software developers could count on operating system stability.
    [Show full text]
  • I.T.S.O. Powerpc an Inside View
    SG24-4299-00 PowerPC An Inside View IBM SG24-4299-00 PowerPC An Inside View Take Note! Before using this information and the product it supports, be sure to read the general information under “Special Notices” on page xiii. First Edition (September 1995) This edition applies to the IBM PC PowerPC hardware and software products currently announced at the date of publication. Order publications through your IBM representative or the IBM branch office serving your locality. Publications are not stocked at the address given below. An ITSO Technical Bulletin Evaluation Form for reader′s feedback appears facing Chapter 1. If the form has been removed, comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JLPC Building 014 Internal Zip 5220 1000 NW 51st Street Boca Raton, Florida 33431-1328 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. Copyright International Business Machines Corporation 1995. All rights reserved. Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Abstract This document provides technical details on the PowerPC technology. It focuses on the features and advantages of the PowerPC Architecture and includes an historical overview of the development of the reduced instruction set computer (RISC) technology. It also describes in detail the IBM Power Series product family based on PowerPC technology, including IBM Personal Computer Power Series 830 and 850 and IBM ThinkPad Power Series 820 and 850.
    [Show full text]
  • White Paper Northforge Innovations Inc
    Modern Packet Switch Design White Paper Northforge Innovations Inc. September 2016 1 Introduction This white paper surveys the architectural evolution of Ethernet packet switches, featuring an overview of early packet switch design and the forces that have driven modern design solutions. These forces, which include increased interface speed, increased number of ports, Software-Defined Networking (SDN), Deep Packet Inspection (DPI), and Network Functions Virtualization (NFV) have had a major impact on the architecture and design of modern packet switches. All Packet Switches Are Divided Into Three Parts The networking industy has been building LAN-based packet switches (including under this rubric, LAN Bridges, MPLS Switches, and IP Routers) since the early-mid 1980s. The three functional components of a packet switch have been stable since the beginning. • Data plane – The primary job of a packet switch is to move packets from an input interface to an output interface. Moving the data from input to output is the job of the data plane (sometimes called the forwarding plane). • Control plane – The data plane decides which output port to select for each arriving packet based on a set of tables that are built by the control plane. For an Ethernet Switch, the control plane includes the process that learns MAC addresses, the spanning tree protocol, etc. For an IP router, the control plane includes the various IP routing protocols (e.g., OSPF and IS-IS). • Management plane – All packet switches require some configuration. In addition, they include mechanisms for fault detection and reporting, statistics collection, and troubleshooting. This is all done by the management plane.
    [Show full text]
  • A Brief History of Debian I
    A Brief History of Debian i A Brief History of Debian A Brief History of Debian ii 1999-2020Debian Documentation Team [email protected] Debian Documentation Team This document may be freely redistributed or modified in any form provided your changes are clearly documented. This document may be redistributed for fee or free, and may be modified (including translation from one type of media or file format to another or from one spoken language to another) provided that all changes from the original are clearly marked as such. Significant contributions were made to this document by • Javier Fernández-Sanguino [email protected] • Bdale Garbee [email protected] • Hartmut Koptein [email protected] • Nils Lohner [email protected] • Will Lowe [email protected] • Bill Mitchell [email protected] • Ian Murdock • Martin Schulze [email protected] • Craig Small [email protected] This document is primarily maintained by Bdale Garbee [email protected]. A Brief History of Debian iii COLLABORATORS TITLE : A Brief History of Debian ACTION NAME DATE SIGNATURE WRITTEN BY September 14, 2020 REVISION HISTORY NUMBER DATE DESCRIPTION NAME A Brief History of Debian iv Contents 1 Introduction -- What is the Debian Project? 1 1.1 In the Beginning ................................................... 1 1.2 Pronouncing Debian ................................................. 1 2 Leadership 2 3 Debian Releases 3 4 A Detailed History 6 4.1 The 0.x Releases ................................................... 6 4.1.1 The Early Debian Packaging System ..................................... 7 4.2 The 1.x Releases ................................................... 7 4.3 The 2.x Releases ................................................... 8 4.4 The 3.x Releases ................................................... 8 4.5 The 4.x Releases ..................................................
    [Show full text]
  • Microprocessors: from Basic Chips to Complete Systems
    - 237 - MICROPROCESSORS: FROM BASIC CHIPS TO COMPLETE SYSTEMS R. W. Dobinson,*) University of Illinois, Urbana, Illinois, USA. "Good-morning, good morning!", the General said When we met him last week on our way to the line. Now the soldiers he smiled at are most of them dead, And we're cursing his staff for Incompetent swine. "He's a cheery old card," grunted Harry to Jack As they slogged up to Arras with rifle and pack. * * * * But he did for them both by his plan of attack. Siegfried Sassoon April 1917 1. AIMS OF THESE LECTURES Microprocessor technology has, since its conception and birth in the early 1970's, entered very many areas of our lives. No end to its growth is in sight, and new uses appear almost daily. The semiconductor industry continues to produce ever more powerful integrated circuits (known far and wide as chips); more functionality and speed at lower cost is every salesman's cry. These lectures aim to present and explain in general terms some of the characteristics of microprocessor chips and associated components. They will show how systems are synthesized from the basic integrated circuit building blocks which are currently available; processor, memory, input-output (I/O) devices, etc. It is not my intention to discuss in detail the many different microprocessors now available on the market, nor will a complete catalogue of support chips be presented. Time will not permit this. Instead, emphasis will be placed on explaining the basic principles of different types of chip. As far as possible X will avoid talking too much about any specific devices; thus I will spend some time discussing a generic microprocessor accessing generic memory and talking to the outside world via generic I/O devices.
    [Show full text]
  • Experimental Verification of Mission Planning by Autonomous Mission Execution and Data Visualization Using the NPS AUV II
    View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Calhoun, Institutional Archive of the Naval Postgraduate School Calhoun: The NPS Institutional Archive Faculty and Researcher Publications Faculty and Researcher Publications 1992 Experimental verification of mission planning by autonomous mission execution and data visualization using the NPS AUV II Healey, A.J. http://hdl.handle.net/10945/44824 EXPERIMENT AL VERIFICATION OF MISSION PLANNING BY AUTONOMOUS MISSION EXECUTION AND DATA YISUALIZATION USING THE NPS AUV II A. J. Healey, D. B. Marco Naval Postgraduate School Monterey, Calif. 93943 (408)-646-2586 (Phone) (408)-646-2238 (Fax) ABSTRACT University of Tokyo has recently developed an underwater vehicle for bottom contour following using neural network techniques This paper describes recent results in mission execution, and (Ura, 1990). At the Nava! Postgra?uate School, we have developed post mission data analysis from the NPS AUV II testbed underwater an ~nderwater testbed :<eh1cle that 1s specifically designed to test and vehicle. Ongoing research is focused on control technology to meet very.fy ~evelopments m control technology. It is run in the NPS the needs of future Naval Autonomous Underwater Vehicles. These sw1mmmg. pool . as an environment for experimental mission vehicle~ are unmanned, untethered, free swimming, robotic demonstrauon usmg a GESPAC computer with a Motorola 68030 submannes to be used for Naval missions including search, C~U. a 2MByt~ R~M card with control code written in "C". The mapping, surveillance, and intervention activity. The approach m1ss1oi: pl~nmng 1_nterface with the vehicle control computer is taken at NPS combines integrated computer simulation, real time e~b?d1ed m_a <;JR1DCASE laptop M~-DOS machine containing rob~st control theory, computer architecture and code development, rmss_10n details m the form of way pomts and run times that are vehicle and component design and experimentation, sonar data obtamed from an external pre-mission planning analysis.
    [Show full text]
  • The Definitive Guide to GCC
    The Definitive Guide to GCC KURT WALL AND WILLIAM VON HAGEN APress Media, LLC The Definitive Guide to GCC Copyright ©2004 by Kurt Wall and William von Hagen Originally published by Apress in 2004 All rights reserved. No part of this work may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage or retrieval system, without the prior written permission of the copyright owner and the publisher. ISBN 978-1-59059-109-3 ISBN 978-1-4302-0704-7 (eBook) DOI 10.1007/978-1-4302-0704-7 Trademarked names may appear in this book. Rather than use a trademark symbol with every occurrence of a trademarked name, we use the names only in an editorial fashion and to the benefit of the trademark owner, with no intention of infringement of the trademark. Technical Reviewer: Gene Sally Editorial Board: Steve Anglin, Dan Appleman, Gary Cornell, James Cox, Tony Davis, John Franklin, Chris Mills, Steven Rycroft, Dominic Shakeshaft, Julian Skinner, Martin Streicher, Jim Sumser, Karen Watterson, Gavin Wray, John Zukowski Assistant Publisher: Grace Wong Project Manager: Sofia Marchant Copy Editor: Ami Knox Production Manager: Kari Brooks Production Editor: Janet Vaii Proofreader: Elizabeth Berry Compositor and Artist: Kinetic Publishing Services, llC Indexer: Valerie Perry Cover Designer: Kurt Krames Manufacturing Manager: Tom Debolski The information in this book is distributed on an "as is" hasis, without warranty. Although every precaution bas been taken in the preparation of this work, neither the author(s) nor Apress shall have any liability to any person or entity with respect to any loss or damage caused or alleged to be caused directly or indirectly by the information contained in this work.
    [Show full text]
  • Gnu Assembler
    Using as The gnu Assembler (Sourcery G++ Lite 2010q1-188) Version 2.19.51 The Free Software Foundation Inc. thanks The Nice Computer Company of Australia for loaning Dean Elsner to write the first (Vax) version of as for Project gnu. The proprietors, management and staff of TNCCA thank FSF for distracting the boss while they gotsome work done. Dean Elsner, Jay Fenlason & friends Using as Edited by Cygnus Support Copyright c 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled \GNU Free Documentation License". i Table of Contents 1 Overview :::::::::::::::::::::::::::::::::::::::: 1 1.1 Structure of this Manual :::::::::::::::::::::::::::::::::::::: 14 1.2 The GNU Assembler :::::::::::::::::::::::::::::::::::::::::: 15 1.3 Object File Formats::::::::::::::::::::::::::::::::::::::::::: 15 1.4 Command Line ::::::::::::::::::::::::::::::::::::::::::::::: 15 1.5 Input Files :::::::::::::::::::::::::::::::::::::::::::::::::::: 16 1.6 Output (Object) File:::::::::::::::::::::::::::::::::::::::::: 16 1.7 Error and Warning Messages :::::::::::::::::::::::::::::::::: 16 2 Command-Line Options::::::::::::::::::::::: 19 2.1 Enable Listings: `-a[cdghlns]'
    [Show full text]
  • Advanced Embedded Systems
    Advanced Embedded Systems | Punit Narang | Manoj Gulati | Sourabh Sankule | P a g e | i Contents Chapter 1 - Introduction to Embedded Electronics ........................................................................... 1 1.1 Embedded System .................................................................................................................. 1 1.1.1 Example of Embedded System ........................................................................................ 2 1.1.2 Characteristics ................................................................................................................. 3 1.1.3 User interface .................................................................................................................. 3 1.1.4 Processors in embedded systems ................................................................................... 4 1.1.5 Peripherals ...................................................................................................................... 4 1.2 Microcontrollers...................................................................................................................... 4 1.2.1 What is a Microcontroller? ............................................................................................. 4 1.2.2 Microcontrollers vs. Microprocessors ............................................................................ 5 1.2.3 Development/Classification of microcontrollers (Invisible) ........................................... 5 1.2.4 Development of microprocessors
    [Show full text]
  • The Definitive Guide to GCC Second Edition
    The Definitive Guide to GCC Second Edition ■■■ William von Hagen The Definitive Guide to GCC, Second Edition Copyright © 2006 by William von Hagen All rights reserved. No part of this work may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage or retrieval system, without the prior written permission of the copyright owner and the publisher. ISBN-13 (pbk): 978-1-59059-585-5 ISBN-10 (pbk): 1-59059-585-8 Printed and bound in the United States of America 9 8 7 6 5 4 3 2 1 Trademarked names may appear in this book. Rather than use a trademark symbol with every occurrence of a trademarked name, we use the names only in an editorial fashion and to the benefit of the trademark owner, with no intention of infringement of the trademark. Lead Editors: Jason Gilmore, Keir Thomas Technical Reviewer: Gene Sally Editorial Board: Steve Anglin, Ewan Buckingham, Gary Cornell, Jason Gilmore, Jonathan Gennick, Jonathan Hassell, James Huddleston, Chris Mills, Matthew Moodie, Dominic Shakeshaft, Jim Sumser, Keir Thomas, Matt Wade Project Manager: Richard Dal Porto Copy Edit Manager: Nicole LeClerc Copy Editor: Jennifer Whipple Assistant Production Director: Kari Brooks-Copony Production Editor: Katie Stence Compositor: Susan Glinert Proofreader: Elizabeth Berry Indexer: Toma Mulligan Artist: April Milne Cover Designer: Kurt Krames Manufacturing Director: Tom Debolski Distributed to the book trade worldwide by Springer-Verlag New York, Inc., 233 Spring Street, 6th Floor, New York, NY 10013. Phone 1-800-SPRINGER, fax 201-348-4505, e-mail [email protected], or visit http://www.springeronline.com.
    [Show full text]
  • Gnu Assembler
    Using as The gnu Assembler January 1994 The Free Software Foundation Inc. thanks The Nice Computer Company of Australia for loaning Dean Elsner to write the first (Vax) version of as for Project gnu. The proprietors, management and staff of TNCCA thank FSF for distracting the boss while they got some work done. Dean Elsner, Jay Fenlason & friends Using as Edited by Cygnus Support Copyright c 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies. Permission is granted to copy and distribute modified versions of this manual under the con- ditions for verbatim copying, provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one. Permission is granted to copy and distribute translations of this manual into another lan- guage, under the above conditions for modified versions. Chapter 1: Overview 1 1 Overview This manual is a user guide to the gnu assembler as. Here is a brief summary of how to invoke as. For details, see Chapter 2 [Comand-Line Options], page 9. as [ -a[cdhlns][=file] ] [ -D ] [ --defsym sym=val ] [ -f ] [ --gstabs ] [ --help ] [ -I dir ] [ -J ] [ -K ] [ -L ] [ --keep-locals ] [ -o objfile ] [ -R ] [ --statistics ] [ -v ] [ -version ] [ --version ] [ -W ] [ -w ] [ -x ] [ -Z ] [ -mbig-endian | -mlittle-endian ] [ -m[arm]1 | -m[arm]2 | -m[arm]250 | -m[arm]3 | -m[arm]6 | -m[arm]7[t][[d]m[i]] ] [ -m[arm]v2 | -m[arm]v2a | -m[arm]v3 | -m[arm]v3m | -m[arm]v4 | -m[arm]v4t ] [ -mthumb | -mall ] [ -mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu ] [ -EB | -EL ] [ -mapcs-32 | -mapcs-26 ] [ -O ] [ -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite -Av8plus | -Av8plusa | -Av9 | -Av9a ] [ -xarch=v8plus | -xarch=v8plusa ] [ -bump ] [ -32 | -64 ] [ -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC ] [ -b ] [ -no-relax ] [ -l ] [ -m68000 | -m68010 | -m68020 | ..
    [Show full text]
  • LCSH Section Numerals
    0 (Group of artists) 1c Magenta (Stamp) 2e children USE Zero (Group of artists) USE British Guiana One-Cent Magenta (Stamp) USE Twice-exceptional children 0⁰ latitude 1I (Interstellar object) 2nd Avenue (Manhattan, New York, N.Y.) USE Equator USE ʻOumuamua (Interstellar object) USE Second Avenue (Manhattan, New York, N.Y.) 0⁰ meridian 1I/2017 U1 (Interstellar object) 2nd Avenue (Seattle, Wash.) USE Prime Meridian USE ʻOumuamua (Interstellar object) USE Second Avenue (Seattle, Wash.) 0-1 Bird Dog (Reconnaissance aircraft) 1I/ʻOumuamua (Interstellar object) 2nd Avenue West (Seattle, Wash.) USE Bird Dog (Reconnaissance aircraft) USE ʻOumuamua (Interstellar object) USE Second Avenue West (Seattle, Wash.) 0th law of thermodynamics 1P/ Halley (Comet) 2nd law of thermodynamics USE Zeroth law of thermodynamics USE Halley's comet USE Second law of thermodynamics 1,000 Year Monument (Novgorod, Russia) 1st Avenue (Seattle, Wash.) 2P/Encke (Comet) USE Tysi︠a︡cheletie Rossii (Novgorod, Russia) USE First Avenue (Seattle, Wash.) USE Encke comet 1,4-beta-D-glucan cellobiohydrolase 1st Avenue West (Seattle, Wash.) 2U 2030+40 (Astronomy) USE Cellulose 1,4-beta-cellobiosidase USE First Avenue West (Seattle, Wash.) USE Cygnus X-3 1 1/2 Strutter (Military aircraft) 1st century, A.D. 3-(1-piperazino)benzotrifluoride USE Sopwith 1 1/2 Strutter (Military aircraft) USE First century, A.D. USE Trifluoromethylphenylpiperazine 1-2 Montague Place (London, England) 1st Hill Park (Seattle, Wash.) 3.1 Tongnip Sŏnŏn Kinyŏmtʻap (Seoul, Korea) BT Office buildings—England
    [Show full text]